Semiconductor device and semiconductor module apparatus

Abstract

A semiconductor device includes: an insulator substrate; a second substrate disposed at a first surface of the insulator substrate; a first structured metallization layer disposed at a second surface of the insulator substrate opposite the first surface, the first structured metallization layer comprising a first portion configured to operate at a first potential and a second portion configured to operate at a second potential; the insulator substrate comprises: a second structured metallization layer buried in the insulator substrate and configured for EMI shielding, arranged adjacent to the second substrate and comprising: a first portion coupled to the first potential; a second portion coupled to the second potential, where the first portion and the second portion do not overlap; and at least one routable third structured metallization layer, the at least one routable third structured metallization layer comprising: a first section coupled to the second potential; a second section, the second section being coupled to the first potential; wherein the first part of the second structured metallization layer and the first section of the third structured metallization layer form a first buffer capacitor.

Description

Technical Field

[0001] This disclosure relates to a low-EMI semiconductor device comprising: an insulating substrate; a second substrate disposed at a first surface of the insulating substrate; and a first structured metallization layer disposed at a second surface of the insulating substrate opposite to the first surface, the first structured metallization layer including a first portion configured to operate at a first potential and a second portion configured to operate at a second potential, wherein the insulating substrate includes a second structured metallization layer buried within the insulating substrate, the second structured metallization layer being configured for EMI shielding and disposed adjacent to the second substrate. Background Technology

[0002] In today's power modules, low inductance and symmetrical design are goals, and these designs are particularly crucial for the operation of fast-switching devices. Within this framework, the main motivations for employing low inductance and symmetrical design are: to primarily reduce overvoltage and achieve extremely steep di / dt and dv / dt characteristics through low inductance design; to primarily reduce inter-chip oscillations and minimize parasitic effects during operation through symmetrical design; and to primarily reduce electromagnetic interference (EMI) through symmetrical design.

[0003] Many attempts have been made to effectively reduce parasitic effects through low inductance and symmetrical designs.

[0004] Regarding EMI, for example, it is known from DE 102013210146 A1 that an electrically connected metal plate placed between a first plane and a second plane of a substrate can have a positive effect on (conducted) EMI. In this arrangement, the first plane is used to house power semiconductor devices, their interconnection structures, and layout components. The second plane is typically connected to a heat sink and therefore to the potential of the typically grounded heat sink.

[0005] According to DE 102013210146 A1, in the case of a half-bridge module, in order to achieve the best electromagnetic interference protection effect, the internal shielding structure should be designed such that the first element of the electrical connection metal plate has the same coupling capacitance as the second element of the electrical connection metal plate that abuts the substrate on the second plane.

[0006] An electrical connection can be established between the inner shielding elements of the first substrate plane and the third plane to ensure that the internal elements have the correct potential when electrically coupled to the second plane.

[0007] To effectively reduce EMI, the first element of the electrical connection metal plate can be connected to the positive potential of the DC link voltage (DC+), and the second element of the electrical connection metal plate can be connected to the negative potential of the DC link voltage (DC-).

[0008] However, it is also desirable to implement the function of a buffer capacitor. This is typically achieved by mounting surface mount devices (SMDs) (e.g., external capacitors) on top or bottom of the substrate of the power module. However, common drawbacks of SMDs are that they occupy the area required for mounting semiconductor devices, generate localized heat, and interact with adjacent components (e.g., with potting compound or semiconductors).

[0009] Therefore, it is hoped that the above-mentioned defects can be overcome. Summary of the Invention

[0010] According to a first aspect of this disclosure, a semiconductor device of the aforementioned type is provided, wherein a second structured metallization layer includes a first portion coupled to a first potential and a second portion coupled to a second potential, wherein the first portion and the second portion do not overlap. The insulating substrate further includes at least one wireable third structured metallization layer, which includes a first segment coupled to the second potential and a second segment coupled to the first potential. The first portion of the second structured metallization layer and the first segment of the third structured metallization layer form a first buffer capacitor.

[0011] According to embodiments of this disclosure, passive components are implemented in an insulator substrate in which the second substrate can be separated from the first metallization layer to reduce electromagnetic interference / emissions, and additional buffer capacitor functionality is provided at the power module level without using layout areas of passive components (similar to SMD) in the first metallization layer. To achieve a basic buffer capacitor within the insulator substrate, a first buffer capacitor is formed between a first portion of the second metallization layer and a first segment of the third structured metallization layer, wherein the material of the insulator substrate acts as a dielectric located between them.

[0012] The first and second portions of the second metallization layer do not overlap and together with the second substrate form a shielding capacitor. The second substrate may be a metallic substrate or typically a conductive substrate. The first and second portions of the second metallization layer may be spaced apart from the second substrate by a material of an insulating substrate, wherein the material of the insulating substrate forms a dielectric for the shielding capacitor. A first segment of the third structured metallization layer may be disposed between the second and first metallization layers within the insulating substrate. Thus, the material of the insulating substrate forms a dielectric between monolayers of each of the second and first metallization layers. The first segment of the third structured metallization layer overlaps with the first portion of the second structured metallization layer and is spaced apart from the first portion of the second structured metallization layer by a material of the insulating substrate, thereby forming a first buffer capacitor.

[0013] It should be noted that the term "structured metallization layer" can refer to a layer with different portions / segments in essentially the same plane. These portions / segments can be separated from each other, linked together, or electrically isolated. Different segments of a structured metallization layer can have different functionalities. Specifically, a buffer capacitor is a DC buffer capacitor used to reduce electromagnetic interference and / or emissions. Buffer capacitors can be a type of capacitor used in circuits to reduce voltage spikes, ringing, and electromagnetic interference (EMI) caused by switching of inductive loads such as relays, solenoids, and motors.

[0014] In one embodiment, a second portion of the second structured metallization layer and a second segment of the third structured metallization layer form a second buffer capacitor. The second buffer capacitor is implemented in this manner because the second portion of the second structured metallization layer is spaced from the second segment of the third structured metallization layer by the material of the insulating substrate. Similar to the first buffer capacitor, the second buffer capacitor is formed inside the insulating substrate and disposed between the second metallization layer and the first metallization layer. Each of the first and second buffer capacitors can be connected to a corresponding switch.

[0015] In one embodiment, the third structured metallization layer includes multiple wireable layers that form an interlocking layer structure alternately coupled to a first potential and a second potential, thereby forming multiple stacked buffer capacitors within the insulating substrate. To form the multiple stacked buffer capacitors, the third structured metallization layer may include multiple layers. To form the buffer capacitors, the multiple layers may be alternately coupled to the first potential and the second potential.

[0016] The individual layers of the plurality of layers can be spaced apart from each other by a material of an insulating substrate that acts as a dielectric to form a corresponding buffer capacitor. The layer structures can be stacked and / or interlocked, i.e., at least partially overlapping. In contrast to the second metallization layer, which includes non-overlapping layers, the plurality of layers of the third metallization layer need to at least partially overlap each other. By stacking multiple layers inside the insulating substrate, a stacked capacitor is generated inside the insulating substrate. The capacitor may include layers that are symmetrically stacked inside the insulating substrate and / or layers that are asymmetrically arranged inside the insulating substrate. Therefore, the total capacitance inside the insulating substrate can be adapted to possible asymmetries in the switching speed of the semiconductor device coupled to the buffer capacitor.

[0017] Specifically, multiple interlocking layer structures are embedded in the first insulating substrate and arranged between the first structured metallization layer and the second structured metallization layer.

[0018] Furthermore, the interlocking layer structures alternately overlap each other and form a plate capacitor structure inside the first insulating substrate.

[0019] In embodiments, the insulating substrate is one of a multilayer ceramic substrate, a multilayer PCB, or a multilayer resin-based substrate. The insulating substrate can be any suitable substrate made of an insulating material. According to embodiments of this disclosure, multilayer ceramic substrates integrated into power semiconductor modules are used in a manner that allows passive components to be integrated / embedded within / as a functional portion of the multilayer ceramic substrate.

[0020] Compared to common methods of using a first structured metallization layer for attaching passive components, such as by soldering SMD-like devices onto a copper surface, this disclosure offers several advantages, which will be described in detail below.

[0021] First, integrating passive components within the inner / buried layer of the insulating substrate saves the area at the first structured metallization layer, which can be used to alternatively attach / mount power semiconductor devices.

[0022] Secondly, by optimizing the heat generation of passive components within the internal / buried layer, heat is not confined to a localized area as in surface-mount devices, and more efficient heat dissipation is achieved due to the large heat dissipation area. In other words, the insulating substrate can act as a heat sink.

[0023] Third, by embedding passive components or the functionality of passive components within the multilayer ceramic substrate, the interaction between passive components and other components (e.g., potting compound and / or edge terminals of power semiconductors) is minimized. Therefore, failures in reliability testing can be avoided or at least reduced.

[0024] Therefore, in another embodiment, a first portion of the first structured metallization layer is configured to accommodate a first semiconductor die, and a second portion of the first structured metallization layer is configured to accommodate a second semiconductor die. The first metallization layer may also be a wiring layer to which the first and second semiconductor dies are attached (i.e., at least electrically and / or thermally coupled). Both the first and second semiconductor dies may be IGBTs, Si / SiC-MOSFETs, JFETs, GaN-HEMTs, or any other transistor dies.

[0025] In this embodiment, the second substrate is a conductive substrate, and the second structured metallization layer is arranged adjacent to the second substrate but isolated from it by the lowermost portion of the insulating substrate. Therefore, each portion of the second structured metallization layer can form an EMI shielding capacitor together with the second substrate. From an electromagnetic interference perspective, these internal shielding structures (i.e., the second metallization layer) are most effective if designed such that the first portion of the second metallization layer and the second portion of the second metallization layer abutting the second substrate have the same coupling capacitance.

[0026] Specifically, the second substrate can form the substrate of the device and can be connected to ground potential and configured to be attached to a heat sink. The substrate can be a heat-conducting plate and / or a conductive plate configured to be attached to the heat sink by, for example, screws, clips, diffusion soldering, soldering or sintering.

[0027] In an embodiment, the first structured metallization layer includes a third portion electrically isolated from both the first and second portions of the first structured metallization layer, wherein the third portion is configured to operate under alternating potentials. For example, in a half-bridge arrangement, depending on the switching states of the first and / or second switches, nodes in the coupling portion between the high-side and low-side switches operate under alternating potentials.

[0028] In one embodiment, the insulating substrate includes a wiring layer disposed between a third structured metallization layer and a first metallization layer. The wiring layer may be part of a stack of buffer capacitors, but may also be a separate portion.

[0029] The wiring layer can also be referred to as a distribution layer. Advantageously, the wiring layer can be the first layer seen from the top side of a layer stack in an insulating substrate. The wiring layer can be a metallization layer configured to transmit an input signal in a corresponding plane from one part of the plane to another part of the plane. For example, the wiring layer can connect an opposite portion of a second metallization layer to a corresponding potential. Thus, internal potential transmission is possible.

[0030] In an embodiment, a first portion of the second structured metallization layer has a first surface area, and a second portion has a second surface area substantially equal to the first surface area, and / or wherein the first and second portions are substantially in the same plane. Therefore, the EMI shielding capacitances are substantially equal because they have substantially the same occupied area. For most effective EMI reduction, the first portion of the second structured metallization layer may be connected to the positive potential of the DC link voltage (first potential, DC+), and the second portion of the second structured metallization layer may be connected to the negative potential of the DC link voltage (second potential, DC-).

[0031] In this embodiment, the second surface area is less than 1 / 0.95 of the first surface area and greater than 1 / 1.05 of the first surface area. The surface area of ​​the metallization layer can be considered as the maximum orthogonal projection of the region onto a plane. By using the ratio of the first and second surface areas described above, the radiated EMI of the semiconductor device can be significantly reduced.

[0032] In one embodiment, the interlocking layer structure forms one or more gate-source capacitors to reduce oscillations during switching of one or more semiconductor dies. The interlocking layer structure can also serve as a gate-source capacitor, where, in this embodiment, the capacitor is coupled to a first potential that is the gate potential. The capacitor is coupled to a second potential that is the source potential. If there is more than one semiconductor switch, each semiconductor switch may require a separate capacitor within the insulating substrate. For example, if there are n semiconductor switches, n-1 gate-source capacitors may be required to adapt the n-1 semiconductor switches to a first reference semiconductor switch. The gate potential and source potential of each semiconductor switch are then electrically coupled to a corresponding capacitor within the multilayer substrate.

[0033] To compensate for switching asymmetry, i.e., the difference in switching speed between corresponding semiconductor switches, the corresponding gate-source capacitance within the insulator substrate can also be asymmetric. In other words, the gate-source capacitance can be adapted to the switching speed of the corresponding semiconductor switch. Differences in switching speed may arise, for example, from different thermal conditions or asymmetries in the control circuitry of the semiconductor switch.

[0034] In this embodiment, the engagement layer structure forms one or more external Miller capacitors. In this embodiment, corresponding capacitors within the insulator substrate can also be connected to the gate and collector potentials of the respective switches. Therefore, each switch can be connected to a spoke capacitor network to compensate for differences in switching speeds. Thus, differences in switching speeds can be compensated by connecting the respective switches to specific capacitors.

[0035] According to a second aspect of this disclosure, a semiconductor module device is provided, the device including an insulating substrate, a second conductive substrate attached to the insulating substrate, the insulating substrate including at least one EMI shielding layer, and an engagement layer structure configured to serve as stacked buffer capacitors. Attached Figure Description

[0036] Exemplary embodiments of this disclosure are described with reference to the following figures: Figures 1a-1c show different views of schematic semiconductor devices in the prior art.

[0037] Figure 2a shows a schematic diagram of a semiconductor device according to the present disclosure.

[0038] Figure 2b shows a schematic diagram of a semiconductor device according to the present disclosure.

[0039] Figure 2c shows a schematic diagram of the internal capacitance of an exemplary semiconductor device according to the present disclosure.

[0040] Figure 3 A sketch of possible constructions of a multilayer ceramic substrate and its different planes is shown.

[0041] Figure 4 It shows that it has the following characteristics: Figure 3 The cross-section of the structured multilayer ceramic substrate showing the internal shielding elements and DC buffer capacitor stack structure. Detailed Implementation

[0042] In the following detailed description, reference will be made to the accompanying drawings. The drawings illustrate specific examples in which the invention can be practiced. It should be understood that, unless otherwise specifically indicated, the features and principles described with respect to the various examples can be combined with each other. And in the claims, the designation of certain elements as "first element," "second element," "third element," etc., should not be construed as exhaustive. Rather, these designations are used only to refer to different "elements." That is, for example, the presence of a "third element" does not require the presence of a "first element" and a "second element." The wire described herein can be a single conductive element or comprise at least two separate conductive elements connected in series and / or in parallel. The wire may comprise metallic and / or semiconductor materials and may be permanently conductive (i.e., non-switchable). The wire may have a resistivity independent of the direction of the current flowing through it. The semiconductor body described herein may be made of (doped) semiconductor material and may be a semiconductor chip or included in a semiconductor chip. The semiconductor body has electrically connected pads and includes at least one semiconductor element having electrodes. The pads are electrically connected to the electrodes, meaning that the pads are electrodes, and vice versa.

[0043] Referring to Figure 1a (prior art), a semiconductor device 1 including an EMI shielding structure 2 is shown. The semiconductor device 1 includes a first switch 3 and a second switch 4. The first switch 3 is a high-side switch. The second switch 4 is a low-side switch. The first switch 3 and the second switch 4 form a half-bridge device 5.

[0044] Semiconductor device 1 also includes a substrate 6, which can be connected to ground potential. Semiconductor device 1 also includes an insulating substrate 7. An EMI shielding structure 2 is contained in the insulating substrate 7. The insulating substrate 7 is connected to the substrate 6, which can be a second substrate. A high-side switch 3 is connected to a first potential 8 and coupled in series with a low-side switch 4. The low-side switch 4 can be coupled to a second potential 9. The portion between the first switch 3 and the second switch 4 may include a node 10, which is configured to operate at either a first potential or a second potential (i.e., in an alternating potential AC) depending on the switching states of the first switch 3 and the second switch 4.

[0045] The EMI shielding structure 2 is buried in the insulating substrate 7. The EMI shielding structure 2 includes a first EMI shielding capacitor C+ and a second EMI shielding capacitor C-. The first EMI shielding capacitor C+ is disposed between the substrate 6 and a first potential, and is connected, for example, to the positive potential (DC+) of the DC link voltage. The second EMI shielding capacitor C- is disposed between the substrate 6 and a second potential, and is connected, for example, to the negative potential (DC-) of the DC link voltage.

[0046] For effective EMI shielding, the first EMI shielding capacitor C+ and the second EMI shielding capacitor C have approximately the same capacitance.

[0047] Figure 1b (Prior Art) shows an external view of a semiconductor device 1, wherein a substrate 6 is disposed on an insulating substrate 7. The insulating substrate 7 includes a first surface 11 and a second surface 12 opposite to the first surface 11. The substrate 6 is disposed on the second surface 12 of the insulating substrate 7. A first metallization layer 13, as a structured layer, is disposed on the first surface 11 of the insulating substrate 7. The first metallization layer 13 includes a first portion 14 configured to operate under a first potential 8. The first metallization layer 13 includes a second portion 15 configured to operate under a second potential 9. Furthermore, the first metallization layer 13 includes nodes 10 configured to operate under alternating potentials.

[0048] The EMI shielding structure 2 is buried inside the insulating substrate 7 and is therefore invisible.

[0049] Figure 1c shows a schematic diagram of a capacitor included in a semiconductor device 1 according to the prior art. Figure 1c illustrates several alternative embodiments, particularly relating to a third EMI shielding capacitor C disposed between node 10 and substrate 6. AC Regarding the first EMI shielding capacitor and the second EMI shielding capacitor, the first metallization layer 13 (that is, the first part 14 and the second part 15 of the first metallization layer 13) together with the substrate 6 forms the EMI shielding capacitors C+ and C-.

[0050] Option 1 illustrates a second semiconductor switch 4 disposed at a third portion 16 of the first metallization layer 13. The third portion 16 of the first metallization layer 13 forms a node 10 operating under an alternating potential AC. For example, node 10 is electrically coupled to the load electrode of the first switch 3 via a bonding wire 17. Furthermore, node 10 is electrically coupled to the load electrode of the second switch 4. According to the first option, a capacitor is formed between node 10 operating under the alternating potential and the substrate 6, wherein the insulating substrate 7 acts as the dielectric.

[0051] Option 2 shows the implementation of the third EMI shielding capacitor C. ACFurther possibilities. A capacitor stack 18 is disposed on top of a second portion of the first metallization layer 13. The capacitor stack 18 includes a lower conductive layer 19, an insulating material 20, and an upper conductive layer 21. The insulating material 20 is sandwiched between the lower conductive layer 19 and the upper conductive layer 21. A second semiconductor switch 4 is disposed on top of the capacitor stack 18 and is bonded, soldered, sintered, or electrically connected in any way to the upper conductive layer 21.

[0052] A capacitor stack 18 is disposed between the second semiconductor switch 4 and the second portion 15 of the first metallization layer 13. The second semiconductor switch 4 is electrically connected to the upper conductive layer 21 via one of its load electrodes. The upper conductive layer 21 is connected to the load electrode of the first semiconductor switch 3 via bonding wire 17. Therefore, the upper conductive layer 21 is configured to operate under alternating potentials. In this embodiment, the upper conductive layer 21 functions as node 10. Subsequently, the capacitor stack 18 forms a third EMI shielding capacitor C. AC .

[0053] Figure 2a shows a schematic diagram of a semiconductor device 1 according to the present disclosure. A substrate 6 is disposed on the underside of an insulating substrate 7. A first metallization layer 13 is disposed on the upper side of the insulating substrate 7. The first metallization layer 13 is structured, that is, it includes a first portion 14 configured to operate under a first potential, a second portion 15 configured to operate under a second potential, and a third portion 16 configured to operate under alternating potentials.

[0054] The first portion 14 is configured to receive a first semiconductor die (not shown), and the second portion 15 is configured to receive a second semiconductor die (not shown). Furthermore, in another embodiment where the semiconductor dies have a vertical structure, the first semiconductor die 3 can be mounted at the first portion 14, and the second semiconductor die 5 can be mounted at the second portion 15. The semiconductor dies can be mounted on top of the respective portions, for example, by soldering, sintering, gluing, or diffusion soldering.

[0055] An EMI shielding structure 2 is included within an insulating substrate 7. The insulating substrate 7 may be a ceramic substrate. The EMI shielding structure 2 is formed by a second structured metallization layer 22. The second structured metallization layer 22 includes a first portion 23 and a second portion 24. The first portion 23 and the second portion 24 of the second structured metallization layer 22 are substantially in the same plane and have substantially the same dimensions. For clarity, the surface area of ​​the first portion 23 is equal to the surface area of ​​the second portion 24 of the second structured metallization layer 22.

[0056] Substrate 6 is a conductive substrate. Two portions 23 and 24 of the second structured metallization layer 22 are arranged adjacent to substrate 6. However, both portions are isolated from substrate 6 by the lowermost portion of the material 25 of the insulating substrate 7. Therefore, a shielding capacitor is formed by the second structured metallization layer 22 and substrate 6, wherein the material of the insulating substrate 7 is disposed therebetween, acting as a dielectric. Substrate 6 is connected to ground potential.

[0057] The insulating substrate 7 includes a third structured metallization layer 26. The third structured metallization layer 26 includes a plurality of wire-connectable layers. The plurality of wire-connectable layers form an interlocking layer structure 27 and / or a stacked layer structure within the insulating substrate 7. The third structured metallization layer 26 includes a first segment 28 coupled to a second potential 9. Furthermore, the third structured metallization layer 26 includes a second segment 29 electrically connected to a first potential 8.

[0058] Multiple wire-connectable layers form an interlocking layer structure 27. The interlocking layers of the interlocking layer structure 27 form a capacitor stack. The interlocking layers of the interlocking layer structure 27 are alternately coupled to a first potential 8 and a second potential 9. The interlocking layer structure 27 forms multiple stacked buffer capacitors within the insulating substrate 7. Specifically, a first segment 28 of the third structured metallization layer 26 together with a first portion 23 of the second structured metallization layer 22 forms a first buffer capacitor, wherein these portions are again separated from each other by the material of the insulating substrate 7. In the same manner, a second portion 24 of the second structured metallization layer 22 together with a second segment 29 of the third structured metallization layer 26 forms a second buffer capacitor.

[0059] In contrast to the non-overlapping first portion 23 and second portion 24 of the second structured metallization layer 22, the layers of the interlocking layer structure 27 overlap each other and are alternately coupled to the first potential 8 and the second potential 9, thus forming a stacked plate capacitor structure within the insulating substrate 7.

[0060] The interlocking layer structure 27 may include layers of different sizes. For example, as shown in the lower part of FIG2a, the layers of the interlocking layer structure 27 may have dimensions approximately equal to the first portion 23 and the second portion 24 of the second metallization layer 22. However, as shown in the upper part of FIG2a, the layers of the interlocking layer structure 27 may extend across the entire lateral dimension of the insulator substrate 7.

[0061] Figure 2b shows a schematic diagram of a semiconductor device according to the present disclosure. The engagement layer structure 27 includes a first upper layer, which may be a wiring layer 30. The wiring layer 30 is a redistribution layer configured to distribute / transmit an input potential or signal to a corresponding lower layer or layer of the engagement layer structure 27. The input potential / or signal is distributed through the wiring layer 30 via a via structure 31 to a lower layer of the engagement layer structure 27 inside the insulating substrate 7.

[0062] Since various input potentials can be transferred to the interlocking layer structure 27 by the redistribution layer, other potentials as DC+ and DC- can also be connected to the capacitor stack inside the insulating substrate 7.

[0063] For example, the first potential 8 can also be the gate potential, and the second potential 9 can also be the source potential. Therefore, the interlocking layer structure 27 can also form a gate-source capacitor to reduce oscillations during switching of one or more semiconductor dies 3, 4.

[0064] As another example, the first potential 8 can be the drain potential, and the second potential 9 can be the gate potential. In this configuration, the interlocking layer structure 27 forms one or more external Miller capacitances.

[0065] An extended view of Figure 2b illustrates an exemplary embodiment of the via structure 31. As an example, a first portion 23 of the second structured metallization layer 22 is shown as the lowermost portion connected to or contacted by the via structure 31. A first segment 28 of the third structured metallization layer 26 is exemplarily shown as a layer through which an input signal, for example, from a first potential 8, is transmitted to the first portion 23 of the second metallization layer 22. For signal distribution, a vertically conductive structure 32 connected to the input potential / signal is isolated by a vertical isolation structure 33. The vertical isolation structure 33 isolates the vertically conductive structure 32 from, for example, the first segment 28 of an interlocking layer structure 27. To accommodate the vertically conductive structure 32 and the vertical isolation structure 33, each of the upper layers of the interlocking layer structure 27 (which should not be contacted by the input potential) includes a hole 34.

[0066] Figure 2c illustrates a schematic diagram of the internal capacitance of an exemplary semiconductor device according to the present disclosure. A first EMI shielding capacitor C+ and a second EMI shielding capacitor C- are formed between the second structured metallization layer 22 and the substrate 6. A third structured metallization layer 26 forms a plurality of buffer capacitors C. S The stacked layers, these buffer capacitors in Figure 2C The capacitors are labeled with capacitor symbols. However, it should be understood that the capacitors / capacitors are formed by stacking layers, where the material of the insulating substrate 7 is the dielectric material located between them. It can be seen that multiple buffer capacitors are connected in series. As a means of visual reference, the polarity of the corresponding layers is indicated in Figure 2c.

[0067] Figure 3 Possible embodiments of a multilayer ceramic substrate and its different planes and conductive layers are shown. In addition to the inner shielding element 2 and EMI shielding structure 2, the illustrated stacked structure also functions as a DC buffer capacitor C. SEach point corresponds to an electrical connection between different layers via, for example, a via structure 31. Each circle represents a vertical isolation structure 33 in the corresponding layer to the (closed) vertical conductive structure 32. For example, in the second inner layer 35, the vertical conductive structure 32 in the upper corner on the right side provides an electrical connection to the conductive layer. The vertical conductive structure 32 in the upper corner on the left side is electrically insulated from the conductive layer of the second inner layer by the vertical isolation structure 33, but provides an electrical connection to the conductive layer of the third inner layer 36.

[0068] Figure 4 It shows that it has the following characteristics: Figure 3 The cross-section of the structured multilayer ceramic substrate shown for the EMI shielding structure 2 and the DC buffer capacitor stack structures 26 and 27. Along... Figure 3 The vertical plane AA shown is cut. To provide internal shielding, elements 23 and 24 of equal size are provided as the last layer of the second structured metallization layer 22. Similarly, as a visual aid, in Figure 4 The polarity of a single layer in the stack is marked at the corresponding layer.

[0069] Reference Symbol List 1 Semiconductor Devices 2 EMI shielding structure 3 First Switch 4. Second switch 5-Half-Bridge Device 6. Substrate, Second Substrate 7 Insulator Substrate 8 First electric potential 9 Second electric potential 10 nodes 11. First surface of the insulating substrate 12. Second surface of the insulating substrate 13 First metallization layer 14 First part of the first metallization layer 15 The second part of the first metallization layer 16 The third part of the first metallization layer 17 Bond wires 18. Capacitor stack 19 Lower conductive layer 20 Insulating Materials 21 conductive layers 22 Second structured metallization layer 23 The first part of the second metallization layer 24 Second part of the second metallization layer The bottom part of the material of the 25 insulating substrate 26 Third structured metallization layer 27 Meshing Layer Structure 28. The first segment of the third structured metallization layer 29. The second segment of the third structured metallization layer 30 wiring layers 31-hole structure 32 Vertical Conductive Structure 33 Vertical isolation structure 34 holes 35 Second Inner Layer 36 Third Inner Layer

Claims

1. A semiconductor device, comprising: Insulating substrate; A second substrate, wherein the second substrate is disposed on the first surface of the insulating substrate; A first structured metallization layer is disposed on a second surface of the insulating substrate opposite to the first surface, the first structured metallization layer comprising: The first part, configured to operate at a first potential; and The second part is configured to operate at a second potential; The insulating substrate includes: A second structured metallization layer, buried in the insulating substrate and configured for EMI shielding, is disposed adjacent to the second substrate and includes: The first part, the first part being coupled to the first potential; and The second part, coupled to the second potential, wherein the first part and the second part do not overlap; and At least one wireable third structured metallization layer, said at least one wireable third structured metallization layer comprising: A first segment, the first segment being coupled to the second potential; and The second segment is coupled to the first potential; The first portion of the second structured metallization layer and the first segment of the third structured metallization layer form a first buffer capacitor.

2. The semiconductor device according to claim 1, wherein, The second portion of the second structured metallization layer and the second segment of the third structured metallization layer form a second buffer capacitor.

3. The semiconductor device according to claim 1 or 2, wherein, The third structured metallization layer includes multiple wireable layers that form an interlocking layer structure alternately coupled to the first potential and the second potential, thereby forming multiple stacked buffer capacitors inside the insulating substrate.

4. The semiconductor device according to any of the preceding claims, wherein, The plurality of interlocking layer structures are embedded in the insulating substrate and arranged between the first structured metallization layer and the second structured metallization layer.

5. The semiconductor device according to claim 3 or 4, wherein, The interlocking layer structures alternately overlap each other and form a plate capacitor structure within the insulating substrate.

6. The semiconductor device according to any of the preceding claims, wherein, The insulating substrate is one of a multilayer ceramic substrate, a multilayer PCB, or a multilayer resin-based substrate.

7. The semiconductor device according to any of the preceding claims, wherein, The first portion of the first structured metallization layer is configured to accommodate a first semiconductor die, and the second portion of the first structured metallization layer is configured to accommodate a second semiconductor die.

8. The semiconductor device according to any of the preceding claims, wherein, The second substrate is a conductive substrate, and wherein the second structured metallization layer is arranged adjacent to the second substrate but isolated from the second substrate by the lowermost portion of the ceramic substrate, and each portion of the second structured metallization layer forms an EMI shielding capacitor with the second substrate.

9. The semiconductor device according to any of the preceding claims, wherein, The second substrate forms the substrate of the device and is connected to ground potential and configured to be attached to a heat sink.

10. The semiconductor device according to any of the preceding claims, wherein, The first structured metallization layer includes a third portion electrically isolated from both the first portion and the second portion of the first structured metallization layer, wherein the third portion is configured to operate under alternating potentials.

11. The semiconductor device according to any of the preceding claims, wherein, The insulating substrate includes a wiring layer, wherein the wiring layer is disposed between the third structured metallization layer and the first structured metallization layer.

12. The semiconductor device according to any of the preceding claims, wherein, The first portion of the second structured metallization layer has a first surface area, and the second portion of the second structured metallization layer has a second surface area substantially equal to the first surface area, and / or wherein the first portion and the second portion of the second structured metallization layer are substantially in the same plane.

13. The semiconductor device according to claim 12, wherein, The second surface area is less than 1 / 0.95 of the first surface area and greater than 1 / 1.05 of the first surface area.

14. The semiconductor device according to any one of claims 3-13, wherein, The interlocking layer structure forms one or more gate-source capacitors to reduce oscillations during the switching of one or more semiconductor dies.

15. The semiconductor device according to any one of claims 3-13, wherein, The interlocking layer structure forms one or more external Miller capacitors.

16. A semiconductor module device, comprising: Insulating substrate; A second conductive substrate is attached to the insulating substrate; The insulating substrate includes: At least one EMI shielding layer; as well as A meshing layer structure, which is configured to function as a stacked buffer capacitor.

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