Semiconductor package

Abstract

A semiconductor package includes: a first semiconductor chip including a first semiconductor substrate and a first via electrode passing through at least a portion of the first semiconductor substrate; a second semiconductor chip on the first semiconductor chip and including a second semiconductor substrate; a first bonding pad structure between the first semiconductor chip and the second semiconductor chip; a first dummy bonding pad structure between the first semiconductor chip and the second semiconductor chip; and a first inter-chip insulating layer and a second inter-chip insulating layer, the first inter-chip insulating layer being on a surface of the first semiconductor chip, the second inter-chip insulating layer being on a surface of the second semiconductor chip, the first bonding pad structure including: a first bonding pad on the surface of the first semiconductor chip; and a second bonding pad on the surface of the second semiconductor chip.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0167759, filed on November 21, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to semiconductor packages, and more specifically, to semiconductor packages comprising semiconductor chips that are directly bonded (or directly joined). Background Technology

[0003] Driven by the development of the electronics industry and user demands, electronic devices are becoming smaller and lighter, requiring semiconductor packages used in these devices to be even smaller and lighter, while also offering higher performance and greater capacity. To achieve high performance and high capacity alongside miniaturization and weight reduction, ongoing research and development is underway on semiconductor chips, including through-silicon vias (TSVs), and semiconductor packages in which these chips are stacked. In semiconductor packages involving directly bonded stacked semiconductor chips, ensuring the reliability of the bonding (or connection) between the semiconductor chips is crucial. Summary of the Invention

[0004] This disclosure provides semiconductor packages with improved reliability by using homogeneous bonding in direct bonding between semiconductor chips.

[0005] Furthermore, the technical objectives achieved by this disclosure are not limited to those mentioned above, and other technical objectives can be clearly understood by those skilled in the art from the following description.

[0006] According to one aspect of the disclosure, a semiconductor package includes: a first semiconductor chip including a first semiconductor substrate and a first via electrode passing through at least a portion of the first semiconductor substrate; a second semiconductor chip on the first semiconductor chip and including the second semiconductor substrate; a first bonding pad structure between the first semiconductor chip and the second semiconductor chip; a first dummy bonding pad structure between the first semiconductor chip and the second semiconductor chip; and a first inter-chip insulating layer and a second inter-chip insulating layer, wherein the first inter-chip insulating layer is on the surface of the first semiconductor chip and the second inter-chip insulating layer is on the surface of the second semiconductor chip, wherein the first... A bonding pad structure includes: a first bonding pad on the surface of a first semiconductor chip; and a second bonding pad on the surface of a second semiconductor chip, wherein the first dummy bonding pad structure includes: a first dummy bonding pad on the surface of the first semiconductor chip; and a second dummy bonding pad on the surface of the second semiconductor chip, wherein the second bonding pad and the first bonding pad are in contact with each other and directly bonded to each other, and wherein the second dummy bonding pad and the first dummy bonding pad are in contact with each other and directly bonded to each other, and at least a portion of the first inter-chip insulating layer and the second inter-chip insulating layer are in contact with each other and directly bonded to each other.

[0007] According to one aspect of the disclosure, a semiconductor package includes: a first semiconductor chip including a first semiconductor substrate and a first via electrode passing through at least a portion of the first semiconductor substrate; a second semiconductor chip on the first semiconductor chip and including a second semiconductor substrate and a second via electrode passing through at least a portion of the second semiconductor substrate; a first bonding pad structure between the first semiconductor chip and the second semiconductor chip; a first dummy bonding pad structure between the first semiconductor chip and the second semiconductor chip; a second dummy bonding pad structure between the first semiconductor chip and the second semiconductor chip; a first inter-chip insulating layer on the surface of the first semiconductor chip; a second inter-chip insulating layer on the surface of the second semiconductor chip; and an encapsulation member on the first semiconductor chip and surrounding the second semiconductor chip, wherein the first bonding pad structure includes: a first bonding pad on the surface of the first semiconductor chip; and a second bonding pad on the second semiconductor chip. On the surface of the chip, wherein the first dummy bonding pad structure comprises: a first dummy bonding pad on the surface of the first semiconductor chip; and a second dummy bonding pad on the surface of the second semiconductor chip, wherein the second dummy bonding pad structure comprises: a third dummy bonding pad on the surface of the first semiconductor chip; and a fourth dummy bonding pad on the surface of the second semiconductor chip, wherein the second bonding pad and the first bonding pad are in contact with each other and directly bonded to each other, wherein at least a portion of the first inter-chip insulating layer and the second inter-chip insulating layer are in contact with each other and directly bonded to each other, wherein the shape of the first semiconductor chip is larger than the shape of the second semiconductor chip, and wherein one surface of the fourth dummy bonding pad is aligned with the second chip perimeter of the second semiconductor chip in one direction, wherein said direction is perpendicular to the surface of the second semiconductor chip.

[0008] According to one aspect of the disclosure, a semiconductor package includes: a first semiconductor chip including a first semiconductor substrate and a first via electrode passing through at least a portion of the first semiconductor substrate; a second semiconductor chip on the first semiconductor chip, including a second semiconductor substrate and a second via electrode passing through at least a portion of the second semiconductor substrate; a first bonding pad structure between the first semiconductor chip and the second semiconductor chip; a first dummy bonding pad structure between the first semiconductor chip and the second semiconductor chip; a second dummy bonding pad structure between the first semiconductor chip and the second semiconductor chip; a third dummy bonding pad structure between the first semiconductor chip and the second semiconductor chip; a first inter-chip insulating layer and a second inter-chip insulating layer, the first inter-chip insulating layer being on the surface of the first semiconductor chip, the second inter-chip insulating layer being on the surface of the first semiconductor chip; and the second inter-chip insulating layer being on the surface of the first semiconductor chip. An inter-chip insulating layer is provided on the surface of a second semiconductor chip; and an encapsulation member is provided on and surrounding the first semiconductor chip, wherein a first bonding pad structure comprises: a first bonding pad on the surface of the first semiconductor chip; and a second bonding pad on the surface of the second semiconductor chip, wherein a first dummy bonding pad structure comprises: a first dummy bonding pad on the surface of the first semiconductor chip; and a second dummy bonding pad on the surface of the second semiconductor chip, wherein the second dummy bonding pad structure comprises: a third dummy bonding pad on the surface of the first semiconductor chip; and a fourth dummy bonding pad on the surface of the second semiconductor chip, wherein the third dummy bonding pad structure comprises: a fifth dummy bonding pad on the surface of the first semiconductor chip;And a sixth dummy bonding pad on the surface of the second semiconductor chip, wherein the second bonding pad and the first bonding pad are in contact with each other and directly bonded to each other, wherein the second dummy bonding pad and the first dummy bonding pad are in contact with each other and directly bonded to each other, wherein at least a portion of the first inter-chip insulating layer and the second inter-chip insulating layer are in contact with each other and directly bonded to each other, wherein the shape of the first semiconductor chip is larger than the shape of the second semiconductor chip, wherein one surface of the fourth dummy bonding pad is aligned with the second chip perimeter of the second semiconductor chip in one direction, wherein said direction is perpendicular to the surface of the second semiconductor chip, wherein the second bonding pad, the second dummy bonding pad, the fourth dummy bonding pad and the first inter-chip insulating layer are not in contact with each other, wherein the first bonding pad, the first dummy bonding pad, the third dummy bonding pad The insulating layer between the pad and the first chip does not contact each other, wherein a fourth dummy bonding pad contacts a portion of a third dummy bonding pad, and the remaining portion of the third dummy bonding pad contacts the encapsulation member, wherein the first semiconductor chip includes a buffer chip, and the second semiconductor chip includes a memory chip, wherein the first bonding pad structure connects the first semiconductor chip and the second semiconductor chip to each other, wherein each of the first, second, and third dummy bonding pad structures is not connected to the first and second semiconductor chips, wherein at least a portion of the third dummy bonding pad structure is within a first region, and wherein the first region is defined as the region between the first and second semiconductor chips, the first region including the first bonding pad structure and excluding the second dummy bonding pad structure. Attached Figure Description

[0009] The embodiments of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0010] Figure 1 This is a cross-sectional view of a semiconductor package according to an embodiment.

[0011] Figure 2 According to the embodiments Figure 1 An enlarged sectional view of part A.

[0012] Figure 3 It is according to the embodiment along Figure 1 The section view taken from part B-B' in the plan view.

[0013] Figure 4 This is a cross-sectional view of a portion of a semiconductor package according to an embodiment, which is related to... Figure 1 The parts B-B' are the same.

[0014] Figure 5 This is a cross-sectional view of a portion of a semiconductor package according to an embodiment, which is related to... Figure 1The parts B-B' are the same.

[0015] Figure 6 This is a cross-sectional view of a portion of a semiconductor package according to an embodiment, which is related to... Figure 1 The parts B-B' are the same.

[0016] Figure 7 This is a cross-sectional view of a portion of a semiconductor package according to an embodiment, which is related to... Figure 1 The parts B-B' are the same.

[0017] Figure 8 This is a cross-sectional view of a portion of a semiconductor package according to an embodiment, which is related to... Figure 1 The parts B-B' are the same.

[0018] Figure 9 This is a cross-sectional view of a portion of a semiconductor package according to an embodiment, which is related to... Figure 1 The parts B-B' are the same.

[0019] Figure 10 This is a cross-sectional view of a portion of a semiconductor package according to an embodiment, which is related to... Figure 1 The parts B-B' are the same.

[0020] Figure 11 This is a cross-sectional view of a semiconductor package according to an embodiment.

[0021] Figure 12 According to the embodiments Figure 11 An enlarged sectional view of part D.

[0022] Figure 13 It is according to the embodiment along Figure 11 The section view taken from part E-E' in the plan view. Detailed Implementation

[0023] It will be understood that while the terms “first,” “second,” “third,” “fourth,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, without departing from the publicly disclosed teachings, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part.

[0024] It will be understood that when an element or layer is referred to as being "above," "on top," "above," "below," "under," "connected to," or "bonded to" another element or layer, the element or layer may be directly above, above, above, below, below, or directly connected to the other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being "directly above," "above," "above," "below," "under," "under," "directly connected to," or "directly bonded to" another element or layer, there are no intermediate elements or layers.

[0025] A layer can be described as having an upper surface and a lower surface. As will be understood by those skilled in the art, the surface of a layer can also be described as a first surface and a second surface, wherein the first surface can be one of the upper surface and the lower surface of the layer, and the second surface can be the other of the upper surface and the lower surface of the layer.

[0026] The specification uses degree terms including "basically" or "approximately". In one or more examples, when the specified parameter X is substantially the same as parameter Y, the term "basically" can be understood as the absolute deviation of X relative to Y being within 10% of Y. In one or more examples, when the specified parameter is approximately X, the term "approximately" can be understood as the absolute deviation of that parameter relative to X being within 10% of X.

[0027] In one or more examples, a bonding pad that includes multiple bonding pads (or joint pads) (such as a lower bonding pad (e.g., a first bonding pad) and an upper bonding pad (e.g., a second bonding pad)) may be referred to as a bonding pad structure.

[0028] Figure 1 This is a cross-sectional view of the semiconductor package 1 according to an embodiment. Figure 2 yes Figure 1 An enlarged sectional view of part A. Figure 3 It is along Figure 1 The section view taken from part B-B' in the plan view.

[0029] Reference Figures 1 to 3 According to an embodiment, the semiconductor package 1 may include a first semiconductor chip 100, a plurality of second semiconductor chips 200 stacked on the first semiconductor chip 100, and an encapsulation member 270 surrounding the plurality of second semiconductor chips 200 on the first semiconductor chip 100. Among the plurality of second semiconductor chips 200, the one closest to the first semiconductor chip 100 may be referred to as the lowermost second semiconductor chip 200B, and among the plurality of second semiconductor chips 200, the one furthest from the first semiconductor chip 100 may be referred to as the uppermost second semiconductor chip 200T.

[0030] The shape of the first semiconductor chip 100 in the planar view may be larger than the shape of the second semiconductor chip 200 in the planar view. For example, as Figure 1 As shown, the length of the first semiconductor chip 100 in the X direction is greater than the length of the second semiconductor chip 200 in the X direction. Figure 3 As shown, the shapes of the plurality of second semiconductor chips 200 in the planar view can be positioned within the shape of the first semiconductor chip 100 in the planar view. For example, the planar shape of the lowermost second semiconductor chip 200B in the planar view can be positioned within the shape of the first semiconductor chip 100 in the planar view. The semiconductor package 1 can be manufactured by a wafer-on-wafer (CoW) process. However, as those skilled in the art will understand, the embodiments of this disclosure are not limited to these constructions (configurations).

[0031] In one or more examples, the plurality of second semiconductor chips 200 may all be memory chips of the same type. The memory chips may be volatile memory chips (such as dynamic random access memory (DRAM) or static random access memory (SRAM)), non-volatile memory chips (such as phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM) or resistive random access memory (RRAM)) or any other suitable memory structure known to those skilled in the art.

[0032] For example, the plurality of second semiconductor chips 200 may each be a memory chip (such as a dynamic random access memory (DRAM) chip). For example, the plurality of second semiconductor chips 200 may be chips of the same type. For example, the semiconductor package 1 including the first semiconductor chip 100 and the plurality of second semiconductor chips 200 may be a high-bandwidth memory (HBM), wherein the first semiconductor chip 100 may be referred to as an HBM controller die, and the plurality of second semiconductor chips 200 may each be referred to as a DRAM die. In one or more examples, the HBM may be a computer memory optimized for fast data transfer and reduced power consumption. The HBM may employ DRAM dies vertically stacked using through-silicon vias (TSVs).

[0033] According to some embodiments, the first semiconductor chip 100 may include a serial-parallel conversion circuit that parallelizes data signals received from the controller chip and sends the parallelized data signals to the memory chip. The first semiconductor chip 100 may also be a buffer chip for controlling the second semiconductor chip 200. The first semiconductor chip 100 may also be referred to as an interface die, substrate die, logic die, main die, etc. According to some embodiments, the second semiconductor chip 200 may be a memory chip including memory cells.

[0034] The semiconductor package 1 may include a plurality of second semiconductor chips 200. Each of the plurality of second semiconductor chips 200 may have the same dimensions in a plan view. For example, the widths of the plurality of second semiconductor chips 200 may be substantially the same as each other. The plurality of second semiconductor chips 200, except for the uppermost second semiconductor chip 200T, may have substantially the same thickness. For example, the sidewalls of the plurality of second semiconductor chips 200 may be vertically aligned with each other. In one or more examples, at least one of the second semiconductor chips 200 may have dimensions different from those of the other second semiconductor chips 200.

[0035] Figure 2 An example structure of the second semiconductor chip 200 is shown. Figure 2 The second semiconductor chip 200 shown in the figure can correspond to Figure 1 Each of the second semiconductor chips 200 shown herein. The second semiconductor chip 200 may include a second semiconductor substrate 210, a second via electrode 220 extending vertically through at least a portion of the second semiconductor substrate 210, a second semiconductor device 234 disposed on one surface of the second semiconductor substrate 210, a second front insulating layer 233 disposed on the front surface (or lower surface) of the second semiconductor substrate 210 and covering the second semiconductor device 234, a second wiring pattern 230 disposed in the second front insulating layer 233, a first upper bonding pad 240B disposed on the second front insulating layer 233, a first upper dummy bonding pad 311B disposed on the second front insulating layer 233, a second upper dummy bonding pad 321B and a third upper dummy bonding pad 321C disposed on the second front insulating layer 233, and a first upper inter-chip insulating layer 250B disposed on the bottom surface of the second front insulating layer 233.

[0036] The first semiconductor chip 100 may include a first semiconductor substrate 110, a first via electrode 120 that vertically passes through at least a portion of the first semiconductor substrate 110, a first semiconductor device disposed on one surface of the first semiconductor substrate 110, a first front insulating layer 133 disposed on the front surface (or lower surface) of the first semiconductor substrate 110, a first wiring pattern 130 disposed in the first front insulating layer 133, a first lower inter-chip insulating layer 250A disposed on the top surface of the first semiconductor substrate 110, a first lower bonding pad 240A disposed on the top surface of the first semiconductor substrate 110, a first lower dummy bonding pad 311A ​​and a second lower dummy bonding pad 321A disposed on the top surface of the first semiconductor substrate 110, a first front pad 150 disposed on the bottom surface of the first semiconductor chip 100, and a first lower passivation layer 170 disposed on the bottom surface of the first semiconductor chip 100 and surrounding a portion of the first front pad 150.

[0037] The first semiconductor substrate 110 and the second semiconductor substrate 210 may comprise semiconductor materials such as silicon (Si). In one or more examples, the first semiconductor substrate 110 and the second semiconductor substrate 210 may comprise semiconductor materials such as germanium (Ge). The first semiconductor substrate 110 and the second semiconductor substrate 210 may each comprise a conductive region (e.g., a well doped with impurities on its active surface). The first semiconductor substrate 110 and the second semiconductor substrate 210 may have various device isolation structures (e.g., shallow trench isolation (STI) structures).

[0038] The first semiconductor chip 100 may include a first via electrode 120 passing through at least a portion of a first semiconductor substrate 110. The first via electrode 120 may electrically connect a first front pad 150 and a first lower bonding pad 240A. The first semiconductor chip 100 may also include a first lower passivation layer 170 disposed on the bottom surface of the first semiconductor chip 100. The first front pad 150 may be surrounded by the first lower passivation layer 170. The first front pad 150 may be electrically connected to a first semiconductor device layer. The first semiconductor device layer may include an insulating layer and a first wiring pattern 130. An external connection terminal 160 may be disposed on the first front pad 150. The first wiring pattern 130 of the first semiconductor chip 100 is shown in simplified form with solid lines.

[0039] The first bonding pad 240 and the second inter-chip insulating layer 260 can be disposed between adjacent second semiconductor chips 200 among a plurality of second semiconductor chips 200. The first bonding pad 240 and the second inter-chip insulating layer 260 disposed between adjacent second semiconductor chips 200 can be formed by direct bonding as described below.

[0040] The first semiconductor chip 100 and the second semiconductor chip 200 may be directly bonded to each other. Direct bonding between the two chips may include direct bonding between conductive components of the two chips facing each other and direct bonding between insulating components of the two chips facing each other. Direct bonding between insulating components may involve forming chemical bonds between the insulating components. Direct bonding between any two chips may include hybrid bonding. In one or more examples, hybrid bonding may be bonding a dielectric compound (e.g., SiO2) with an embedded metal (e.g., Cu). x They are combined to form the bonding of interconnects.

[0041] In one or more examples, a first lower bonding pad 240A disposed on the top surface of the first semiconductor substrate 110 of the first semiconductor chip 100 and a first upper bonding pad 240B disposed on the second front insulating layer 233 of the second semiconductor chip 200 can be directly bonded to each other. A first lower dummy bonding pad 311A ​​disposed on the top surface of the first semiconductor substrate 110 of the first semiconductor chip 100 and a first upper dummy bonding pad 311B disposed on the second front insulating layer 233 of the second semiconductor chip 200 can be directly bonded to each other. A second lower dummy bonding pad 321A disposed on the top surface of the first semiconductor substrate 110 of the first semiconductor chip 100 and a second upper dummy bonding pad 321B disposed on the second front insulating layer 233 of the second semiconductor chip 200 can be directly bonded to each other. For example... Figure 3 As shown, the second lower dummy bonding pad 321A and the third upper dummy bonding pad 321C disposed on the second front insulating layer 233 of the second semiconductor chip 200 can be directly bonded to each other.

[0042] For example, a first lower inter-chip insulating layer 250A disposed on the top surface of the first semiconductor substrate 110 of the first semiconductor chip 100 and a first upper inter-chip insulating layer 250B disposed on the bottom surface of the second front insulating layer 233 of the second semiconductor chip 200 can be directly bonded to each other. The first lower inter-chip insulating layer 250A and the first upper inter-chip insulating layer 250B can comprise the same material. For example, the first lower inter-chip insulating layer 250A and the first upper inter-chip insulating layer 250B can comprise silicon oxide. The direct bonding process can be performed by a high-temperature annealing process while the first lower inter-chip insulating layer 250A and the first upper inter-chip insulating layer 250B are in direct contact with each other. The dielectric material constituting the first lower inter-chip insulating layer 250A and the first upper inter-chip insulating layer 250B is not limited to silicon oxide, and can be a material that can be bonded to each other. For example, the dielectric material can comprise silicon carbonitride (SiCN).

[0043] The first lower inter-chip insulating layer 250A may be disposed on the top surface of the first semiconductor chip 100 to substantially match the shape of the second semiconductor chip 200 in the planar view; or the first lower inter-chip insulating layer 250A may be disposed on the top surface of the first semiconductor chip 100 to have a planar area larger than that of the second semiconductor chip 200. The first lower inter-chip insulating layer 250A may be disposed on the top surface of the first semiconductor chip 100 to have a size equal to or smaller than the size of the shape of the first semiconductor chip 100 in the planar view. The shape of the first upper inter-chip insulating layer 250B in the planar view may be included within the shape of the first lower inter-chip insulating layer 250A in the planar view, or the shape of the first lower inter-chip insulating layer 250A in the planar view may be substantially the same as the shape of the first upper inter-chip insulating layer 250B in the planar view.

[0044] During the direct bonding process, for example, metal atoms in the first lower bonding pad 240A disposed on the top surface of the first semiconductor substrate 110 of the first semiconductor chip 100 can diffuse into the first upper bonding pad 240B disposed on the second front insulating layer 233 of the second semiconductor chip 200, and metal atoms in the first upper bonding pad 240B can diffuse into the first lower bonding pad 240A. Therefore, the interface between the first upper bonding pad 240B and the first lower bonding pad 240A can be indistinguishable. However, for the purpose of differentiation, in Figure 1 and Figure 2 The interface is indicated by a dashed line. In one or more examples, the direct bonding process between two components may include component pretreatment, pre-bonding at room temperature, and annealing at elevated temperature.

[0045] Through a direct bonding process, the first upper bonding pad 240B and the first lower bonding pad 240A can be firmly bonded. This can be referred to as a direct bond between the first upper bonding pad 240B and the first lower bonding pad 240A. The directly bonded first upper bonding pad 240B and the first lower bonding pad 240A can be collectively referred to as the first bonding pad 240. The directly bonded first lower dummy bonding pad 311A ​​and the first upper dummy bonding pad 311B can be collectively referred to as the first dummy bonding pad 310. The directly bonded second lower dummy bonding pad 321A and the second upper dummy bonding pad 321B can be collectively referred to as the second dummy bonding pad 320B. For example... Figure 3 As shown, the second lower dummy bonding pad 321A and the third upper dummy bonding pad 321C, which are directly bonded, can be collectively referred to as the third dummy bonding pad 320C.

[0046] The first dummy bonding pad 310, the second dummy bonding pad 320B, and the third dummy bonding pad 320C may not be electrically connected to the first semiconductor chip 100 and the second semiconductor chip 200. The first dummy bonding pad 310, the second dummy bonding pad 320B, and the third dummy bonding pad 320C may not be electrically connected to the plurality of first via electrodes 120 and the plurality of second via electrodes 220. In one or more examples, the first dummy bonding pad 310, the second dummy bonding pad 320B, and the third dummy bonding pad 320C may not be electrically connected to the second semiconductor device 234. In one or more examples, the first dummy bonding pad 310, the second dummy bonding pad 320B, and the third dummy bonding pad 320C may be electrically connected to only one of the first semiconductor chip 100 and the second semiconductor chip 200.

[0047] During the direct bonding process, the first lower inter-chip insulating layer 250A and the first upper inter-chip insulating layer 250B can be in direct contact and connected by direct bonding. For example, chemical bonds can be provided between the first lower inter-chip insulating layer 250A and the first upper inter-chip insulating layer 250B. These chemical bonds can be covalent bonds. After direct bonding, the interface between the first lower inter-chip insulating layer 250A and the first upper inter-chip insulating layer 250B can be indistinguishable. However, for distinguishing purposes, in Figure 1 and Figure 2 The interface is indicated by a dashed line. The first lower inter-chip insulating layer 250A and the first upper inter-chip insulating layer 250B, which are directly bonded, can be collectively referred to as the first inter-chip bonding insulating layer 250.

[0048] A second front insulating layer 233 is disposed on the bottom surface of the second semiconductor substrate 210 and may cover the second semiconductor device 234. The second front insulating layer 233 may include a silicon-based insulating material. The silicon-based insulating material may include, for example, silicon oxide, silicon nitride, silicon oxynitride, and / or tetraethyl orthosilicate (TEOS). The second front insulating layer 233 may include multiple stacked layers.

[0049] The second semiconductor device 234 may be disposed on one surface of the second semiconductor substrate 210. Each of the second semiconductor devices 234 may comprise multiple individual devices of various types. The multiple individual devices may include various microelectronic devices (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs) (such as complementary metal-oxide-semiconductor transistors (CMOS transistors)), system-scale integrated circuits (LSI), microelectromechanical systems (MEMS), active devices, passive devices, etc.).

[0050] The second wiring pattern 230 may be disposed within the second front insulating layer 233. The second wiring pattern 230 may include a second line pattern 231 and a second via pattern 232. For example, the second wiring pattern 230 may be a multilayer wiring in which two or more second line patterns 231 and / or two or more second via patterns 232 are stacked alternately.

[0051] The second wiring pattern 230 may be electrically connected to at least one of the second semiconductor device 234 and the second via electrode 220. As used herein, electrical connection includes direct connection or indirect connection via another conductive component. Electrical connection to a semiconductor chip may mean electrical connection to an integrated circuit of the semiconductor chip. Component connection to a through-via and / or integrated circuit may mean that the component is electrically connected to at least one of the through-via and the integrated circuit.

[0052] Encapsulation member 270 may surround the second semiconductor chip 200 on the top surface of the first semiconductor chip 100. Encapsulation member 270 may include, for example, epoxy molding compound (EMC). Encapsulation member 270 may also include filler. In one or more examples, encapsulation member 270 may be formed of one or more materials that protect the semiconductor chip from damage from the external environment, such as moisture. Encapsulation member may be formed of plastic (e.g., epoxy molding compound, silicone resin, polyurethane), metal (e.g., Kovar alloy) or ceramic.

[0053] The boundary formed by the side surface of the second semiconductor chip 200 may be referred to as the second chip perimeter 210SA. The second chip perimeter 210SA may be included in the vertically aligned surfaces of the plurality of second semiconductor chips 200. For example... Figure 2 As shown, at least a portion of the second chip perimeter 210SA can contact the encapsulation member 270. Portions of the side surfaces of the second upper dummy bonding pad 321B and the third upper dummy bonding pad 321C can contact the encapsulation member 270.

[0054] The second lower dummy bonding pad 321A may be placed on the top surface of the first semiconductor chip 100 and at the lower end of the outer edge of the second semiconductor chip 200. A portion of the second lower dummy bonding pad 321A may be located inside the second chip perimeter 210SA of the second semiconductor chip 200, and the remaining portion of the second lower dummy bonding pad 321A may be located outside the second chip perimeter 210SA. In one or more examples, a portion of the second lower dummy bonding pad 321A may have a shape that protrudes from the second chip perimeter 210SA toward the outer edge of the first semiconductor chip 100.

[0055] The second upper dummy bonding pad 321B and the third upper dummy bonding pad 321C may be positioned adjacent to the outer edge of the second semiconductor chip 200, but they may be located inside the second chip perimeter 210SA. Unlike the second lower dummy bonding pad 321A, the second upper dummy bonding pad 321B and the third upper dummy bonding pad 321C may not protrude outside the second chip perimeter 210SA. In one or more examples, one surface of each of the second upper dummy bonding pad 321B and the third upper dummy bonding pad 321C may be aligned with the second chip perimeter 210SA in a direction perpendicular to the surface of the second semiconductor chip 200.

[0056] The second upper dummy bonding pad 321B and the third upper dummy bonding pad 321C may each contact a portion of the second lower dummy bonding pad 321A. The second lower dummy bonding pad 321A, excluding the portion that contacts the second upper dummy bonding pad 321B, may contact the encapsulation member 270 without contacting the second upper dummy bonding pad 321B. The second lower dummy bonding pad 321A, excluding the portion that contacts the third upper dummy bonding pad 321C, may contact the encapsulation member 270 without contacting the third upper dummy bonding pad 321C.

[0057] In a plan view, the second upper dummy bonding pad 321B may have a shape substantially the same as a portion of the shape of the second lower dummy bonding pad 321A. For example, the second lower dummy bonding pad 321A may have a circular shape in the plan view, and the second upper dummy bonding pad 321B may have an arc shape and a shape connecting the two ends of the arc, or a semi-circular shape in the plan view. For example, the second lower dummy bonding pad 321A may have a rectangular shape in the plan view, and the second upper dummy bonding pad 321B may have a rectangular shape in the plan view with a portion of the rectangular shape of the second lower dummy bonding pad 321A removed.

[0058] In a plan view, the third upper dummy bonding pad 321C may have a shape substantially identical to a portion of the shape of the second lower dummy bonding pad 321A. For example, the second lower dummy bonding pad 321A may have a circular shape in the plan view, and the third upper dummy bonding pad 321C may have a quarter-circle shape in the plan view. For example, the second lower dummy bonding pad 321A may have a rectangular shape in the plan view, and the third upper dummy bonding pad 321C may have a rectangular shape in the plan view with a portion of the rectangular shape of the second lower dummy bonding pad 321A removed.

[0059] For example, such as Figure 3As shown, a plurality of second dummy bonding pads 320B may be arranged along the second chip perimeter 210SA. A plurality of third dummy bonding pads 320C may be arranged at vertices, the vertices being the curved portions (bends) of the second chip perimeter 210SA. Figure 3 In the middle, the second upper dummy bonding pad 321B and the third upper dummy bonding pad 321C are indicated by dashed lines, and the second lower dummy bonding pad 321A is indicated by solid lines.

[0060] For example, a plurality of second lower dummy bonding pads 321A may be arranged along the second chip perimeter 210SA on the top surface of the first semiconductor chip 100. In one or more examples, the plurality of second lower dummy bonding pads 321A may be arranged such that the second chip perimeter 210SA is superimposed on the plurality of second lower dummy bonding pads 321A. A second upper dummy bonding pad 321B may be arranged along the second chip perimeter 210SA. In one or more examples, the second upper dummy bonding pad 321B may be arranged without deviating from (detaching from) the inside of the second chip perimeter 210SA. A third upper dummy bonding pad 321C may be positioned at the apex of the second chip perimeter 210SA, but the third upper dummy bonding pad 321C may be positioned without deviating from (detaching from) the inside of the second chip perimeter 210SA.

[0061] The shape of the second upper dummy bonding pad 321B in the plan view is substantially the same as a portion of the shape of the second lower dummy bonding pad 321A in the plan view. Therefore, when the second upper dummy bonding pad 321B and the second lower dummy bonding pad 321A are directly bonded, the portion of the second lower dummy bonding pad 321A that does not match the second upper dummy bonding pad 321B may not contact the second upper dummy bonding pad 321B. Therefore, the encapsulation member 270 may contact the portion of the second lower dummy bonding pad 321A that does not match the second upper dummy bonding pad 321B.

[0062] The shape of the third upper dummy bonding pad 321C in the plan view is substantially the same as a portion of the shape of the second lower dummy bonding pad 321A in the plan view. Therefore, when the third upper dummy bonding pad 321C and the second lower dummy bonding pad 321A are directly bonded, the portion of the second lower dummy bonding pad 321A that does not match the third upper dummy bonding pad 321C may not contact the third upper dummy bonding pad 321C. Therefore, the encapsulation member 270 may contact the portion of the second lower dummy bonding pad 321A that does not match the third upper dummy bonding pad 321C.

[0063] The first dummy bonding pad 310 may include a first upper dummy bonding pad 311B disposed on the bottom surface of the second semiconductor chip 200 and a first lower dummy bonding pad 311A ​​disposed on the top surface of the first semiconductor chip 100. In a plan view, the shape of the first upper dummy bonding pad 311B can substantially match the shape of the first lower dummy bonding pad 311A. Therefore, the entire bottom surface of the first upper dummy bonding pad 311B and the entire top surface of the first lower dummy bonding pad 311A ​​can be in contact with each other.

[0064] The first bonding pad 240, the first dummy bonding pad 310, the second dummy bonding pad 320B, and the third dummy bonding pad 320C disposed between the first semiconductor chip 100 and the second semiconductor chip 200 do not contact the first inter-chip bonding insulating layer 250 at the first direct bonding interface IDB1. The first direct bonding interface IDB1 can refer to the interface formed between the first semiconductor chip 100 and the second semiconductor chip 200 before they are integrated by direct bonding. Therefore, the first direct bonding interface IDB1 can be understood as a plane passing through approximately half the thickness of each component after direct bonding, and the first direct bonding interface IDB1 can be understood as a virtual interface that cannot be observed after direct bonding is performed.

[0065] For example, the first direct bonding interface IDB1 may refer to the surfaces of the first upper bonding pad 240B and the first lower bonding pad 240A that are in contact with each other just before the direct bonding process is performed, the surfaces of the first upper dummy bonding pad 311B and the first lower dummy bonding pad 311A ​​that are in contact with each other, the surfaces of the second upper dummy bonding pad 321B and the second lower dummy bonding pad 321A that are in contact with each other, the surfaces of the third upper dummy bonding pad 321C and the second lower dummy bonding pad 321A that are in contact with each other, and the extended surfaces of the surfaces of the first upper inter-chip insulating layer 250B and the first lower inter-chip insulating layer 250A that are in contact with each other.

[0066] In the semiconductor package 1 according to the embodiment, the components directly bonded between the first semiconductor chip 100 and the second semiconductor chip 200 are not hetero-bonded. In other words, in the semiconductor package 1 according to the embodiment, the components directly bonded between the first semiconductor chip 100 and the second semiconductor chip 200 are homo-bonded.

[0067] In one or more examples, hetero-bonding can refer to a direct bonding process performed while materials of different categories are in contact with each other. For example, hetero-bonding can refer to a direct bonding process performed at a direct bonding interface where metallic and non-metallic components are in direct contact at the interface. In one or more examples, homo-bonding can refer to a direct bonding process performed while materials of the same category are in contact with each other. For example, homo-bonding can refer to a direct bonding process performed at a direct bonding interface where metallic components are in direct contact with metallic components or non-metallic components are in direct contact with non-metallic components.

[0068] In one or more examples, heterogeneous bonding may mean that at least a portion of the first upper bonding pad 240B, at least a portion of the first upper dummy bonding pad 311B, at least a portion of the second upper dummy bonding pad 321B, or at least a portion of the third upper dummy bonding pad 321C is directly bonded to the first lower inter-chip insulating layer 250A while in contact with it. In one or more examples, heterogeneous bonding may include a situation where at least a portion of the first lower bonding pad 240A, at least a portion of the first lower dummy bonding pad 311A, or at least a portion of the second lower dummy bonding pad 321A is directly bonded to the first upper inter-chip insulating layer 250B while in contact with it.

[0069] In one or more examples, homogeneous bonding may include direct bonding of the first upper bonding pad 240B, the first upper dummy bonding pad 311B, the second upper dummy bonding pad 321B, and the third upper dummy bonding pad 321C without contacting the first lower inter-chip insulating layer 250A. In one or more examples, homogeneous bonding may include direct bonding of the first lower bonding pad 240A, the first lower dummy bonding pad 311A, or the second lower dummy bonding pad 321A without contacting the first upper inter-chip insulating layer 250B.

[0070] In the semiconductor package 1 according to an embodiment, components that are directly bonded to each other can be homogeneously bonded. Figure 1 and Figure 2 At the first direct bonding interface IDB1, the first lower bonding pad 240A may not contact the first upper inter-chip insulating layer 250B, and at the first direct bonding interface IDB1, the first upper bonding pad 240B may not contact the first lower inter-chip insulating layer 250A. Similarly, at the first direct bonding interface IDB1, the first lower dummy bonding pad 311A ​​and the second lower dummy bonding pad 321A may not contact the first upper inter-chip insulating layer 250B, and at the first direct bonding interface IDB1, the first upper dummy bonding pad 311B and the second upper dummy bonding pad 321B may not contact the first lower inter-chip insulating layer 250A.

[0071] In other words, the first lower bonding pad 240A can contact only the first upper bonding pad 240B at the first direct bonding interface IDB1, the first lower dummy bonding pad 311A ​​can contact only the first upper dummy bonding pad 311B at the first direct bonding interface IDB1, and the second upper dummy bonding pad 321B can contact only the second lower dummy bonding pad 321A at the first direct bonding interface IDB1. Furthermore, the third upper dummy bonding pad 321C can contact only the second lower dummy bonding pad 321A at the first direct bonding interface IDB1.

[0072] In the semiconductor package 1 according to the embodiment, components directly bonded between the first semiconductor chip 100 and the second semiconductor chip 200 are not heterogeneously bonded. In other words, in the semiconductor package 1 according to the embodiment, components directly bonded between the first semiconductor chip 100 and the second semiconductor chip 200 may be homogeneously bonded. Specifically, in the second dummy bonding pad 320B and the third dummy bonding pad 320C, the second lower dummy bonding pad 321A and the first upper inter-chip insulating layer 250B are in contact with each other but are not directly bonded. Alternatively, in the semiconductor package 1, the second lower dummy bonding pad 321A and the second upper dummy bonding pad 321B are directly bonded, and the second lower dummy bonding pad 321A and the third upper dummy bonding pad 321C are directly bonded; therefore, heterogeneous bonding does not occur at the first direct bonding interface IDB1.

[0073] As described above, the direct bonding between the first semiconductor chip 100 and the second semiconductor chip 200 can include direct bonding between conductive components and direct bonding between insulating components. In direct bonding, since homogeneous bonding is formed in the semiconductor package 1, the bond strength of the direct bonding between the first semiconductor chip 100 and the second semiconductor chip 200 can be greater than when heterogeneous bonding is performed between the first semiconductor chip 100 and the second semiconductor chip 200. In the semiconductor package 1 in which components are directly bonded by homogeneous bonding, the possibility of defects such as warpage of the semiconductor package 1, peeling between the first semiconductor chip 100 and the second semiconductor chip 200, or short circuits between the first semiconductor chip 100 and the second semiconductor chip 200 can be reduced. Therefore, since only homogeneous bonding is performed in the direct bonding between semiconductor chips, the reliability of the semiconductor package 1 according to the embodiment can be improved.

[0074] The first region TA1 can be defined as the region including the first bonding pad 240 between the first semiconductor chip 100 and the second semiconductor chip 200. For example... Figures 1 to 3As shown, when the first semiconductor chip 100 and the second semiconductor chip 200 are rectangular in shape in the plan view, the first region TA1 can also be rectangular in shape in the plan view. The first region TA1 may include a first bonding pad 240 in the first region TA1, and subsequently in Figure 7 The internal virtual bonding pad 310A described in the text, and then in Figure 8 The sixth dummy bonding pad 320F or later described in the text Figure 9 At least a portion of the seventh dummy bonding pad 320G described herein may be included within the first region TA1. See below for reference. Figures 7 to 9 Provide additional descriptions for the first region TA1.

[0075] Figure 4 It is the semiconductor package 1A and Figure 1 A sectional view of the same portion B-B'. Descriptions not given below are substantially the same as those given above.

[0076] Reference Figure 4 The second semiconductor chip 200 may further include a fourth upper dummy bonding pad 323D on the bottom surface of the second semiconductor chip 200. The first semiconductor chip 100 may further include a fourth lower dummy bonding pad 323A on the top surface of the first semiconductor chip 100. The fourth upper dummy bonding pad 323D and the fourth lower dummy bonding pad 323A may be directly bonded to each other. The fourth upper dummy bonding pad 323D and the fourth lower dummy bonding pad 323A directly bonded to each other may be referred to as the fourth dummy bonding pad 320D. The fourth dummy bonding pad 320D may not be electrically connected to the first semiconductor chip 100 and the second semiconductor chip 200. In one or more examples, the fourth dummy bonding pad 320D may not be electrically connected to the first semiconductor chip 100 or the second semiconductor chip 200.

[0077] For example, such as Figure 4 As shown, a plurality of fourth dummy bonding pads 320D may be arranged along the second chip perimeter 210SA. The fourth dummy bonding pads 320D may have a strip-like shape extending along the second chip perimeter 210SA. In one or more examples, the fourth lower dummy bonding pad 323A and the fourth upper dummy bonding pad 323D may each have a strip-like shape extending along the second chip perimeter 210SA. The fourth upper dummy bonding pad 323D is indicated by a dashed line, and the fourth lower dummy bonding pad 323A is indicated by a solid line. In one or more examples, as shown in 4, a plurality of fourth dummy bonding pads 320D may be symmetrically arranged around the center of the second semiconductor chip 200.

[0078] For example, a plurality of fourth lower dummy bonding pads 323A may be arranged along the second chip perimeter 210SA on the top surface of the first semiconductor chip 100. In one or more examples, the plurality of fourth lower dummy bonding pads 323A may be arranged such that the second chip perimeter 210SA is superimposed on the plurality of fourth lower dummy bonding pads 323A. A fourth upper dummy bonding pad 323D may be arranged along the second chip perimeter 210SA, but the fourth upper dummy bonding pad 323D may be arranged not to deviate from (detach from) the inside of the second chip perimeter 210SA. In one or more examples, one surface of the fourth upper dummy bonding pad 323D may be aligned with the second chip perimeter 210SA in a direction perpendicular to the surface of the second semiconductor chip 200.

[0079] The shape of the fourth upper dummy bonding pad 323D in the plan view can be substantially consistent with a portion of the shape of the fourth lower dummy bonding pad 323A in the plan view. Therefore, when the fourth upper dummy bonding pad 323D and the fourth lower dummy bonding pad 323A are directly bonded, the portion of the fourth lower dummy bonding pad 323A that does not match the fourth upper dummy bonding pad 323D may not contact the fourth upper dummy bonding pad 323D. Therefore, the encapsulation member 270 can contact the portion of the fourth lower dummy bonding pad 323A that does not match the fourth upper dummy bonding pad 323D.

[0080] The length of the fourth dummy bonding pad 320D in its extension direction may be referred to as a first length L1, and the length of the fourth dummy bonding pad 320D in its thickness direction based on the length direction may be referred to as a second length L2. The first length L1 may be greater than the second length L2. The first length L1 may, for example, be in the range from about 20 μm to about 1 mm. The second length L2 may, for example, be in the range from about 10 μm to about 200 μm. However, this disclosure is not limited by the numerical values ​​of the first length L1 and the second length L2.

[0081] In a semiconductor package 1A in which components are directly bonded via homogeneous bonding, the likelihood of defects such as warpage of the semiconductor package 1A, peeling between the first semiconductor chip 100 and the second semiconductor chip 200, or short circuits between the first semiconductor chip 100 and the second semiconductor chip 200 can be reduced. In one or more examples, the semiconductor package 1A may have a larger direct bonding portion of homogeneous bonding between the first semiconductor chip 100 and the second semiconductor chip 200 via a fourth dummy bonding pad 320D. Therefore, since only homogeneous bonding is performed in the direct bonding between semiconductor chips in the semiconductor package 1A, the reliability of the semiconductor package 1A according to the embodiment can be improved.

[0082] Figure 5 It is the semiconductor package 1B and Figure 1A sectional view of the same portion B-B'. Descriptions not given below are substantially the same as those given above.

[0083] Reference Figure 5 The second semiconductor chip 200 may further include a fifth upper dummy bonding pad 322E on the bottom surface of the second semiconductor chip 200. The first semiconductor chip 100 may further include a fifth lower dummy bonding pad 322A on the top surface of the first semiconductor chip 100. The fifth upper dummy bonding pad 322E and the fifth lower dummy bonding pad 322A may be directly bonded to each other. The fifth upper dummy bonding pad 322E and the fifth lower dummy bonding pad 322A may be referred to as the fifth dummy bonding pad 320E. The fifth dummy bonding pad 320E may not be electrically connected to the first semiconductor chip 100 and the second semiconductor chip 200. In one or more examples, the fifth dummy bonding pad 320E may not be electrically connected to either the first semiconductor chip 100 or the second semiconductor chip 200.

[0084] For example, such as Figure 5 As shown, multiple fifth dummy bonding pads 320E may be arranged along the second chip perimeter 210SA. The fifth dummy bonding pads 320E may extend along the second chip perimeter 210SA, but may have an "L-shaped" bend (bend) at a portion of the fifth dummy bonding pad 320E. In one or more examples, the fifth lower dummy bonding pad 322A and the fifth upper dummy bonding pad 322E may each extend along the second chip perimeter 210SA, but may have an "L-shaped" bend in the middle. The fifth upper dummy bonding pad 322E is indicated by a dashed line, and the fifth lower dummy bonding pad 322A is indicated by a solid line. In one or more examples, as... Figure 5 As shown, a plurality of fifth dummy bonding pads 320E may be symmetrically arranged around the center of the second semiconductor chip 200.

[0085] For example, a plurality of fifth lower dummy bonding pads 322A may be arranged along the second chip perimeter 210SA on the top surface of the first semiconductor chip 100. The plurality of fifth lower dummy bonding pads 322A may be arranged such that the second chip perimeter 210SA is superimposed on the plurality of fifth lower dummy bonding pads 322A. A fifth upper dummy bonding pad 322E may be arranged along the second chip perimeter 210SA, but the fifth upper dummy bonding pad 322E may be arranged without deviating (detaching) from the inside of the second chip perimeter 210SA. In one or more examples, one surface of the fifth upper dummy bonding pad 322E may be aligned with the second chip perimeter 210SA in a direction perpendicular to the surface of the second semiconductor chip 200.

[0086] The shape of the fifth upper dummy bonding pad 322E in the plan view can be substantially consistent with a portion of the shape of the fifth lower dummy bonding pad 322A in the plan view. Therefore, when the fifth upper dummy bonding pad 322E and the fifth lower dummy bonding pad 322A are directly bonded, the portion of the fifth lower dummy bonding pad 322A that does not match the fifth upper dummy bonding pad 322E may not contact the fifth upper dummy bonding pad 322E. Therefore, the encapsulation member 270 can contact the portion of the fifth lower dummy bonding pad 322A that does not match the fifth upper dummy bonding pad 322E.

[0087] In a semiconductor package 1B in which components are directly bonded via homogeneous bonding, a fifth dummy bonding pad 320E may be disposed at the apex (e.g., folded portion) of the second chip perimeter 210SA of the second semiconductor chip 200. The apex of the second chip perimeter 210SA of the second semiconductor chip 200 may be susceptible to peeling occurring between the first semiconductor chip 100 and the second semiconductor chip 200. The bonding strength between the first semiconductor chip 100 and the second semiconductor chip 200 may be increased by the fifth dummy bonding pad 320E. Therefore, the reliability of the semiconductor package 1B according to the embodiment can be improved.

[0088] Figure 6 It is a semiconductor package IC and Figure 1 A sectional view of the same portion B-B'. Descriptions not given below are substantially the same as those given above.

[0089] Reference Figure 6 The semiconductor package 1C may together include a fourth dummy bonding pad 320D and a fifth dummy bonding pad 320E. A detailed description of the fourth dummy bonding pad 320D is provided above. Figure 4 The detailed description of the fifth dummy bonding pad 320E is given above and can be found in the reference above. Figure 5 It was given.

[0090] Figure 7 It is the semiconductor package 1D and Figure 1 A sectional view of the same part B-B'. Figure 8 It is the semiconductor package 1E and Figure 1 A sectional view of the same part B-B'. Figure 9 It is the semiconductor package 1F and Figure 1 A sectional view of the same portion B-B'. Descriptions not given below are substantially the same as those given above.

[0091] Reference Figure 7According to an embodiment, the semiconductor package 1D may further include an inner dummy bonding pad 310A between the first semiconductor chip 100 and the second semiconductor chip 200. Similar to the first dummy bonding pad 310, the inner dummy bonding pad 310A may be formed as an inner upper dummy bonding pad and an inner lower dummy bonding pad having the same shape and directly bonded to each other, and is not electrically connected to the first semiconductor chip 100 and / or the second semiconductor chip 200. The shape of the inner dummy bonding pad 310A in a plan view may be the same as the shape of the first dummy bonding pad 310 in a plan view, and for example, the shape of the inner dummy bonding pad 310A in a plan view may be circular.

[0092] The internal dummy bonding pad 310A can be disposed inside the first region TA1, rather than adjacent to the second chip perimeter 210SA. In other words, the internal dummy bonding pad 310A can be disposed adjacent to the first bonding pad 240. For example, as Figure 7 As shown, the internal dummy bonding pad 310A can be positioned adjacent to one or more first bonding pads 240.

[0093] Reference Figure 8 The semiconductor package 1E according to an embodiment may further include a sixth dummy bonding pad 320F between the first semiconductor chip 100 and the second semiconductor chip 200. The sixth dummy bonding pad 320F can be formed by directly bonding a sixth upper dummy bonding pad 324B and a sixth lower dummy bonding pad 324A of the same shape, and is not electrically connected to the first semiconductor chip 100 and the second semiconductor chip 200. The shape of the sixth dummy bonding pad 320F in a plan view may be, for example, a "strip shape" extending in one direction.

[0094] The sixth dummy bonding pad 320F can be disposed within the first region TA1, rather than adjacent to the second chip perimeter 210SA. In other words, the sixth dummy bonding pad 320F can be disposed adjacent to the first bonding pad 240. For example, as Figure 8 As shown, the sixth dummy bonding pad 320F may be positioned adjacent to a plurality of first bonding pads 240. In one or more examples, according to other embodiments, at least a portion of the sixth dummy bonding pad 320F may extend outside the first region TA1.

[0095] Reference Figure 9According to an embodiment, the semiconductor package 1F may further include a seventh dummy bonding pad 320G and an inner dummy bonding pad 310A between the first semiconductor chip 100 and the second semiconductor chip 200. The seventh dummy bonding pad 320G can be formed by directly bonding a seventh upper dummy bonding pad 325G and a seventh lower dummy bonding pad 325A of the same shape, and is not electrically connected to the first semiconductor chip 100 and the second semiconductor chip 200. The shape of the seventh dummy bonding pad 320G in a plan view can be, for example, an "L-shape" with a partial bend. The inner dummy bonding pad 310A... Figure 7 It is described in detail in the text.

[0096] The seventh dummy bonding pad 320G is partially adjacent to the second chip perimeter 210SA. Furthermore, at least a portion of the seventh dummy bonding pad 320G may be disposed within the first region TA1. For example, as... Figure 9 As shown, the portion of the seventh dummy bonding pad 320G, excluding the bent portion, may be positioned within the first region TA1. At least a portion of the seventh dummy bonding pad 320G may be configured to be adjacent to the first bonding pad 240. For example, as... Figure 9 As shown, the seventh dummy bonding pad 320G may be positioned adjacent to a plurality of first bonding pads 240. In one or more examples, the seventh dummy bonding pad 320G may be positioned adjacent to the inner dummy bonding pad 310A. In one or more examples, according to other embodiments, the entire portion of the seventh dummy bonding pad 320G may be disposed within the first region TA1.

[0097] exist Figures 7 to 9 In each of the semiconductor packages 1D, 1E, and 1F, a dummy bonding pad may be disposed within a first region TA1 located between the first semiconductor chip 100 and the second semiconductor chip 200 and spaced apart from the second chip perimeter 210SA of the second semiconductor chip 200, thereby ensuring bonding strength within the first semiconductor chip 100 and the second semiconductor chip 200. Therefore, the reliability of the semiconductor packages 1D, 1E, and 1F according to the embodiments can be ensured.

[0098] Figure 10 It is a semiconductor package 1G and Figure 1 A sectional view of the same portion B-B'. Descriptions not given below are substantially the same as those given above.

[0099] Reference Figure 10 According to the embodiments, the semiconductor package 1G may include an eighth dummy bonding pad 330, a ninth dummy bonding pad 330B and a tenth dummy bonding pad 330C between the first semiconductor chip 100 and the second semiconductor chip 200.

[0100] The eighth dummy bonding pad 330, the ninth dummy bonding pad 330B, and the tenth dummy bonding pad 330C are not electrically connected to the first semiconductor chip 100 and the second semiconductor chip 200. The eighth dummy bonding pad 330 is formed by directly bonding an eighth upper dummy bonding pad and an eighth lower dummy bonding pad that have substantially the same shape in a plan view. The ninth dummy bonding pad 330B is formed by directly bonding a ninth upper dummy bonding pad 331B and a ninth lower dummy bonding pad 331A. The tenth dummy bonding pad 330C is formed by directly bonding a tenth upper dummy bonding pad 331C and a ninth lower dummy bonding pad 331A.

[0101] For example, such as Figure 10 As shown, a plurality of ninth dummy bonding pads 330B and a plurality of tenth dummy bonding pads 330C may be arranged along the second chip perimeter 210SA. The tenth dummy bonding pads 330C may be located at the apex (bent portion) of the second chip perimeter 210SA.

[0102] The ninth dummy bonding pad 330B and the tenth dummy bonding pad 330C may have a rectangular shape.

[0103] For example, a plurality of ninth lower dummy bonding pads 331A may be arranged along the second chip perimeter 210SA on the top surface of the first semiconductor chip 100. In one or more examples, the plurality of ninth lower dummy bonding pads 331A may be arranged such that the plurality of ninth lower dummy bonding pads 331A overlap with the second chip perimeter 210SA. Ninth upper dummy bonding pads 331B may be arranged along the second chip perimeter 210SA, but the ninth upper dummy bonding pads 331B may be arranged not to deviate from (detach from) the inside of the second chip perimeter 210SA.

[0104] The shape of the ninth upper dummy bonding pad 331B in the planar view can be substantially the same as a portion of the shape of the ninth lower dummy bonding pad 331A in the planar view. For example, as Figure 10 As shown, the ninth lower dummy bonding pad 331A can be rectangular in shape in the plan view, and the ninth upper dummy bonding pad 331B can be a rectangle with half the size of the rectangular shape of the ninth lower dummy bonding pad 331A in the plan view.

[0105] When the ninth upper dummy bonding pad 331B and the ninth lower dummy bonding pad 331A are directly bonded, the portion of the ninth lower dummy bonding pad 331A that does not match the ninth upper dummy bonding pad 331B may not contact the ninth upper dummy bonding pad 331B. Therefore, the encapsulation member 270 may contact the portion of the ninth lower dummy bonding pad 331A that does not match the ninth upper dummy bonding pad 331B.

[0106] For example, the tenth dummy bonding pad 331C can be arranged along the perimeter 210SA of the second chip, but the tenth dummy bonding pad 331C can be arranged so as not to deviate (detach) from the inside of the perimeter 210SA of the second chip.

[0107] The shape of the tenth upper dummy bonding pad 331C in the planar view can be substantially the same as a portion of the shape of the ninth lower dummy bonding pad 331A in the planar view. For example, as Figure 10 As shown, the ninth lower dummy bonding pad 331A can be rectangular in shape in the plan view, and the tenth upper dummy bonding pad 331C can be a rectangle with a size of 1 / 4 of the rectangular shape of the ninth lower dummy bonding pad 331A in the plan view. The encapsulation member 270 can contact the portion of the ninth lower dummy bonding pad 331A that does not match the tenth upper dummy bonding pad 331C.

[0108] In a semiconductor package 1G in which components are directly bonded via homogeneous bonding, the likelihood of defects such as warpage of the semiconductor package 1G, peeling between the first semiconductor chip 100 and the second semiconductor chip 200, or short circuits between the first semiconductor chip 100 and the second semiconductor chip 200 can be reduced. Therefore, since only homogeneous bonding is performed in the direct bonding between semiconductor chips, the reliability of the semiconductor package 1G according to the embodiment can be improved.

[0109] Figure 11 This is a cross-sectional view of the semiconductor package 2 according to an embodiment. Figure 12 yes Figure 11 An enlarged sectional view of part D. Figure 13 It is along Figure 11 A partial cross-sectional view taken from E-E' in the plan view. Based on semiconductor package 2 and... Figures 1 to 3 Description of differences between semiconductor packages 1 Figures 11 to 13 .

[0110] Reference Figures 11 to 13 According to an embodiment, the semiconductor package 2 may include a first semiconductor chip 400 and a second semiconductor chip 500 disposed on the first semiconductor chip 400. The shape of the first semiconductor chip 400 in a plan view may be larger than the shape of the second semiconductor chip 500 in a plan view.

[0111] The second semiconductor chip 500 may include a second semiconductor substrate 510, a second semiconductor device 534 disposed on one surface of the second semiconductor substrate 510, a second front insulating layer 533 disposed on the front surface (or bottom surface) of the second semiconductor substrate 510 and covering the second semiconductor device 534, a second wiring pattern 530 disposed in the second front insulating layer 533 including a second line pattern 531 and a second via pattern 532, a first upper bonding pad 240B disposed on the second front insulating layer 533, a first upper dummy bonding pad 311B disposed on the second front insulating layer 533, a second upper dummy bonding pad 321B and a third upper dummy bonding pad 321C disposed on the bottom surface of the second front insulating layer 533, and a first upper inter-chip insulating layer 250B disposed on the bottom surface of the second front insulating layer 533. According to the design, the second semiconductor chip 500 may also include a second via electrode passing through at least a portion of the second semiconductor substrate 510.

[0112] The first semiconductor chip 400 may include a first semiconductor substrate 410, a first via electrode 420 that vertically passes through at least a portion of the first semiconductor substrate 410, a first semiconductor device disposed on one surface of the first semiconductor substrate 410, a first front insulating layer 433 disposed on the front surface (or bottom surface) of the first semiconductor substrate 410, a first wiring pattern 430 disposed in the first front insulating layer 433, a first lower inter-chip insulating layer 250A disposed on the top surface of the first semiconductor substrate 410, a first lower bonding pad 240A disposed on the top surface of the first semiconductor substrate 410, a first lower dummy bonding pad 311A ​​and a second lower dummy bonding pad 321A disposed on the top surface of the first semiconductor substrate 410, a first front pad 450 disposed on the bottom surface of the first semiconductor chip 400, and a first lower passivation layer 470 surrounding a portion of the first front pad 450.

[0113] The first semiconductor chip 400 and the second semiconductor chip 500 can be chiplets constituting a multi-chip module (MCM). In this case, the number of second semiconductor chips 500 stacked vertically or horizontally on the first semiconductor chip 400 can be one or more. The first semiconductor chip 400 can be a logic chip including, for example, a central processing unit (CPU), a graphics processing unit (GPU), a field-programmable gate array (FPGA), an application processor (AP), a digital signal processor (DSP), a cryptographic processor, a microprocessor, a microcontroller, an analog-to-digital converter, an application-specific integrated circuit (ASIC), etc., and the second semiconductor chip 500 can be a memory chip such as DRAM, SRAM, PRAM, MRAM, FeRAM, or RRAM.

[0114] remove Figures 1 to 3 Outside the second via electrode 220, Figures 11 to 13The descriptions of the first dummy bonding pad 310, the second dummy bonding pad 320B, and the third dummy bonding pad 320C are consistent with... Figures 1 to 3 The descriptions of the first dummy bonding pad 310, the second dummy bonding pad 320B, and the third dummy bonding pad 320C are substantially the same. For example, the boundary formed by the side surface of the second semiconductor chip 500 may be referred to as the second chip perimeter 510SA. A portion of the second lower dummy bonding pad 321A may be located inside the second chip perimeter 510SA of the second semiconductor chip 500, and the remaining portion of the second lower dummy bonding pad 321A may be located outside the second chip perimeter 510SA.

[0115] The specification describes the components as "bottom," "top," etc. In one or more examples, these components may optionally (or alternatively) be exposed as:

[0116] While this disclosure has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, comprising: The first semiconductor chip includes a first semiconductor substrate and a first via electrode that passes through at least a portion of the first semiconductor substrate; A second semiconductor chip is disposed on the first semiconductor chip and includes a second semiconductor substrate; A first bonding pad structure is located between the first semiconductor chip and the second semiconductor chip; The first dummy bonding pad structure is located between the first semiconductor chip and the second semiconductor chip; as well as A first inter-chip insulating layer and a second inter-chip insulating layer, wherein the first inter-chip insulating layer is on the surface of the first semiconductor chip, and the second inter-chip insulating layer is on the surface of the second semiconductor chip. The first bonding pad structure includes: a first bonding pad on the surface of the first semiconductor chip; and a second bonding pad on the surface of the second semiconductor chip. The first dummy bonding pad structure includes: a first dummy bonding pad on the surface of the first semiconductor chip; and a second dummy bonding pad on the surface of the second semiconductor chip. The second bonding pad and the first bonding pad are in contact with each other and are directly bonded to each other. In this configuration, the second dummy bonding pad and the first dummy bonding pad are in contact with each other and are directly bonded to each other. At least a portion of the first inter-chip insulating layer and the second inter-chip insulating layer are in contact with each other and are directly bonded to each other.

2. The semiconductor package according to claim 1, wherein, The second bonding pad and the second dummy bonding pad do not contact the insulating layer between the first chip, and The first bonding pad and the first dummy bonding pad do not contact the insulating layer between the second chip.

3. The semiconductor package according to claim 1, wherein, The first bonding pad structure electrically connects the first semiconductor chip and the second semiconductor chip to each other, and The first dummy bonding pad structure is not electrically connected to the first semiconductor chip and the second semiconductor chip.

4. The semiconductor package according to claim 1, further comprising: A second dummy bonding pad structure is located between the first semiconductor chip and the second semiconductor chip. The second dummy bonding pad structure includes: a third dummy bonding pad disposed on the surface of the first semiconductor chip; and a fourth dummy bonding pad disposed on the surface of the second semiconductor chip. The fourth dummy bonding pad and the third dummy bonding pad are not electrically connected to the first semiconductor chip and the second semiconductor chip, respectively.

5. The semiconductor package according to claim 4, wherein, A portion of the third dummy bonding pad protrudes from the perimeter of the second semiconductor chip toward the perimeter of the first semiconductor chip.

6. The semiconductor package according to claim 4, wherein, One surface of the fourth dummy bonding pad is aligned in one direction with the second chip perimeter of the second semiconductor chip, wherein the direction is perpendicular to the surface of the second semiconductor chip.

7. The semiconductor package according to claim 4, wherein, The fourth dummy bonding pad contacts a portion of the third dummy bonding pad, and the remaining portion of the third dummy bonding pad does not contact the second inter-chip insulating layer.

8. The semiconductor package according to claim 4, wherein, The second dummy bonding pad structure has a strip shape and extends along the second chip perimeter of the second semiconductor chip.

9. The semiconductor package according to claim 8, wherein, The first length is greater than the second length. The first length is the length of one side of the second dummy bonding pad structure, and the second length is the length of the other side of the second dummy bonding pad structure that is connected to the first side. The first length is 20μm to 1mm, and The second length is 10 μm to 200 μm.

10. The semiconductor package according to claim 4, wherein, The second dummy bonding pad structure has an L-shape, the L-shape having a curved portion, and the second dummy bonding pad structure extends along the second chip perimeter of the second semiconductor chip.

11. The semiconductor package according to claim 8 or 10, wherein, The second dummy bond pad structure is one of multiple second dummy bond pad structures, and The plurality of second dummy bonding pad structures are symmetrically arranged around the center of the second semiconductor chip.

12. The semiconductor package according to claim 4, further comprising: Encapsulation components on the first semiconductor chip The encapsulation component surrounds the second semiconductor chip. In this configuration, a portion of the third dummy bonding pad contacts the encapsulation member, and the remaining portion of the third dummy bonding pad contacts the fourth dummy bonding pad.

13. The semiconductor package according to claim 1, further comprising: A third dummy bonding pad structure is located between the first semiconductor chip and the second semiconductor chip. The third dummy bonding pad structure includes: a fifth dummy bonding pad on the surface of the first semiconductor chip; and a sixth dummy bonding pad on the surface of the second semiconductor chip. The third dummy bonding pad structure is not electrically connected to the first semiconductor chip and the second semiconductor chip, and At least a portion of the third dummy bonding pad structure is located within a first region, which is between the first semiconductor chip and the second semiconductor chip and includes the first bonding pad structure.

14. The semiconductor package of claim 13, wherein, The third dummy bonding pad structure has a strip shape and extends along the second chip perimeter of the second semiconductor chip.

15. The semiconductor package according to claim 1, wherein, The first semiconductor chip includes a buffer chip. The second semiconductor chip includes a memory chip. The second semiconductor chip includes at least one second semiconductor chip stacked on the first semiconductor chip, and The second semiconductor chip also includes a second via electrode that passes through at least a portion of the second semiconductor substrate.

16. A semiconductor package, comprising: The first semiconductor chip includes a first semiconductor substrate and a first via electrode that passes through at least a portion of the first semiconductor substrate; A second semiconductor chip is disposed on the first semiconductor chip and includes a second semiconductor substrate; A first bonding pad structure is located between the first semiconductor chip and the second semiconductor chip; The first dummy bonding pad structure is located between the first semiconductor chip and the second semiconductor chip; A second dummy bonding pad structure is located between the first semiconductor chip and the second semiconductor chip; A first inter-chip insulating layer is disposed on the surface of the first semiconductor chip; The second inter-chip insulating layer is on the surface of the second semiconductor chip; as well as Encapsulation components are present on the first semiconductor chip and surrounding the second semiconductor chip. The first bonding pad structure includes: a first bonding pad on the surface of the first semiconductor chip; and a second bonding pad on the surface of the second semiconductor chip. The first dummy bonding pad structure includes: a first dummy bonding pad on the surface of the first semiconductor chip; and a second dummy bonding pad on the surface of the second semiconductor chip. The second dummy bonding pad structure includes: a third dummy bonding pad on the surface of the first semiconductor chip; and a fourth dummy bonding pad on the surface of the second semiconductor chip. The second bonding pad and the first bonding pad are in contact with each other and are directly bonded to each other. In this configuration, the second dummy bonding pad and the first dummy bonding pad are in contact with each other and are directly bonded to each other. In this configuration, at least a portion of the first inter-chip insulating layer and the second inter-chip insulating layer are in contact with each other and are directly bonded to each other. The first semiconductor chip has a larger shape than the second semiconductor chip, and In this embodiment, one surface of the fourth dummy bonding pad is aligned with the second chip perimeter of the second semiconductor chip in one direction, wherein the direction is perpendicular to the surface of the second semiconductor chip.

17. The semiconductor package of claim 16, wherein, The second bonding pad, the second dummy bonding pad, the fourth dummy bonding pad, and the insulating layer between the first chip do not contact each other. The first bonding pad, the first dummy bonding pad, the third dummy bonding pad, and the insulating layer between the second chip do not contact each other, and The fourth dummy bonding pad contacts a portion of the third dummy bonding pad, and the remaining portion of the third dummy bonding pad contacts the encapsulation member.

18. The semiconductor package of claim 16, wherein, The first semiconductor chip includes a buffer chip, and the second semiconductor chip includes a memory chip. The first bonding pad structure electrically connects the first semiconductor chip and the second semiconductor chip to each other, and The first dummy bonding pad structure and the second dummy bonding pad structure are not electrically connected to the first semiconductor chip and the second semiconductor chip, respectively.

19. The semiconductor package of claim 16, further comprising: A third dummy bonding pad structure is disposed between the first semiconductor chip and the second semiconductor chip. The third dummy bonding pad structure includes: a fifth dummy bonding pad on the surface of the first semiconductor chip; and a sixth dummy bonding pad on the surface of the second semiconductor chip. The third dummy bonding pad structure is not electrically connected to the first semiconductor chip and the second semiconductor chip. Wherein, at least a portion of the third dummy bonding pad structure is located in the first region, and The first region is defined as the region between the first semiconductor chip and the second semiconductor chip, and the first region includes a first bonding pad structure but does not include a second dummy bonding pad structure.

20. A semiconductor package, comprising: The first semiconductor chip includes a first semiconductor substrate and a first via electrode that passes through at least a portion of the first semiconductor substrate; A second semiconductor chip is disposed on the first semiconductor chip and includes a second semiconductor substrate; A first bonding pad structure is located between the first semiconductor chip and the second semiconductor chip; The first dummy bonding pad structure is located between the first semiconductor chip and the second semiconductor chip; A second dummy bonding pad structure is located between the first semiconductor chip and the second semiconductor chip; A third dummy bonding pad structure is located between the first semiconductor chip and the second semiconductor chip; A first inter-chip insulating layer and a second inter-chip insulating layer, wherein the first inter-chip insulating layer is on the surface of the first semiconductor chip and the second inter-chip insulating layer is on the surface of the second semiconductor chip; as well as Encapsulation components are present on the first semiconductor chip and surrounding the second semiconductor chip. The first bonding pad structure includes: a first bonding pad on the surface of the first semiconductor chip; and a second bonding pad on the surface of the second semiconductor chip. The first dummy bonding pad structure includes: a first dummy bonding pad on the surface of the first semiconductor chip; and a second dummy bonding pad on the surface of the second semiconductor chip. The second dummy bonding pad structure includes: a third dummy bonding pad on the surface of the first semiconductor chip; and a fourth dummy bonding pad on the surface of the second semiconductor chip. The third dummy bonding pad structure includes: a fifth dummy bonding pad on the surface of the first semiconductor chip; and a sixth dummy bonding pad on the surface of the second semiconductor chip. The second bonding pad and the first bonding pad are in contact with each other and are directly bonded to each other. In this configuration, the second dummy bonding pad and the first dummy bonding pad are in contact with each other and are directly bonded to each other. In this configuration, at least a portion of the first inter-chip insulating layer and the second inter-chip insulating layer are in contact with each other and are directly bonded to each other. In this configuration, one surface of the fourth dummy bonding pad is aligned with the perimeter of the second semiconductor chip in one direction, wherein said direction is perpendicular to the surface of the second semiconductor chip. Each of the first dummy bonding pad structure, the second dummy bonding pad structure, and the third dummy bonding pad structure is not electrically connected to the first semiconductor chip and the second semiconductor chip. Wherein, at least a portion of the third dummy bonding pad structure is located in the first region, and The first region is defined as the region between the first semiconductor chip and the second semiconductor chip, and the first region includes a first bonding pad structure but does not include a second dummy bonding pad structure.

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