Parallel interface test method, system and device
By determining the sampling point sequence in parallel interface testing and stopping the test when the bit error reaches the threshold, the problem of excessively long testing time in the prior art is solved, and a more efficient testing process is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- PINGTOU GE (HANGZHOU) SEMICON CO LTD
- Filing Date
- 2025-12-29
- Publication Date
- 2026-05-26
AI Technical Summary
The existing parallel interface SHMOO test requires traversing all combination points to test the data, which results in excessively long test times and severely reduces test efficiency.
By determining the sampling point sequence of the parallel interface, data transmission tests are performed on the target sampling points, and the test stops when the number of bit errors reaches a predetermined threshold, directly moving to the next sampling point, thus reducing the test time for a single sampling point.
It improves the testing efficiency of parallel interfaces, reduces the testing time for a single sampling point, and speeds up the testing process.
Smart Images
Figure CN122086718A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of computer technology, and in particular to a method, system, and apparatus for testing parallel interfaces. Background Technology
[0002] SHMOO testing is a method for evaluating the extreme performance and stability of parallel interfaces. By changing the operating conditions of the parallel interface (usually two key parameters) and observing whether the parallel interface can pass functional tests under these conditions, the safe area or operating range of the parallel interface can be plotted to discover design margins, optimize performance, and ensure the stability of the product under various operating conditions.
[0003] Currently, SHMOO testing iterates through all combinations of the two parameters, performs a complete data test on each combination, and records the corresponding number of bit errors. However, this approach requires extensive and comprehensive data testing for each combination, resulting in long testing times and significantly reducing testing efficiency. Summary of the Invention
[0004] In view of this, the purpose of this invention is to provide a testing method, system, and apparatus for parallel interfaces, which can reduce the testing time of a single sampling point and improve the testing efficiency of parallel interfaces.
[0005] In a first aspect, embodiments of the present invention provide a method for testing a parallel interface, the method comprising: Determine the sampling point sequence corresponding to the parallel interface to be tested. The sampling point sequence includes multiple sampling points, and the sampling points are a combination of timing parameters and reference voltage of the parallel interface to be tested. Determine the target sampling point that needs to be processed in the sampling point sequence; Based on the target timing parameters and target reference voltage corresponding to the target sampling point, a data transmission test is performed on the parallel interface under test, and the number of bit errors during the data transmission test is recorded. In response to the number of bit errors being greater than or equal to a predetermined threshold, the target sampling point is identified as a failure point, the data transmission test on the target sampling point is stopped, and the next sampling point to be processed is determined in the sampling point sequence.
[0006] In some embodiments, the method further includes: In response to the completion of the data transmission test and the number of bit errors being less than a predetermined threshold, the target sampling point is determined as a valid point.
[0007] In some embodiments, determining the sampling point sequence corresponding to the parallel interface to be tested includes: Obtain the timing parameter range, reference voltage range, first step value, and second step value corresponding to the parallel interface under test. The first step value is the step value corresponding to the timing parameter, and the second step value is the step value corresponding to the reference voltage. The sampling point sequence corresponding to the parallel interface under test is determined based on the timing parameter range, the reference voltage range, the first step value, and the second step value.
[0008] In some embodiments, the step of performing data transmission testing on the parallel interface under test based on the target timing parameters and target reference voltage corresponding to the target sampling point, and recording the number of bit errors during the data transmission test, includes: The operating parameters of the parallel interface are adjusted to the target timing parameters and target reference voltage corresponding to the target sampling point; Send a test data stream to the parallel interface under test and obtain the read-back data stream after processing by the parallel interface under test; The number of errors is determined based on the test data stream and the readback data stream.
[0009] In some embodiments, the method further includes: The first test chart is generated based on the test results of each sampling point.
[0010] In some embodiments, generating the first test map based on the test results of each sampling point includes: A first coordinate system is established based on the timing parameter range and the reference voltage range, wherein the two coordinate axes of the first coordinate system are the timing parameters and the reference voltage, respectively. The display method is determined based on the test results of each sampling point, and the display methods for failure points and valid points are different. According to the display method, a display pattern is drawn at the corresponding position of each sampling point in the first coordinate system to obtain the first test image.
[0011] In some embodiments, the predetermined threshold is greater than or equal to 1.
[0012] In some embodiments, in response to the predetermined threshold being greater than 1, the method further includes: A second test chart is generated based on the test results of each sampling point.
[0013] In some embodiments, generating a second test map based on the test results of each sampling point includes: Obtain the number of bit errors corresponding to each sampling point; The display method is determined based on the number of bit errors, and different display methods correspond to different numbers of bit errors. The display pattern is drawn at the corresponding position in the second coordinate system according to the display method to obtain the second test image.
[0014] Secondly, embodiments of the present invention provide a testing system for a parallel interface, the system comprising: The test carrier board is used to provide a runtime environment for the parallel interface to be tested. An automated testing apparatus includes a memory and a processor, the memory being used to store one or more computer program instructions, wherein the one or more computer program instructions are executed by the processor to implement the method as described in the first aspect.
[0015] Thirdly, embodiments of the present invention provide a testing apparatus for a parallel interface, the apparatus comprising: A sequence determination unit is used to determine the sampling point sequence corresponding to the parallel interface under test. The sampling point sequence includes multiple sampling points, which are combinations of timing parameters and reference voltages of the parallel interface under test. A target sampling point determination unit is used to determine the target sampling point that needs to be processed in the sampling point sequence. The transmission test unit is used to perform data transmission tests on the parallel interface under test based on the target timing parameters and target reference voltage corresponding to the target sampling point, and record the number of bit errors during the data transmission test. The failure point determination unit is used to determine the target sampling point as a failure point in response to the number of bit errors being greater than or equal to a predetermined threshold, stop the data transmission test of the target sampling point, and determine the next sampling point to be processed in the sampling point sequence.
[0016] Fourthly, embodiments of the present invention provide an electronic device, including a memory and a processor, wherein the memory is used to store one or more computer program instructions, wherein the one or more computer program instructions are executed by the processor to implement the method as described in the first aspect.
[0017] Fifthly, embodiments of the present invention provide a computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, implement the method described in the first aspect.
[0018] In a sixth aspect, embodiments of the present invention provide a computer program product comprising a computer program, wherein when the computer program is run on a computer, the computer performs the method described in the first aspect above.
[0019] The technical solution of this invention determines the sampling point sequence corresponding to the parallel interface under test, identifies the target sampling point to be processed in the sampling point sequence, and performs data transmission testing on the parallel interface under test based on the target timing parameters and target reference voltage corresponding to the target sampling point. The number of bit errors during the data transmission test is recorded. When the number of bit errors reaches a predetermined threshold, the target sampling point is identified as a failure point, the data transmission test on the target sampling point is stopped, and the next sampling point is tested. Therefore, by setting a predetermined threshold, the next sampling point can be tested directly when the number of bit errors reaches the predetermined threshold, reducing the testing time for a single sampling point and improving the testing efficiency of the parallel interface. Attached Figure Description
[0020] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which: Figure 1 This is a schematic diagram of a test system for a parallel interface according to an embodiment of the present invention; Figure 2 This is a flowchart of a testing method for a parallel interface according to an embodiment of the present invention; Figure 3 This is a flowchart illustrating the acquisition of a sampling point sequence according to an embodiment of the present invention; Figure 4 This is a flowchart of the data transmission test according to an embodiment of the present invention; Figure 5 This is a flowchart illustrating the generation of the first test image according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the first test diagram according to an embodiment of the present invention; Figure 7 This is a flowchart illustrating the generation of the second test pattern according to an embodiment of the present invention; Figure 8 This is a schematic diagram of the opening in an embodiment of the present invention; Figure 9 This is a schematic diagram of eyelid thickness according to an embodiment of the present invention; Figure 10 This is a schematic diagram of the second test diagram according to an embodiment of the present invention; Figure 11 This is a schematic diagram of a test apparatus for a parallel interface according to an embodiment of the present invention; Figure 12 This is a schematic diagram of an electronic device according to an embodiment of the present invention. Detailed Implementation
[0021] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the substance of the present application, well-known methods, processes, flows, elements, and circuits are not described in detail.
[0022] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.
[0023] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".
[0024] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "a plurality of" means two or more.
[0025] The solutions described in this specification and embodiments, if involving the processing of personal information, will be processed only on the premise of having a legal basis (such as obtaining the consent of the personal information subject, or being necessary for the performance of a contract), and will only be processed within the scope stipulated or agreed upon. A user's refusal to process personal information beyond what is necessary for basic functions will not affect the user's use of basic functions.
[0026] A parallel interface is a communication interface that transmits multiple data bits simultaneously under the control of a single clock cycle or strobe signal using multiple independent data signal lines. The parallel interface can be any existing parallel interface, such as DDR (Double Data Rate) or D2D (Die-to-Die) interfaces. to Die (inter-die) interface and PCI (Peripheral Component Interconnect) interface. To ensure that the parallel interface can operate stably and reliably within the theoretically designed performance boundaries throughout its entire lifecycle and under various complex environments, it is necessary to test the parallel interface. This invention mainly involves SHMOO testing of the parallel interface.
[0027] SHMOO testing automatically and systematically scans the combination of two key operating parameters of the parallel interface (such as reference voltage and timing parameters) to plot a map showing the regions where the parallel interface can operate stably and where it will fail—this is the SHMOO plot. The SHMOO plot allows determination of the parameter range for normal operation of the parallel interface, as well as timing and voltage margins.
[0028] Figure 1 This is a schematic diagram of a test system for a parallel interface according to an embodiment of the present invention. Figure 1 As shown, the parallel interface testing system of this embodiment includes an automatic testing device 1 and a test carrier board 2. The automatic testing device 1 and the test carrier board 2 can be used to test the parallel interface 3 to be tested.
[0029] A parallel interface is a communication interface that transmits multiple data bits simultaneously under the control of a single clock cycle or strobe signal using multiple independent data signal lines. The parallel interface can be any existing parallel interface, such as DDR (Double Data Rate) or D2D (Die-to-Die) interfaces. to Die (inter-die) interface and PCI (Peripheral Component Interconnect) interface.
[0030] Test carrier board 2 is used to provide the operating environment for the parallel interface 3 under test. Specifically, test carrier board 2 is the physical bridge between automatic test equipment 1 and parallel interface 3 under test, and is used to realize functions such as power distribution, signal routing, termination matching, and decoupling.
[0031] Specifically, the test carrier board 2 can provide a normal operating environment for the parallel interface under test, including regulated power supply, reference clock, reset logic, necessary peripheral devices (termination, pull-up / pull-down capacitors, decoupling capacitors), and temperature control interface, so that the parallel interface can work normally during the test.
[0032] Meanwhile, the test carrier board 2 is also used to realize data communication between the automatic test equipment 1 and the parallel interface 3 under test, including transmitting the test data stream sent by the automatic test equipment to the parallel interface under test, and transmitting the read-back data stream obtained from the parallel interface under test to the automatic test equipment 1.
[0033] The automated test equipment 1 is used to execute the test process of the parallel interface 3 under test. Specifically, the automated test equipment 1 includes a timing parameter generation module, a power supply module, a memory, and a processor.
[0034] The timing parameter generation module is used to output timing parameters. The type of timing parameter can be determined based on the type of parallel interface; different types of parallel interfaces may correspond to different timing parameter types. This embodiment of the invention uses CLK (Clock) as an example for the timing parameter. CLK provides a sampling time reference for the parallel interface, informing the receiving end when to read data. If the phase, duty cycle, jitter, or relative timing of CLK deviates from the ideal value, it will lead to bit errors.
[0035] The power module is used to provide a reference voltage VREF, which is a logic threshold voltage used to determine whether the data is 0 or 1.
[0036] Furthermore, the timing parameter generation module and the power supply module are connected to the parallel interface under test 3 through the test carrier board 2, thereby providing reference voltage and timing parameters for the parallel interface under test 3.
[0037] The memory stores instructions that can be executed by at least one processor to implement the test method of the parallel interface of the present invention.
[0038] Specifically, the processor determines sampling points based on the timing parameter range and reference voltage range of the parallel interface under test. Each sampling point is a combination of the timing parameters and reference voltage of the parallel interface under test. Within these sampling points, a target sampling point is identified. Based on the target timing parameters and target reference voltage corresponding to the target sampling point, a data transmission test is performed on the parallel interface under test. The number of bit errors during the data transmission test is recorded. If the number of bit errors is greater than or equal to a predetermined threshold, the target sampling point is designated as a failure point, the data transmission test on the target sampling point is stopped, and the next sampling point is tested.
[0039] Figure 2 This is a flowchart of a testing method for a parallel interface according to an embodiment of the present invention. Figure 2 The test method shown is executed by automated test equipment to perform SHMOO testing on parallel interfaces. Figure 2 As shown, the testing method for the parallel interface in this embodiment of the invention includes the following steps: Step S100: Determine the sampling point sequence corresponding to the parallel interface to be tested.
[0040] In this embodiment, the sampling point sequence includes multiple sampling points, which are combinations of timing parameters and reference voltages of the parallel interface under test.
[0041] Figure 3 This is a flowchart illustrating the acquisition of a sampling point sequence according to an embodiment of the present invention. For example... Figure 3As shown, determining the sampling point sequence corresponding to the parallel interface to be tested includes the following steps: Step S110: Obtain the timing parameter range, reference voltage range, first step value, and second step value corresponding to the parallel interface under test.
[0042] In this embodiment, the timing parameter range, reference voltage range, first step value, and second step value corresponding to the parallel interface under test are obtained. The timing parameter range is a pre-determined operating range of the timing parameters corresponding to the parallel interface under test, and the reference voltage range is a pre-determined operating range of the reference voltage corresponding to the parallel interface under test. These two ranges can be determined according to the specifications of the parallel interface under test. For example, the timing parameter range and reference voltage range can be obtained by extending a certain scale both above and below the recommended timing parameters. Alternatively, they can be pre-set based on experience.
[0043] Furthermore, as described above, the sampling point is a combination of the timing parameters and the reference voltage of the parallel interface under test. That is, different sampling points are obtained by adjusting the timing parameters within the timing parameter range and / or adjusting the reference voltage within the reference voltage range, and the magnitude of this adjustment is a step value. The first step value is the step value corresponding to the timing parameters, and the second step value is the step value corresponding to the reference voltage. The first step value and the second step value can be preset.
[0044] Taking the parallel interface as an example of the DDR4 interface, the reference voltage range of the DDR4 interface can be [0.5, 0.7], in volts. The range of the clock signal CLK can be selected within... The range is approximately 0.3UI to 0.7UI, where UI is the time required to transmit 1 bit of data. Assuming UI = 625 ps, the clock signal CLK can have a range of [...]. [190, 440], in ps (picoseconds).
[0045] The first step value is the step value corresponding to the timing parameters, and the second step value is the step value corresponding to the reference voltage. Both the first and second step values can be preset. For example, the first step value can be between 1ps and 100ps, and the second step value can be between 1mV and 20mV.
[0046] Step S120: Determine the sampling point sequence corresponding to the parallel interface under test based on the timing parameter range, reference voltage range, first step value and second step value.
[0047] In this embodiment, starting from the minimum value in the timing parameter range, a scan is performed according to the first step value to obtain the point in the timing direction. Assuming the first step value is 10ps, the range of the clock signal CLK can be [ If the reference voltage range is [190ps, 440ps], then 64 points can be scanned in the timing direction. Using the same method, starting with the minimum value in the reference voltage range, scanning is performed according to the second step value to obtain points in the reference voltage direction. Assuming the second step value is 10mV, and the reference voltage range is [500mV, 700mV], then 21 points can be scanned in the reference voltage direction. The sampling points are combinations of the timing parameters and reference voltage of the parallel interface under test. The 64 points in the timing direction and the 21 points in the reference voltage direction can form 64 × 21 = 1344 combinations, resulting in 1344 sampling points.
[0048] Furthermore, the sampling points obtained above are sorted to obtain the sampling point sequence.
[0049] Step S200: Determine the target sampling point that needs to be processed in the sampling point sequence.
[0050] In this embodiment, the target sampling point that needs to be processed is determined in the sampling point sequence according to the order of sampling.
[0051] Step S300: Based on the target timing parameters and target reference voltage corresponding to the target sampling point, perform data transmission test on the parallel interface to be tested, and record the number of bit errors during the data transmission test.
[0052] In this embodiment, after obtaining the target sampling point, the parallel interface under test is controlled to work according to the reference voltage and timing parameters corresponding to the target sampling point, and a data transmission test is performed on the parallel interface under test, and the number of bit errors during the data transmission test is recorded.
[0053] Specifically, Figure 4 This is a flowchart of a data transmission test according to an embodiment of the present invention, which specifically includes the following steps: Step S310: Adjust the operating parameters of the parallel interface to the target timing parameters and target reference voltage corresponding to the target sampling point.
[0054] In this embodiment, after obtaining the target sampling point, the target reference voltage and target timing parameters corresponding to the target sampling point are determined, and the parallel interface under test is controlled to work according to the target reference voltage and target timing parameters.
[0055] Step S320: Send a test data stream to the parallel interface under test and obtain the read-back data stream after being processed by the parallel interface under test.
[0056] In this embodiment, a test data stream is acquired and sent to the parallel interface under test. The parallel interface under test reads the test data stream according to the target reference voltage and target timing parameters to obtain a read-back data stream. The parallel interface under test then returns the read-back data stream to the automated testing equipment.
[0057] In one optional implementation, the test data stream is predetermined, that is, the complete test data stream is provided to the automated test equipment in advance, and the automated test equipment can send the test data stream.
[0058] In another alternative implementation, the test data stream is generated in real time by an automated testing device based on an algorithm. For example, the automated testing device is equipped with a PRBS (Pseudo-Random Binary Sequence) generator, which is used to generate pseudo-random binary sequences, i.e., the test data stream.
[0059] The processes of the automatic test equipment sending test data streams to the parallel interface under test and retrieving data streams from the parallel interface under test are executed concurrently.
[0060] Step S330: Determine the bit errors based on the test data stream and the readback data stream, and record the number of bit errors.
[0061] In this embodiment, the same bits of data in the test data stream and the read-back data stream are compared to check if the read-back data stream is consistent with the test data stream. If they are inconsistent, it indicates that the bit is an error; if they are consistent, it indicates that the bit is not an error. Simultaneously, the number of errors is recorded during the test.
[0062] Step S400: In response to the number of bit errors being greater than or equal to a predetermined threshold, the target sampling point is determined as a failure point, the data transmission test on the target sampling point is stopped, and the next sampling point to be processed is determined in the sampling point sequence.
[0063] In this embodiment, during the real-time recording of bit errors, if the number of bit errors is greater than or equal to a predetermined threshold, the target sampling point is identified as a failure point, and data transmission testing of the target sampling point is stopped. Simultaneously, the next sampling point to be processed is determined from the sampling point sequence, and testing is performed on the next sampling point until all data in the sampling point sequence has been tested. In response to the completion of data transmission testing and the number of bit errors being less than the predetermined threshold, the target sampling point is identified as a valid point.
[0064] Wherein, the predetermined threshold is greater than or equal to 1.
[0065] In some embodiments, when only the stable operating boundary of the parallel interface under test in the reference voltage and timing parameter space needs to be tested, the predetermined threshold can be set to a small value, such as 1 or 2. When it is necessary to analyze the eyelid thickness data, the bit error rate threshold can be set according to the requirements. For example, when the predetermined threshold is set to 1, the automatic test equipment will immediately proceed to the next sampling point for testing as soon as a bit error is detected, which can greatly improve the testing efficiency. In the prior art, it is necessary to send all the test data streams and then calculate the bit error rate to determine whether the sampling point is valid. In some scenarios, the number of bit errors may reach 16,000.
[0066] This invention, through its embodiments, determines the sampling point sequence corresponding to the parallel interface under test, identifies the target sampling point to be processed within this sequence, and performs data transmission testing on the parallel interface based on the target timing parameters and target reference voltage corresponding to the target sampling point. The number of bit errors during the data transmission test is recorded. When the number of bit errors reaches a predetermined threshold, the target sampling point is designated as a failure point, data transmission testing on that target sampling point is stopped, and the next sampling point is tested. Therefore, by setting a predetermined threshold, the testing time for a single sampling point can be reduced and the testing efficiency of the parallel interface can be improved by directly testing the next sampling point when the number of bit errors reaches the predetermined threshold.
[0067] In some embodiments, the method further includes: Step S500: Generate the first test image based on the test results of each sampling point.
[0068] The first test graph is the working boundary graph.
[0069] Specifically, Figure 5 This is a flowchart illustrating the generation of the first test image according to an embodiment of the present invention. Figure 1 As shown, generating the first test image based on the test results of each sampling point includes the following steps: Step S510: Establish a first coordinate system based on the timing parameter range and the reference voltage range.
[0070] In this embodiment, the first coordinate system is a Cartesian coordinate system, and the two coordinate axes of the first coordinate system are the timing parameters and the reference voltage, respectively.
[0071] For example, the X-axis (horizontal axis) of the first coordinate system represents timing parameters, and the Y-axis (vertical axis) of the first coordinate system represents the reference voltage. Alternatively, the X-axis (horizontal axis) of the first coordinate system represents the reference voltage, and the Y-axis (vertical axis) of the first coordinate system represents timing parameters.
[0072] Step S520: Determine the corresponding display method based on the test results of each sampling point.
[0073] In this embodiment, the test results include valid points and invalid points, which are displayed in different ways. The display method can be one or more combinations of pattern fill, color fill, etc. For example, invalid points are displayed in red, while valid points are displayed in green.
[0074] Step S530: Draw display patterns at the corresponding positions of each sampling point in the first coordinate system according to the display method to obtain the first test image.
[0075] In this embodiment, according to the display method obtained above, corresponding display patterns are drawn at the corresponding positions of each sampling point in the first coordinate system to obtain the first test image.
[0076] Figure 6 This is a schematic diagram of the first test diagram according to an embodiment of the present invention. Figure 6 As shown, the X-axis of the first coordinate system represents the timing parameter T, and the Y-axis represents the reference voltage V. The figure shows the test results of each sampling point, where the darker colors represent failure points and the lighter colors represent valid points.
[0077] Analysis of the first side view reveals that the first test diagram can be divided into two regions: a valid region composed of valid points and an invalid region composed of invalid points. The boundary between the valid and invalid regions represents the operating limits of the parallel interface under test under current operating conditions. Furthermore, the performance of the interface can be determined based on the first test diagram. For example, a more rounded and wider valid region indicates that the parallel interface under test is less sensitive to changes in reference voltage and timing parameters, and has a larger design margin. Another example is that analyzing the offset of the center point of the valid region from the rated operating conditions (VREF, CLK) may reveal design or manufacturing deviations of the parallel interface under test. Yet another example is that analyzing the symmetry of the boundaries can reveal specific design weaknesses of the parallel interface under test.
[0078] In some embodiments, if it is necessary to analyze "eyelid thickness", a predetermined threshold can be set according to actual needs. The predetermined threshold is greater than 1, for example, it can be set to 100, 255, etc.
[0079] That is, in response to the predetermined threshold being greater than 1, the method further includes: Step S600: Generate a second test chart based on the test results of each sampling point.
[0080] The second test image is an eye diagram.
[0081] Specifically, Figure 7This is a flowchart illustrating the generation of the second test pattern according to an embodiment of the present invention. Figure 7 As shown, generating the second test image based on the test results of each sampling point includes: Step S610: Obtain the number of bit errors corresponding to each sampling point.
[0082] In this embodiment, after testing all sampling points through the above steps S100-S400, the number of bit errors corresponding to each sampling point can be obtained.
[0083] Step S620: Determine the corresponding display method based on the number of bit errors. Different display methods correspond to different numbers of bit errors.
[0084] In this embodiment, the display method is determined according to the number of bit errors, and different display methods correspond to different numbers of bit errors. For example, assuming the predetermined threshold is 255, there are 256 possible number of bit errors from 0 to 255, and a color can be set for each value.
[0085] Step S630: Draw a display pattern at the corresponding position in the second coordinate system according to the display method to obtain the second test image.
[0086] In this embodiment, after determining the display method corresponding to each sampling point, a display pattern is drawn at the corresponding position in the second coordinate system according to the display method to obtain the second test image. The second coordinate system is a Cartesian coordinate system, and its two axes are timing parameters and a reference voltage, respectively. For example, the X-axis (horizontal axis) of the second coordinate system represents the timing parameters, and the Y-axis (vertical axis) represents the reference voltage. Alternatively, the X-axis (horizontal axis) of the second coordinate system represents the reference voltage, and the Y-axis (vertical axis) represents the timing parameters.
[0087] Figure 8 This is a schematic diagram of the opening in an embodiment of the present invention. For example... Figure 8 As shown, EH is the eye height, used to reflect the size of the vertical aperture. EH1, EH2, and EH3 are the aperture heights corresponding to different bit error rates (BER), for example: EH1 is The opening height; EH2 is The opening height; EH3 is The opening height.
[0088] Correspondingly, EW is the eye width, used to reflect the size of the horizontal aperture. EW1, EW2, and EW3 are the aperture heights corresponding to different bit error rates, for example: EW1 is The width of the opening; EW2 is The width of the opening; EW3 is The width of the opening.
[0089] Specifically, assuming the second test plot described above is an N-column × M-row plot, for the i-th column (i=1, 2, ..., N), starting from the lowest row (the first row) of that column, calculate the bit error rate for each row. For the j-th row, its corresponding cumulative bit error rate is:
[0090] in, Let j be the number of bit errors in the j-th row. Let K be the bit error rate of the j-th row, and K be the total amount of data transmitted.
[0091] Therefore, the bit error rate (BER) of each row in this column can be obtained. After obtaining the BER of each row, starting from the lowest row, find the first row with a BER less than or equal to the preset BER as the minimum row, and starting from the highest row, find the first row with a BER less than or equal to the preset BER as the maximum row. This gives the maximum and minimum rows in a column. After calculating the maximum and minimum rows for all columns, select the column with the largest difference between the maximum and minimum rows as the corresponding opening height. By adjusting the BER, EH1, EH2, and EH3 can be obtained.
[0092] Based on a similar principle, processing each row yields EW1, EW2, and EW3 as described above.
[0093] In some embodiments, the intersection point CP of EH1 and EW1 can also be determined. Ideally, the intersection point CP should be the center point of the "glasses". By analyzing the deviation of the intersection point CP from the center point, the performance of the parallel interface under test can be determined.
[0094] In some embodiments, the opening profile EOP can also be determined. Specifically, after obtaining EH and EW at the same bit error rate, the vertices of EH and EW are connected sequentially to form a closed region, which is the opening profile. Figure 8 The opening profile formed by EH2 and EW2 is shown.
[0095] Figure 9 This is a schematic diagram of eyelid thickness according to an embodiment of the present invention. Figure 9 As shown, the number in each cell represents the corresponding number of bit errors. (This is based on the above...) Figure 8 After obtaining the opening contours at different bit error rates using the method shown, if it is necessary to analyze the eyelid thickness at a certain bit error rate, find the corresponding opening contour and determine the eyelid thickness based on the opening contour.
[0096] Eyelid thickness refers to the width of the blur band at the edges of the left and right sides (in the direction of timing parameters) or the top and bottom sides (in the direction of reference voltage) of the eye diagram, which can quantify the instability of the signal in time and voltage.
[0097] by Figure 9 Taking this as an example, after obtaining the opening contour EOP, the corresponding eyelid thickness is determined from the four vertices of the opening contour. Specifically, for each vertex, the first cell with a value equal to a predetermined threshold is found in its corresponding direction, and the distance between the vertex cell and the first cell with a value equal to the predetermined threshold is the eyelid thickness.
[0098] Specifically, the upper vertex of the opening profile is searched upwards, the lower vertex is searched downwards, the left vertex is searched to the left, and the right vertex is searched to the right.
[0099] If the eyelids are thicker in the horizontal direction (left and right sides), it may indicate a timing jitter problem; if the eyelids are thicker in the vertical direction (up and down), it may indicate voltage noise.
[0100] Figure 10 This is a schematic diagram of the second test diagram according to an embodiment of the present invention. Figure 10 As shown, the second test diagram is an eye diagram at a certain bit error rate.
[0101] The black area in the center of the eye diagram is the glasses area A1, which is the area with better signal.
[0102] The area outside the glasses area A1 is the eyelid area, which corresponds to the rising edge, falling edge and the fluctuation range of the signal during the comment holding phase. The thickness of the eyelid reflects the steepness of the signal edge and the amplitude of the jitter.
[0103] Q1 is the outline of the opening, and P1 is the center point of the glasses area.
[0104] R stands for void, which is an abnormal point appearing inside the eyeglass area.
[0105] The Q2 box is an optimized outline that excludes holes.
[0106] This invention, through its embodiments, determines the sampling point sequence corresponding to the parallel interface under test, identifies the target sampling point to be processed within this sequence, and performs data transmission testing on the parallel interface based on the target timing parameters and target reference voltage corresponding to the target sampling point. The number of bit errors during the data transmission test is recorded. When the number of bit errors reaches a predetermined threshold, the target sampling point is designated as a failure point, data transmission testing on that target sampling point is stopped, and the next sampling point is tested. Therefore, by setting a predetermined threshold, the testing time for a single sampling point can be reduced and the testing efficiency of the parallel interface can be improved by directly testing the next sampling point when the number of bit errors reaches the predetermined threshold.
[0107] Figure 11 This is a schematic diagram of a test apparatus for a parallel interface according to an embodiment of the present invention. Figure 11 As shown, the testing apparatus for a parallel interface according to an embodiment of the present invention includes a sequence determination unit 111, a target sampling point determination unit 112, a transmission test unit 113, and a failure point determination unit 114. The sequence determination unit 111 determines a sampling point sequence corresponding to the parallel interface under test. The sampling point sequence includes multiple sampling points, each being a combination of timing parameters and a reference voltage of the parallel interface under test. The target sampling point determination unit 112 determines the target sampling point that needs to be processed from the sampling point sequence. The transmission test unit 113 performs a data transmission test on the parallel interface under test based on the target timing parameters and target reference voltage corresponding to the target sampling point, and records the number of bit errors during the data transmission test. The failure point determination unit 114, in response to the number of bit errors being greater than or equal to a predetermined threshold, determines the target sampling point as a failure point, stops the data transmission test on the target sampling point, and determines the next sampling point to be processed from the sampling point sequence.
[0108] This invention, through its embodiments, determines the sampling point sequence corresponding to the parallel interface under test, identifies the target sampling point to be processed within this sequence, and performs data transmission testing on the parallel interface based on the target timing parameters and target reference voltage corresponding to the target sampling point. The number of bit errors during the data transmission test is recorded. When the number of bit errors reaches a predetermined threshold, the target sampling point is designated as a failure point, data transmission testing on that target sampling point is stopped, and the next sampling point is tested. Therefore, by setting a predetermined threshold, the testing time for a single sampling point can be reduced and the testing efficiency of the parallel interface can be improved by directly testing the next sampling point when the number of bit errors reaches the predetermined threshold.
[0109] Figure 12 This is a schematic diagram of an electronic device according to an embodiment of the present invention. In this embodiment, the electronic device 12 includes a server, a terminal, etc. Figure 12As shown, the electronic device 12 includes at least one processor 121; a memory 122 communicatively connected to at least one processor 121; and a communication component 123 communicatively connected to a scanning device, wherein the communication component 123 receives and transmits data under the control of the processor 121; wherein the memory 122 stores instructions executable by at least one processor 121, which are executed by at least one processor 121 to implement the above-described test method.
[0110] Specifically, the electronic device includes: one or more processors 121 and a memory 122. Figure 12 Taking a processor 121 as an example, the processor 121 and the memory 122 can be connected via a bus or other means. Figure 12 Taking a bus connection as an example, memory 122, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. Processor 121 executes various functional applications and data processing of the device by running the non-volatile software programs, instructions, and modules stored in memory 122, thereby implementing the above-mentioned test method.
[0111] The memory 122 may include a program storage area and a data storage area, wherein the program storage area may store the operating system and applications required for at least one function; the data storage area may store an option list, etc. Furthermore, the memory 122 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 122 may optionally include memory remotely located relative to the processor 121, and these remote memories may be connected to external devices via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.
[0112] One or more modules are stored in memory 122 and, when executed by one or more processors 121, perform the test methods in any of the above method embodiments.
[0113] The above-mentioned products can perform the methods provided in the embodiments of this application, and have the corresponding functional modules and beneficial effects of performing the methods. For technical details not described in detail in this embodiment, please refer to the methods provided in the embodiments of this application.
[0114] This invention, through its embodiments, determines the sampling point sequence corresponding to the parallel interface under test, identifies the target sampling point to be processed within this sequence, and performs data transmission testing on the parallel interface based on the target timing parameters and target reference voltage corresponding to the target sampling point. The number of bit errors during the data transmission test is recorded. When the number of bit errors reaches a predetermined threshold, the target sampling point is designated as a failure point, data transmission testing on that target sampling point is stopped, and the next sampling point is tested. Therefore, by setting a predetermined threshold, the testing time for a single sampling point can be reduced and the testing efficiency of the parallel interface can be improved by directly testing the next sampling point when the number of bit errors reaches the predetermined threshold.
[0115] Another embodiment of the present invention relates to a non-volatile storage medium for storing a computer-readable program for use by a computer to execute some or all of the above-described method embodiments.
[0116] That is, those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing related hardware. This program is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.
[0117] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A testing method for a parallel interface, characterized in that, The method includes: Determine the sampling point sequence corresponding to the parallel interface to be tested. The sampling point sequence includes multiple sampling points, and the sampling points are a combination of timing parameters and reference voltage of the parallel interface to be tested. Determine the target sampling point that needs to be processed in the sampling point sequence; Based on the target timing parameters and target reference voltage corresponding to the target sampling point, a data transmission test is performed on the parallel interface under test, and the number of bit errors during the data transmission test is recorded. In response to the number of bit errors being greater than or equal to a predetermined threshold, the target sampling point is identified as a failure point, the data transmission test on the target sampling point is stopped, and the next sampling point to be processed is determined in the sampling point sequence.
2. The method according to claim 1, characterized in that, The method further includes: In response to the completion of the data transmission test and the number of bit errors being less than a predetermined threshold, the target sampling point is determined as a valid point.
3. The method according to claim 1, characterized in that, The process of determining the sampling point sequence corresponding to the parallel interface to be tested includes: Obtain the timing parameter range, reference voltage range, first step value, and second step value corresponding to the parallel interface under test. The first step value is the step value corresponding to the timing parameter, and the second step value is the step value corresponding to the reference voltage. The sampling point sequence corresponding to the parallel interface under test is determined based on the timing parameter range, the reference voltage range, the first step value, and the second step value.
4. The method according to claim 1, characterized in that, The step of performing data transmission tests on the parallel interface under test based on the target timing parameters and target reference voltage corresponding to the target sampling point, and recording the number of bit errors during the data transmission test, includes: The operating parameters of the parallel interface are adjusted to the target timing parameters and target reference voltage corresponding to the target sampling point; Send a test data stream to the parallel interface under test and obtain the read-back data stream after processing by the parallel interface under test; The number of errors is determined based on the test data stream and the readback data stream.
5. The method according to claim 3, characterized in that, The method further includes: The first test chart is generated based on the test results of each sampling point.
6. The method according to claim 5, characterized in that, The step of generating the first test image based on the test results of each sampling point includes: A first coordinate system is established based on the timing parameter range and the reference voltage range, wherein the two coordinate axes of the first coordinate system are the timing parameters and the reference voltage, respectively. The display method is determined based on the test results of each sampling point, and the display methods for failure points and valid points are different. According to the display method, a display pattern is drawn at the corresponding position of each sampling point in the first coordinate system to obtain the first test image.
7. The method according to claim 1, characterized in that, The predetermined threshold is greater than or equal to 1.
8. The method according to claim 1, characterized in that, In response to the predetermined threshold being greater than 1, the method further includes: A second test chart is generated based on the test results of each sampling point.
9. The method according to claim 8, characterized in that, The step of generating the second test map based on the test results of each sampling point includes: Obtain the number of bit errors corresponding to each sampling point; The display method is determined based on the number of bit errors, and different display methods correspond to different numbers of bit errors. The display pattern is drawn at the corresponding position in the second coordinate system according to the display method to obtain the second test image.
10. A test system for a parallel interface, characterized in that, The system includes: The test carrier board is used to provide a runtime environment for the parallel interface to be tested. An automated testing apparatus includes a memory and a processor, the memory being used to store one or more computer program instructions, wherein the one or more computer program instructions are executed by the processor to implement the method as described in any one of claims 1-9.
11. A testing device for a parallel interface, characterized in that, The device includes: A sequence determination unit is used to determine the sampling point sequence corresponding to the parallel interface under test. The sampling point sequence includes multiple sampling points, which are combinations of timing parameters and reference voltages of the parallel interface under test. A target sampling point determination unit is used to determine the target sampling point that needs to be processed in the sampling point sequence. The transmission test unit is used to perform data transmission tests on the parallel interface under test based on the target timing parameters and target reference voltage corresponding to the target sampling point, and record the number of bit errors during the data transmission test. The failure point determination unit is used to determine the target sampling point as a failure point in response to the number of bit errors being greater than or equal to a predetermined threshold, stop the data transmission test of the target sampling point, and determine the next sampling point to be processed in the sampling point sequence.
12. An electronic device comprising a memory and a processor, characterized in that, The memory is used to store one or more computer program instructions, wherein the one or more computer program instructions are executed by the processor to implement the method as described in any one of claims 1-9.
13. A computer-readable storage medium storing computer program instructions thereon, characterized in that, The computer program instructions, when executed by a processor, implement the method as described in any one of claims 1-9.
14. A computer program product comprising a computer program, characterized in that, When the computer program is run on a computer, the computer performs the method according to any one of claims 1-9.