Pipelined performance analysis method and system based on quantized delay and resource constraints

Abstract

This invention proposes a pipeline performance analysis method and system based on quantized latency and resource constraints. The method includes: acquiring pre-configured pipeline structure information, wherein the pipeline structure information includes the number of pipeline nodes, node dependencies, resource vectors and processing latency corresponding to each pipeline node, total resources, and task arrival rate or interval; initializing the pipeline structure information into a data structure that can be processed internally by the system; acquiring tasks according to the task arrival rate or interval, and performing task simulation using the data structure according to processing rules to obtain simulation results; analyzing the simulation results to obtain corresponding pipeline performance analysis results; and shortening the development cycle and improving the performance of the final product by quickly identifying performance bottlenecks and performing targeted optimizations in the early stages of design.

Description

Technical Field

[0001] This invention relates to the field of electronic design automation technology, and in particular to a pipeline performance analysis method based on quantized delay and resource constraints, a computer-readable storage medium, a computer device, and a pipeline performance analysis system based on quantized delay and resource constraints. Background Technology

[0002] In related technologies, especially in the co-development of hardware and software based on Field-Programmable Gate Arrays (FPGAs), and particularly when developing high-performance storage controllers (such as RAID cards) and network acceleration cards, system I / O performance (such as operations per second, OPS) is a core metric. Developers typically employ hardware and software pipelined designs to improve concurrent processing capabilities. However, the complex pipeline structure introduces a series of design challenges: Performance bottlenecks are difficult to pinpoint intuitively: a complete I / O operation (such as a read / write request) requires dozens or even hundreds of hardware and software processing stages (nodes). Each node has different processing latency and shares hardware resources (such as computing units, buffers, memory bandwidth, and parallelism of each stage). Traditional methods rely on developers' experience to make theoretical estimations or to locate bottlenecks through on-board testing later, which is inefficient and blind.

[0003] Lack of early quantitative evaluation methods: Before RTL code development is completed and synthesis and routing are performed, there is a lack of effective tools to conduct early and rapid simulation evaluations of the theoretical performance limits of the pipeline design. This leads to long design iteration cycles, unclear optimization directions, and often results in performance failures being discovered only in the later stages, requiring rework.

[0004] Limitations of existing tools: Existing performance analysis tools, such as software-side performance profilers or hardware simulation waveform observations, have significant shortcomings: Software Profiler: It can only analyze the execution time of the software part and cannot accurately simulate the parallelism, blocking, resource contention and other behaviors of the hardware pipeline.

[0005] Hardware simulation: While accurate, it is extremely slow, complex to set up simulation environments, and difficult to use in the early conceptual stages of design (when only architecture and estimated latency data are available).

[0006] Theoretical calculations: Manual calculations are too simplistic and cannot handle complex situations such as dynamic task arrivals, resource contention, and pipeline blockages, resulting in large errors.

[0007] Therefore, there is an urgent need for a tool that can quickly and automatically simulate pipeline behavior, quantify performance indicators, and accurately locate bottlenecks in the early stages of design, based on architectural parameters and estimated data, to guide developers in targeted optimization. Summary of the Invention

[0008] This invention aims to at least partially solve one of the technical problems in the aforementioned technologies. To this end, one objective of this invention is to propose a pipeline performance analysis method based on quantized latency and resource constraints. By automating pipeline performance simulation, bottleneck analysis, and visualization guidance, this method enables early, rapid, and automated discovery of performance bottlenecks, thereby shortening the development cycle and improving the performance of the final product.

[0009] A second objective of this invention is to provide a computer-readable storage medium.

[0010] The third objective of this invention is to provide a computer device.

[0011] The fourth objective of this invention is to propose a pipeline performance analysis system based on quantized latency and resource constraints.

[0012] To achieve the above objectives, a first aspect of the present invention proposes a pipeline performance analysis method based on quantized latency and resource constraints, comprising the following steps: acquiring pre-configured pipeline structure information, wherein the pipeline structure information includes the number of pipeline nodes, node dependencies, resource vectors and processing latency corresponding to each pipeline node, total resources, and task arrival rate or interval; initializing the pipeline structure information into a data structure that can be processed internally by the system; acquiring tasks according to the task arrival rate or interval, and performing task simulation using the data structure according to processing rules to obtain simulation results; and analyzing the simulation results to obtain corresponding pipeline performance analysis results.

[0013] The pipeline performance analysis method based on quantized latency and resource constraints according to embodiments of the present invention enables early, rapid, and automated discovery of performance bottlenecks by performing automated simulation, bottleneck analysis, and visualization guidance on pipeline performance, thereby shortening the development cycle and improving the performance of the final product.

[0014] In addition, the pipeline performance analysis method based on quantized delay and resource constraints proposed in the above embodiments of the present invention may also have the following additional technical features: Optionally, the processing rules include: after a task enters a pipeline node, it needs to consume all the processing latency corresponding to that node before it can be allowed to attempt to enter the next pipeline node; during the entire processing latency of a task executing in a pipeline node, the task continuously occupies the corresponding resource vector, and when the task leaves the pipeline node, all occupied resources are immediately released; the pipeline node can only be started to execute a task if the current system idle resources are greater than or equal to the resource vector corresponding to the pipeline node; if the current system idle resources are less than the resource vector corresponding to the pipeline node, it needs to wait until resources are sufficient; when insufficient resources cause subsequent tasks to wait, the system records the duration for which this type of resource becomes the current bottleneck, and simultaneously calculates and monitors the throughput.

[0015] Optionally, the data structure is used to perform task simulation according to processing rules to obtain simulation results, including the following steps: S301, determine whether the total number of tasks has reached the upper limit based on the preset first threshold. If yes, end the task simulation; otherwise, execute S302. S302, determine whether the rate of change of throughput within the most recent second threshold is less than the third threshold. If yes, end the task simulation; otherwise, execute S303. S303, Get the current time t; S304, check if the current task queue is empty. If it is, execute S306; otherwise, execute S305. S305, Start a task from the task queue and add it to the pipeline node processing queue; S306, process pipeline nodes one by one until all pipeline nodes have been processed; S307, update time t=t+1; S308, check if the task completion queue is empty. If it is, return to execute S301; otherwise, execute S309. S309 records task completion information, calculates throughput, and returns to execute S301.

[0016] Optionally, pipeline nodes are processed one by one until all pipeline nodes have been processed, including the following steps: S3061, determine if there are still pipeline nodes that have not been processed. If yes, execute S3062; otherwise, execute S307. S3062, randomly select an unprocessed pipeline node for processing; S3063, determine whether the selected unprocessed pipeline node is idle. If yes, execute S3066; otherwise, execute S3064. S3064, determine whether the start time of the previous task in the current pipeline node plus the processing delay is less than or equal to the current time t. If yes, execute S3065; otherwise, execute S3061. S3065, Update task status, release occupied resources and put them into the next node task queue or completion queue; S3066, determine whether the current pipeline node has an empty task queue or insufficient resources. If yes, execute S3061; otherwise, execute S3067. S3067, retrieve the next task from the current pipeline node task queue and update the node status, then return to execute S3061.

[0017] To achieve the above objectives, a second aspect of the present invention provides a computer-readable storage medium storing a pipeline performance analysis program based on quantization latency and resource constraints, which, when executed by a processor, implements the pipeline performance analysis method based on quantization latency and resource constraints as described above.

[0018] To achieve the above objectives, a third aspect of the present invention provides a computer device including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the pipeline performance analysis method based on quantized latency and resource constraints as described above.

[0019] To achieve the above objectives, a fourth aspect of the present invention proposes a pipeline performance analysis system based on quantized latency and resource constraints, comprising: an acquisition module for acquiring pre-configured pipeline structure information, wherein the pipeline structure information includes the number of pipeline nodes, node dependencies, resource vectors and processing latency corresponding to each pipeline node, total resources, and the rate or interval of task arrival; a configuration initialization module for initializing the pipeline structure information into a data structure that can be processed internally by the system; a simulation engine module for acquiring tasks according to the rate or interval of task arrival, and simulating tasks using the data structure according to processing rules to obtain simulation results; and a result analysis and visualization module for analyzing the simulation results to obtain corresponding pipeline performance analysis results. Attached Figure Description

[0020] Figure 1 This is a flowchart illustrating the pipeline performance analysis method based on quantized latency and resource constraints according to an embodiment of the present invention. Figure 2 This is a schematic diagram of an assembly line structure according to an embodiment of the present invention; Figure 3This is a schematic diagram of a task simulation according to an embodiment of the present invention; Figure 4 This is a block diagram of a pipeline performance analysis system based on quantized delay and resource constraints according to an embodiment of the present invention. Figure 5 A block diagram of a simulation engine according to an embodiment of the present invention; Figure 6 This is a schematic diagram illustrating the performance results of a simulated pipeline according to a specific embodiment of the present invention. Detailed Implementation

[0021] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0022] To better understand the above technical solutions, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the invention to those skilled in the art.

[0023] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0024] Figure 1 This is a flowchart illustrating a pipeline performance analysis method based on quantized latency and resource constraints according to an embodiment of the present invention. Figure 1 As shown, the pipeline performance analysis method based on quantization latency and resource constraints in this embodiment of the invention includes the following steps: S101, obtain pre-configured pipeline structure information, wherein the pipeline structure information includes the number of pipeline nodes, node dependencies, resource vector and processing latency corresponding to each pipeline node, total resources, and the rate or interval at which tasks arrive.

[0025] It should be noted that the pre-configured pipeline structure information can be user-input design parameters, including: Pipeline topology (such as the number of nodes and dependencies) defines the sequence of nodes (N1, N2, ..., Nk) that must be traversed to complete a specific task (such as an I / O request), and clarifies the dependencies.

[0026] Node quantization parameters: Configured for each node Ni: (1) Processing delay Di: The unit time required for the task to remain at this node.

[0027] (2) Resource occupancy vector Ri: The type and quantity of various resources (such as BRAM, DSP, processing engine instance, buffer slot, bandwidth channel, stage parallel unit, etc.) occupied by the task during execution.

[0028] System resource pool: Defines the total amount of various resources in the system.

[0029] Task injection model: Defines the rate or interval at which tasks arrive (such as constant rate, Poisson distribution, etc.) to simulate load.

[0030] Specifically, such as Figure 2 As shown, each task flows into the pipeline from the starting point 101 and begins processing. After passing through several pipeline nodes 102, it ends at the last pipeline node after completion. Each pipeline node has dependencies; in this diagram, pipeline node B depends on pipeline node A, and pipeline node C depends on pipeline node B. This application supports any one-to-many or many-to-one dependency relationship. Each pipeline node 102 may have a certain degree of parallelism. Each pipeline node requires a corresponding resource of 104 to process a task, and there is a corresponding delay from the start of processing to completion. Only after step 103 can the next pipeline stage be reached. The resources of the entire system 105 may be occupied by various pipeline nodes at different times. When the system resources are insufficient, pipeline nodes that do not occupy enough resources will cause a pause, thereby affecting the throughput performance of the entire pipeline.

[0031] S102 initializes the pipeline structure information into a data structure that can be processed internally by the system.

[0032] In other words, the above parameters are mapped to internal system data structures, such as: using linked lists or arrays to store the order and dependencies of pipeline nodes; using hash tables or dictionaries to record the latency and resource consumption of each node; using counters or queues to manage the allocation status of system resources; and using event queues to store the arrival and processing time of tasks.

[0033] S103: Obtain tasks based on the arrival rate or interval of the tasks, and use data structures to simulate the tasks according to the processing rules to obtain simulation results.

[0034] As an example, the processing rules include: after a task enters a pipeline node, it must consume all the processing latency corresponding to that node before it is allowed to attempt to enter the next pipeline node; during the entire processing latency of a task executing in a pipeline node, it continuously occupies the corresponding resource vector, and when the task leaves the pipeline node, all occupied resources are immediately released; a pipeline node can only be started to execute a task if the current system idle resources are greater than or equal to the resource vector corresponding to the pipeline node; if the current system idle resources are less than the resource vector corresponding to the pipeline node, it is necessary to wait until sufficient resources are available; when insufficient resources cause subsequent tasks to wait, the system records the duration for which this type of resource becomes the current bottleneck, and simultaneously calculates and monitors the throughput.

[0035] In other words, the simulation engine progresses in minimum time steps, maintaining a global event queue. For each arriving task, it "flows" strictly according to the sequence of its pipeline nodes, as follows: a. Sequential Flow and Delay Consumption: After a task enters node Ni, it must consume the node's preset delay Xi before it can be allowed to attempt to enter the next node Ni+1. During this period, the task is considered to occupy the node.

[0036] b. Resource Occupation and Release: During the entire delay Xi of the execution at node Ni, the task continuously occupies its declared resource vector Ri. When the task leaves node Ni, it immediately releases all occupied resources.

[0037] c. Execution under resource constraints: A task can only start execution on a node Ni if the following conditions are met: The current system has more or less available resources than the node's required resources Ri.

[0038] If the conditions are not met, the task, after completing at node Ni-1, must wait (Pending) at the entry point of node Ni until sufficient resources are available. This simulates a pipeline stall caused by resource contention.

[0039] d. Dynamic bottleneck identification and convergence determination: Bottleneck logging: Whenever a certain type of resource is fully occupied, causing subsequent tasks to wait, the system records the duration for which that type of resource becomes the "current bottleneck".

[0040] Performance monitoring: The system calculates the global OPS (number of tasks completed / total simulation time) in real time.

[0041] Intelligent convergence: The system continuously monitors the OPS value. After the simulation has run for a period of time, if the OPS volatility is detected to be less than a preset threshold (e.g., 0.1%) over several adjacent statistical periods (e.g., every 1000 time units), the system is considered to have reached a stable state and the simulation is automatically terminated. This avoids meaningless long-term simulations and improves efficiency.

[0042] As an example, such as Figure 3 As shown, a data structure is used to simulate the task according to the processing rules to obtain the simulation results, including the following steps: S301, determine whether the total number of tasks has reached the upper limit based on the preset first threshold. If yes, end the task simulation; otherwise, execute S302. S302, determine whether the rate of change of throughput within the most recent second threshold is less than the third threshold. If yes, end the task simulation; otherwise, execute S303. S303, Get the current time t; S304, check if the current task queue is empty. If it is, execute S306; otherwise, execute S305. S305, Start a task from the task queue and add it to the pipeline node processing queue; S306, process pipeline nodes one by one until all pipeline nodes have been processed; S307, update time t=t+1; S308, check if the task completion queue is empty. If it is, return to execute S301; otherwise, execute S309. S309 records task completion information, calculates throughput, and returns to execute S301.

[0043] As a specific example, such as Figure 3 As shown, pipeline nodes are processed one by one until all pipeline nodes are processed, including the following steps: S3061, determine if there are still pipeline nodes that have not been processed. If yes, execute S3062; otherwise, execute S307. S3062, randomly select an unprocessed pipeline node for processing; S3063, determine whether the selected unprocessed pipeline node is idle. If yes, execute S3066; otherwise, execute S3064. S3064, determine whether the start time of the previous task in the current pipeline node plus the processing delay is less than or equal to the current time t. If yes, execute S3065; otherwise, execute S3061. S3065, Update task status, release occupied resources and put them into the next node task queue or completion queue; S3066, determine whether the current pipeline node has an empty task queue or insufficient resources. If yes, execute S3061; otherwise, execute S3067. S3067, retrieve the next task from the current pipeline node task queue and update the node status, then return to execute S3061.

[0044] In other words, the simulation module algorithm first determines whether the current exit condition is met, namely, the total number of tasks has reached the upper limit or the OPS change rate of the last 100 times is <0.1%. If the exit condition is met, the pipeline simulation is exited. If the exit condition is not met, the current time t is obtained, and then it is determined whether the current task queue is empty. If it is not empty, a task is started; otherwise, pipeline nodes are processed one by one. When processing pipeline nodes one by one, it first determines whether there are any unprocessed nodes. If there are unprocessed nodes, one is randomly selected from the unprocessed nodes for processing. If there are no unprocessed nodes, it jumps to 307. After selecting a node, check if the selected node is idle. If the node had a task being processed at the previous time step, check if the delay of the previous task has been reached. If not, the current node still needs to process the previous task and jumps back to 3061. Otherwise, update the status of this task and add it to the task queue of the next node. If the current node is the last node in the pipeline stage, add it to the completion queue. If the current node is idle or the previous task has been completed, check if its task queue is empty. If it is not empty and resources are sufficient, take out the next task for processing and update the node status. Otherwise, jump to 3061. If all nodes have been processed once, the current time step ends. Update the time step t = t + 1 and check if the task completion queue is empty. If it is empty, jump directly to 301 to check the exit condition. If it is not empty, record the task completion information, update the task completion count, calculate OPS, and then jump to 301 to check the exit condition.

[0045] S104. Analyze the simulation results to obtain the corresponding pipeline performance analysis results.

[0046] In other words, after the simulation is complete, the system automatically generates a multi-dimensional analysis report: (1) Visualized pipeline simulation diagram: showing the flow and blockage of tasks in the pipeline.

[0047] (2) Steady-state performance report: Provides key indicators such as average OPS and average task delay after convergence.

[0048] (3) Bottleneck Analysis Report: Quantify the percentage of time that various resources become bottlenecks in the total simulation time, and directly and in order point out the resource bottlenecks that have the greatest impact on overall performance.

[0049] (4) Optimization suggestions: Based on the bottleneck report, optimization directions can be derived (such as increasing the number of certain types of computing units, expanding the buffer depth, optimizing the algorithm to reduce the latency of a certain node, etc.).

[0050] As a specific example, such as Figure 6 As shown, assuming a three-node pipeline, node 1 processes a task every 50ns, requiring resource R1; node 2 processes a task every 70ns, requiring resource R2; and node 3 processes a task every 90ns, requiring resources R1 and R3. The current task dependency relationship is A->B->C. The total number of system resources is one each for R1, R2, and R3. The task queue generation mode is high-pressure mode, and tasks can be retrieved from the task queue at any time (i.e., latency is 0). The above information constitutes input 501 in this example. After simulation in this application, the result analysis and visualization module will output a resource usage report 502 and a stage resource capacity bottleneck report 503. Since both pipeline nodes A and C will compete for resource R1, the report shows that resource R1 is the bottleneck and outputs the pipeline result diagram and performance results of this simulation 504.

[0051] In summary, the pipeline performance analysis method based on quantized latency and resource constraints according to embodiments of the present invention does not require complete RTL code and software code. Performance prediction can be performed during the architecture design phase. By decomposing and simulating or measuring the time of each pipeline stage, latency data can be obtained without waiting for the entire system to be fully implemented to test its overall performance, thus achieving "left-shift" testing. Compared with gate-level simulation, abstract-level simulation is extremely fast, capable of simulating millions of tasks within minutes. Through resource constraints and dynamic blocking rules, it can realistically simulate hardware behavior and accurately quantify the impact of different resource bottlenecks, rather than relying on guesswork. The output bottleneck time percentage provides developers with clear, data-driven optimization priorities, allowing for targeted optimization of specific pipeline parts to overcome performance bottlenecks and ensure that the product meets performance requirements. The built-in convergence determination mechanism automatically completes the simulation and outputs core conclusions, reducing the analytical burden on users.

[0052] In addition, this embodiment of the invention also proposes a computer-readable storage medium storing a pipeline performance analysis program based on quantization latency and resource constraints. When the pipeline performance analysis program based on quantization latency and resource constraints is executed by a processor, it implements the pipeline performance analysis method based on quantization latency and resource constraints as described above.

[0053] In addition, this invention also proposes a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the pipeline performance analysis method based on quantized latency and resource constraints as described above.

[0054] Figure 4 This is a block diagram of a pipeline performance analysis system based on quantized latency and resource constraints according to an embodiment of the present invention. Figure 4 As shown, the pipeline performance analysis system based on quantized latency and resource constraints in this embodiment includes: an acquisition module 10, a configuration initialization module 20, a simulation engine module 30, and a result analysis and visualization module 40.

[0055] The acquisition module 10 is used to acquire pre-configured pipeline structure information, which includes the number of pipeline nodes, node dependencies, resource vectors and processing delays corresponding to each pipeline node, total resources, and the rate or interval of task arrival. The configuration initialization module 20 is used to initialize the pipeline structure information into a data structure that can be processed internally by the system. The simulation engine module 30 is used to acquire tasks according to the rate or interval of task arrival and to simulate tasks according to processing rules using the data structure to obtain simulation results. The result analysis and visualization module 40 is used to analyze the simulation results to obtain the corresponding pipeline performance analysis results.

[0056] It should be noted that, as Figure 5 As shown, the simulation engine module 30 is further composed of four sub-modules: a configuration loader 301, a task queue generator 302, a simulation module 303, and a data output module 304. The configuration loader receives information from the configuration initialization module 20 after initialization, updates the pipeline structure and node dependencies, and starts a simulation. The configuration loader 301 configures the resources and latency data occupied by the pipeline nodes into the current simulation module 303 for use in subsequent simulation processes. The task queue generator 302 continuously simulates task generation times and places them into the simulation processing queue according to a preset algorithm, based on one of the following: a sudden large number of tasks, a Poisson distribution, or a uniform distribution. Subsequently, the simulation module 303 works, using the pipeline structure preset by the configuration loader 301 to continuously retrieve tasks from the queue of the task queue generator 302, according to... Figure 3 The algorithm shown drives its built-in clock to perform simulation, while calculating its throughput per unit time (OPS) and transmitting the simulation results to the data output module 304. The simulation terminates when the simulation results converge to the required level or exceed the upper limit of the number of simulation tasks. After the simulation terminates, the data output module 304 outputs the performance results, bottleneck ratio, and complete simulation footprint information to the system database based on the information in the database.

[0057] It should be noted that the foregoing explanation of the embodiment of the pipeline performance analysis method based on quantized delay and resource constraints also applies to the pipeline performance analysis system based on quantized delay and resource constraints in this embodiment, and will not be repeated here.

[0058] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0059] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0060] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0061] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0062] It should be noted that any reference signs placed between parentheses in the claims should not be construed as limiting the claims. The word "comprising" does not exclude the presence of components or steps not listed in the claims. The word "a" or "an" preceding a component does not exclude the presence of a plurality of such components. The invention can be implemented by means of hardware comprising several different components and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

[0063] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0064] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

[0065] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0066] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0067] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0068] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms should not be construed as necessarily referring to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0069] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A pipeline performance analysis method based on quantized latency and resource constraints, characterized in that, Includes the following steps: Obtain pre-configured pipeline structure information, wherein the pipeline structure information includes the number of pipeline nodes, node dependencies, resource vector and processing latency corresponding to each pipeline node, total resources, and the rate or interval at which tasks arrive; The pipeline structure information is initialized into a data structure that can be processed internally by the system. Tasks are acquired based on their arrival rate or interval, and the data structure is used to simulate the tasks according to the processing rules to obtain simulation results. The simulation results are analyzed to obtain the corresponding pipeline performance analysis results.

2. The pipeline performance analysis method based on quantization delay and resource constraints as described in claim 1, characterized in that, The processing rules include: Once a task enters a pipeline node, it must consume all the processing delay corresponding to that node before it can be allowed to attempt to enter the next pipeline node. During the entire processing delay of a task executing at a pipeline node, the corresponding resource vector is continuously occupied. When the task leaves the pipeline node, all occupied resources are immediately released. The pipeline node can only be started to execute a task if the current system idle resources are greater than or equal to the resource vector corresponding to the pipeline node. If the current system idle resources are less than the resource vector corresponding to the pipeline node, it is necessary to wait until sufficient resources are available. When resource shortages cause subsequent tasks to wait, the system records the duration for which that type of resource becomes the current bottleneck, and simultaneously calculates and monitors the throughput.

3. The pipeline performance analysis method based on quantization delay and resource constraints as described in claim 2, characterized in that, The data structure is used to simulate the task according to the processing rules to obtain the simulation results, including the following steps: S301, determine whether the total number of tasks has reached the upper limit based on the preset first threshold. If yes, end the task simulation; otherwise, execute S302. S302, determine whether the rate of change of throughput within the most recent second threshold is less than the third threshold. If yes, end the task simulation; otherwise, execute S303. S303, Get the current time t; S304, check if the current task queue is empty. If it is, execute S306; otherwise, execute S305. S305, Start a task from the task queue and add it to the pipeline node processing queue; S306, process pipeline nodes one by one until all pipeline nodes have been processed; S307, update time t=t+1; S308, check if the task completion queue is empty. If it is, return to execute S301; otherwise, execute S309. S309 records task completion information, calculates throughput, and returns to execute S301.

4. The pipeline performance analysis method based on quantization delay and resource constraints as described in claim 3, characterized in that, Process each pipeline node one by one until all pipeline nodes have been processed, including the following steps: S3061, determine if there are still pipeline nodes that have not been processed. If yes, execute S3062; otherwise, execute S307. S3062, randomly select an unprocessed pipeline node for processing; S3063, determine whether the selected unprocessed pipeline node is idle. If yes, execute S3066; otherwise, execute S3064. S3064, determine whether the start time of the previous task in the current pipeline node plus the processing delay is less than or equal to the current time t. If yes, execute S3065; otherwise, execute S3061. S3065, Update task status, release occupied resources and put them into the next node task queue or completion queue; S3066, determine whether the current pipeline node has an empty task queue or insufficient resources. If yes, execute S3061; otherwise, execute S3067. S3067, retrieve the next task from the current pipeline node task queue and update the node status, then return to execute S3061.

5. A computer-readable storage medium, characterized in that, It stores a pipeline performance analysis program based on quantized latency and resource constraints, which, when executed by the processor, implements the pipeline performance analysis method based on quantized latency and resource constraints as described in any one of claims 1-4.

6. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the pipeline performance analysis method based on quantized latency and resource constraints as described in any one of 1-4.

7. A pipeline performance analysis system based on quantized delay and resource constraints, characterized in that, include: The acquisition module is used to acquire pre-configured pipeline structure information, wherein the pipeline structure information includes the number of pipeline nodes, node dependencies, resource vector and processing latency corresponding to each pipeline node, total resources, and the rate or interval at which tasks arrive. A configuration initialization module is used to initialize the pipeline structure information into a data structure that can be processed internally by the system; The simulation engine module is used to acquire tasks based on the arrival rate or interval of the tasks, and to perform task simulation according to the processing rules using the data structure to obtain simulation results. The results analysis and visualization module is used to analyze the simulation results to obtain the corresponding pipeline performance analysis results.

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