A method and system for handling atomic operations in a cache
By transferring bus operands to the auxiliary storage area for processing, the problem of bus storage area saturation is solved, and the throughput and processing efficiency of atomic operations are improved.
CN122086800APending Publication Date: 2026-05-26T-HEAD (SHANGHAI) SEMICON CO LTD
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Patent Information
- Authority / Receiving Office
- CN Β· China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- T-HEAD (SHANGHAI) SEMICON CO LTD
- Filing Date
- 2026-01-08
- Publication Date
- 2026-05-26
AI Technical Summary
Technical Problem
In multi-core processor systems, atomic operation requests can easily saturate bus memory resources under high concurrency and high miss rate scenarios, leading to a decrease in atomic operation processing efficiency.
Method used
After detecting that it is impossible to read the stored operand from the last-level cache, the bus operand is transferred to the auxiliary storage area to wait, thereby releasing the storage resources of the bus storage area and avoiding bus storage area saturation due to memory access latency.
Benefits of technology
Without increasing the bus memory width, it improves throughput and processing efficiency in high-concurrency atomic operation scenarios.
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Figure CN122086800A_ABST
Abstract
This invention discloses a method and system for processing atomic operations in a cache. The method involves, upon receiving an atomic operation request containing a target address and bus operands, temporarily storing the bus operands in the bus storage area. It then searches for the stored operands in the last-level cache based on the target address. If not found, it requests to read them from memory and transfers the bus operands from the bus storage area to an auxiliary storage area. After receiving the stored operands from memory, it reads the bus operands from the auxiliary storage area. Finally, it performs an atomic operation on the bus operands and the stored operands to obtain the operation result. This method, upon detecting that the stored operands cannot be read from the last-level cache, transfers the bus operands to the auxiliary storage area to wait, thereby releasing the storage resources of the bus storage area and preventing storage resource saturation due to memory access latency. This improves the throughput and processing efficiency of atomic operations in high-concurrency scenarios.
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