Methods to save power and their display driver circuits

Abstract

The present invention discloses a method for a display driving circuit and the display driving circuit thereof. The method includes the following steps: receiving display data through a display interface; detecting whether the display driving circuit has entered a non-operating state, in which the display driving circuit stops refreshing a display screen; and in response to detecting that the display driving circuit has entered the non-operating state, setting an internal circuit of the display driving circuit to a power supply state to save power consumption of the internal circuit.

Description

Technical Field

[0001] This invention relates to a method for a display driving circuit, and more particularly to a power consumption reduction scheme for a display driving circuit. Background Technology

[0002] While advanced semiconductor processes offer advantages in terms of dynamic power consumption, they often come with the disadvantage of higher component leakage current. To reduce overall power consumption, display devices typically switch to low frame rate modes depending on the application scenario. However, when reducing the frame rate to lower dynamic power consumption, static power consumption caused by leakage current becomes the main factor in the overall power consumption of the display system. Summary of the Invention

[0003] Therefore, the main objective of this invention is to provide a method for display driving circuits that can reduce overall power consumption in low frame rate mode by detecting the operation behavior of high-speed interfaces.

[0004] An embodiment of the present invention discloses a method for a display driving circuit. The method includes the following steps: receiving display data through a display interface; detecting whether the display driving circuit has entered a non-active state, in which the display driving circuit stops refreshing a display screen; and in response to detecting that the display driving circuit has entered the non-active state, setting an internal circuit of the display driving circuit to a power supply state to save power consumption of the internal circuit.

[0005] Another embodiment of the present invention discloses a display driving circuit, which includes a receiver, a detector, and a power control circuit. The receiver is used to receive display data through a display interface. The detector is used to detect whether the display driving circuit enters a non-operating state, in which the display driving circuit stops refreshing a display screen. The power control circuit is coupled to the detector and, in response to detecting that the display driving circuit has entered the non-operating state, sets an internal circuit of the display driving circuit to a power supply state to save power consumption of the internal circuit. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of the display system according to Embodiment 1 of the present invention.

[0007] Figure 2 This is a flowchart of the power control process according to Embodiment 1 of the present invention.

[0008] Figure 3 The present invention illustrates a detector that detects the display state by detecting the operating mode of a display interface conforming to an embedded display port.

[0009] Figure 4The present invention illustrates a detector that detects display status by detecting the operating mode of another display interface that conforms to the mobile industry processor interface.

[0010] Figure 5 An embodiment of the present invention illustrates a detector that detects the display status by counting according to a frame rate switching command.

[0011] Figure 6 The diagram shows the display driver circuit receiving a preset signal from the host computer indicating the display status.

[0012] Figure 7 This demonstrates how a detector uses a counter to preemptively change the level of the power control signal before the display driver circuit enters its operational state.

[0013] Figures 8 to 11 The image shows the detector using another counter to monitor the display status for a period of time.

[0014] Figure 12A and Figure 12B This is a schematic diagram illustrating the operation of an internal circuit controlled by a power control circuit according to an embodiment of the present invention.

[0015] Figure 13A and Figure 13B An embodiment of the power control circuit of the present invention is shown.

[0016] Figure 14A and Figure 14B This is a schematic diagram illustrating the operation of an internal circuit controlled by a power control circuit according to an embodiment of the present invention.

[0017] Figure 15A and Figure 15B An embodiment of the power control circuit of the present invention is shown.

[0018] Figure 16 An embodiment of the present invention is shown. Figure 14A Another implementation of the power control circuit shown.

[0019] Figure 17 An embodiment of the present invention is shown. Figure 14A Another implementation of the power control circuit shown.

[0020] The reference numerals in the attached figures are explained as follows: Detailed Implementation

[0021] Figure 1This is a schematic diagram of a display system 10 according to an embodiment of the present invention. The display system 10 includes a host 102 and a display driving circuit 104. The host 102 can serve as a video source to generate and provide image data to be displayed. Examples of the host 102 include a central processing unit (CPU) and an application processor (AP), but are not limited thereto. The display driving circuit 104 can be capable of driving a display screen (omitted for simplicity). Figure 1 The display is a circuit device for displaying information. In one or more embodiments, the display driver circuit 104 may be implemented in a chip and is a display driver integrated circuit (DDIC).

[0022] like Figure 1 As shown, the display driver circuit 104 can receive power from external power supply devices PS1 and PS2 to operate. Specifically, power supply device PS1 outputs a supply voltage VDD to the display driver circuit 104, while power supply device PS2 outputs another supply voltage VDDLC to the display driver circuit 104. Each power supply device PS1 and PS2 can be implemented using a power management integrated circuit (PMIC), but is not limited to this.

[0023] The display driver circuit 104 includes a receiver 112, a detector 114, a voltage generator 116, power control circuits PC1 and PC2, and internal circuits IC1 to IC4. The internal circuits IC1 to IC4 may be or include various circuit blocks or modules, such as image processing circuits, compensation circuits, and display driver channels, but are not limited thereto. These internal circuits IC1 to IC4 can operate by receiving their respective supply voltages. In this example, internal circuits IC1 and IC2 receive a supply voltage VDDLA from the power control circuit PC1, internal circuit IC3 receives a supply voltage VDDLB from the power control circuit PC2, and internal circuit IC4 receives a supply voltage VDDLC from an external power supply device PS2.

[0024] Power control circuits PC1 and PC2 can be used to control the power supply to their respective internal circuits. In this example, power control circuit PC1 can output a supply voltage VDDLA to set the power supply state of internal circuits IC1 and IC2, and power control circuit PC2 can output a supply voltage VDDLB to set the power supply state of internal circuit IC3. Voltage generator 116 is coupled between power supply device PS1 and power control circuit PC2 to convert the supply voltage VDD into a desired output voltage to be supplied to power control circuit PC2 and internal circuit IC3 (e.g., as supply voltage VDDLB). Power control circuit PC1 can convert the supply voltage VDD into supply voltage VDDLA. In some embodiments, power control circuit PC1 may include a similar voltage generator capable of generating and outputting supply voltage VDDLA. Examples of voltage generator 116 include, but are not limited to, low-dropout regulators (LDO regulators) and switching regulators.

[0025] To transmit display data, the host 102 and the display driver circuit 104 can be interconnected via a display interface 120 conforming to an interface standard (such as Mobile Industry Processor Interface (MIPI), DisplayPort (DP), embedded DisplayPort (eDP), or Serial Peripheral Interface (SPI)). Therefore, the receiver 112 may be, or include, a receiving circuit capable of receiving display data via the display interface 120 based on that interface standard. The detector 114 can detect the receiving behavior of the receiver 112 and / or monitor the operating state of the display interface 120, thereby determining the display's operating mode. Alternatively or additionally, the receiver 112 may receive an indication signal from the host 102 via the display interface 120 or another interface, indicating an operating mode, which will be discussed in more detail in the following paragraphs.

[0026] In embodiments of the present invention, the display system 10 is allowed to dynamically control the display frame rate. For example, when the display screen needs to display video, the display driving circuit 104 can refresh the display screen at a higher frame rate; while when the display screen displays a static image, the display driving circuit 104 can refresh the display screen at a lower frame rate to reduce power consumption. However, as described above, although power consumption can be reduced by lowering the frame rate and reducing data transmission of the display interface 120, there is still unavoidable static power consumption in the internal circuits IC1 to IC4. To solve this problem, based on the detection of the display operation mode, the detector 114 can provide power control signals S1 to S3 to the power control circuits PC1 and PC2 and the power supply device PS2 to adjust the power supply state of the internal circuits IC1 to IC4, thereby reducing the static power consumption of the internal circuits IC1 to IC4.

[0027] It is worth noting that, Figure 1 The illustrated structure is used to explain various possible scenarios for power control of internal circuits. For example, a power control circuit can be configured to control only one internal circuit (such as power control circuit PC2), or to control two or more internal circuits (such as power control circuit PC1). Furthermore, a power control circuit can transmit internal power supplied by a voltage generator to an internal circuit (such as power control circuit PC2), or it can directly convert external power to supply power to an internal circuit (such as power control circuit PC1). Moreover, an internal circuit can receive power from the internal power control circuit of the display driver circuit (such as internal circuits IC1-IC3), or it can receive power from an external power supply device (such as internal circuit IC4).

[0028] Another point to note is... Figure 1 The structure shown is merely one exemplary embodiment of the display driving circuit 104. In various embodiments of the present invention, the display driving circuit may be designed to have any number of internal circuits that receive power supply control in various suitable ways. In this case, there may be any number of power control circuits for controlling the internal circuits, and the display driving circuit may receive power supply from any number of external power supply devices.

[0029] For example, in Figure 1In one embodiment, the display driving circuit 104 includes four internal circuits IC1 to IC4 and two power control circuits PC1 to PC2, and these circuits may coexist in the display driving circuit. In another embodiment, a display driving circuit may include only one or some of the internal circuits IC1 to IC4. For example, in one embodiment, the display driving circuit includes only internal circuit IC4 and its corresponding power supply device PS2, omitting other internal circuits and power supply circuits. In another embodiment, the display driving circuit includes only internal circuit IC1 and its corresponding power control circuit PC1 and power supply device PS1, omitting other internal circuits and power supply circuits. In fact, the internal circuits and power control circuits can be configured in any suitable manner, and their related implementations are not intended to limit the scope of the invention.

[0030] In addition, Figure 1 In the display driver circuit 104, power control circuits PC1 and PC2, as well as power supply device PS2, each receive a power control signal S1 to S3. In another embodiment, multiple power control circuits and / or power supply devices can receive the same power control signal to provide power supply settings. This is because the power control signal is generated based on the display state of the display driver circuit 104 and / or the display interface 120, and different power control signals in the same display driver circuit typically have the same switching behavior.

[0031] Figure 2 This is a flowchart of power control process 20 according to an embodiment of the present invention. Power control process 20 can be implemented in a display driver circuit, such as... Figure 1 The display driver circuit 104 is shown. (As shown...) Figure 2 As shown, the power control process 20 includes the following steps: Step 202: Receive display data through display interface 120.

[0032] Step 204: Detect whether the display driving circuit 104 has entered a non-operating state, in which the display driving circuit 104 stops refreshing a display screen.

[0033] Step 206: In response to the detection that the display driver circuit 104 has entered a non-operational state, set any one of the internal circuits IC1 to IC4 to a power supply state to save power consumption of the internal circuits IC1 to IC4.

[0034] According to power control flow 20, receiver 112 can receive display data from host 102 via display interface 120 (step 202). Based on dynamic frame rate control, each frame period for receiving display data can be divided into an active period and a non-active period. Display data is only transmitted through display interface 120 during the active period. Host 102 can dynamically allocate the active and non-active periods within a frame period, and the non-active period has a variable length to achieve the desired frame rate. During the active period, display driver circuit 104 can operate in the active state to refresh the display screen by receiving display data; during the non-active period, display driver circuit 104 can operate in the non-active state to stop refreshing the display screen, and at this time, receiving display data through display interface 120 can also be stopped.

[0035] In another embodiment, the operational and non-operational periods can be configured using a long-V approach. In this way, the length of the non-operational period can be adjusted to dynamically control the frame rate by extending the vertical front / back porch or blanking period.

[0036] Regardless of the configuration during operation and non-operation, the detector 114 can detect whether the display driver circuit 104 has entered a non-operational state (step 204) and output power control signals S1 to S3 accordingly. Based on the corresponding power control signals, the power control circuits PC1, PC2, and / or the power supply device PS2 can set the power supply state of the internal circuits IC1 to IC4. For example, if the display driver circuit 104 is in an operating state, the internal circuits IC1 to IC4 can be set to a normal power supply state; if the display driver circuit 104 enters a non-operational state, the internal circuits IC1 to IC4 can be set to a low power supply state. To save power consumption, when the display driver circuit 104 enters a non-operational state, the power control circuits PC1, PC2, and / or the power supply device PS2 can dynamically reduce the supply voltage or even shut off the power supply to the corresponding internal circuits IC1 to IC4.

[0037] The detector 114 can determine the power supply status of the internal circuits IC1 to IC4 by detecting the operating mode of the display interface 120, and the detection can be performed in any suitable manner. For example, in one embodiment, the detector 114 can detect whether the display interface 120 has switched from a normal operating mode to a sleep mode or a low-power mode, thereby determining whether to adjust the power supply status of the internal circuits IC1 to IC4.

[0038] Figure 3 This embodiment of the invention illustrates how a detector 114 detects the display state by detecting the operating mode of a display interface 120. In this embodiment, a display interface 120 conforming to an embedded display port is used as an example. Figure 3 As shown, the display interface 120 includes a main link and an auxiliary link. Furthermore, Figure 3 The waveforms of the display status and power control signal SX (which can be any of S1 to S3) of the display driving circuit 104 are also shown.

[0039] according to Figure 3 The behavior shown initially involves both the main and auxiliary channels of the display interface 120 being in normal operating mode, causing the display driver circuit 104 to be operational, with display data being transmitted normally from the host 102 to the display driver circuit 104. Subsequently, when the host 102 transmits a sleep indication packet ML_PHY_SLEEP via the main channel to indicate that the display interface 120 will enter sleep mode, the display driver circuit 104 can correspondingly enter a non-operating state. In response to the receipt of the sleep indication packet ML_PHY_SLEEP, the receiver 112 of the display driver circuit 104 can enter sleep mode, and the main channel can also switch to sleep mode to save power. At this time, the power control signal SX output by the detector 114 is pulled low, thereby controlling the corresponding internal circuit to enter a low power supply state.

[0040] During the next frame, host 102 transmits a wake-up indication packet (AUX_PHY_WAKE) via the auxiliary channel to instruct display interface 120 to switch to normal mode, causing display driver circuit 104 to return to operation and transmit display data normally. Subsequently, the main channel returns to normal operation mode, and receiver 112 of display driver circuit 104 resumes normal operation. At this time, the power control signal SX output by detector 114 is pulled high, thereby controlling the corresponding internal circuits to enter normal power supply state.

[0041] In this example, the internal circuitry enters a low-power state when the power control signal is pulled low and a normal-power state when the power control signal is pulled high. Those skilled in the art will understand that this embodiment is merely exemplary, and the power supply state of the internal circuitry can be indicated by any logic level or state of the power control signal. In fact, the power control signal can be implemented in any suitable manner, such as digital signals, analog signals, and / or flags, and should not be limited to the scope described in this specification.

[0042] Figure 3The data transmission operations and related packets provided are for a display interface 120 that conforms to an embedded display port. In another embodiment, another interface standard also applies. For example, Figure 4 Another embodiment is shown, in which the display interface 120 conforms to the specifications of a mobile industry processor interface. For example... Figure 4 As shown, initially, the display interface 120 is in high-speed mode to transmit display data, causing the display driver circuit 104 to operate. Subsequently, the host 102 controls the display interface 120 to switch from high-speed mode to low-power mode, and the display driver circuit 104 correspondingly enters a non-operating state. At this time, the receiver 112 of the display driver circuit 104 can enter sleep mode, and the power control signal SX output by the detector 114 is pulled low, thereby controlling the corresponding internal circuit to enter a low-power state.

[0043] During the next frame, host 102 controls display interface 120 to return to high-speed mode, causing display driver circuit 104 to return to operation and transmit display data normally. Correspondingly, receiver 112 can resume normal operation, and the power control signal SX output by detector 114 is pulled high, thereby controlling the corresponding internal circuit to enter normal power supply state.

[0044] In another embodiment, the host 102 may provide a frame rate switching instruction to the display driver circuit 104, wherein the frame rate switching instruction may indicate the rules for frame rate changes.

[0045] Figure 5 This embodiment of the invention illustrates a detector 114 that detects display status by counting according to a frame rate switching instruction FR_CMD. This embodiment is applicable to display interfaces with any interface standard, such as mobile processor interfaces, embedded display ports, or serial peripheral interfaces, but is not limited thereto. Figure 5 As shown, the host 102 can transmit the frame rate switching instruction FR_CMD to the display driver circuit 104 through an interface. This interface can be the display interface 120 used by the host 102 to transmit display data to the display driver circuit 104, or any other transmission interface used by the host 102 to transmit the instructions required by the display driver circuit 104.

[0046] In one or more embodiments, the frame rate switching instruction FR_CMD may carry information indicating the frame rate transition rules for subsequent frame periods. For example, when the current frame rate is 120Hz, the frame rate switching instruction FR_CMD may indicate that the frame rate is about to change to 60Hz. Therefore, by receiving the frame rate switching instruction FR_CMD and using a counter, the display driver circuit 104 knows when to allocate the operating period and non-operating period for the first frame period after the frame rate change. In this example, the detector 114 may be configured to have a counter for counting the length of the operating period and / or the length of the non-operating period, which may be defined by the frame rate set by the frame rate switching instruction FR_CMD, so that the display driver circuit 104 can determine when to change the level of the power control signal SX. If the frame rate switching instruction FR_CMD is transmitted through a display interface, it may be transmitted within an appropriate blank period, and the transmission time of the instruction is not limited to this.

[0047] In other words, the counter can calculate the period during which the display driver circuit 104 remains in the operating state, thereby determining the start time of the non-operating state after the operating state ends. Alternatively or additionally, the counter can calculate the period during which the display driver circuit 104 remains in the non-operating state, thereby determining the end time of the current non-operating state. In this case, the detector 114 can detect whether the display driver circuit 104 has entered the non-operating state by the counting / calculation behavior of the counter, thereby changing the level of the power control signal SX to adjust the power supply state of the internal circuitry in the non-operating state.

[0048] In another embodiment, the display driving circuit 104 may directly receive a preset signal PCONF indicating the display status from the host 102. For example, such as Figure 6 As shown, the preset signal PCONF at a first logic level (such as logic "low") corresponds to the operating state, while the preset signal PCONF at a second logic level (such as logic "high") corresponds to the non-operating state. Therefore, the detector 114 can detect whether the preset signal PCONF changes from a "low" level to a "high" level to determine whether the display driver circuit 104 enters the non-operating state.

[0049] In an embodiment where a preset signal PCONF is transmitted via host 102 to indicate a non-operational state, the preset signal PCONF can be transmitted through any interface, such as a General Purpose Input / Output (GPIO) port. The GPIO port can be an interface independent of the display interface used to transmit display data; therefore, the display interface can be of any protocol.

[0050] In some embodiments, after the power supply to a specific internal circuit is turned off in a non-operating state, the internal circuit may not immediately operate normally to process display data when the power supply is restored at the end of the non-operating state. In other words, the internal circuit requires a startup time before it is ready to operate normally. In this case, the power supply should be restarted a predetermined time before the end of the non-operating state. Therefore, the power control signal SX should return to the level corresponding to the operating state a certain amount of time in advance, so that the internal circuit can return from a low power supply state to a normal power supply state before the display driver circuit enters the operating state.

[0051] Figure 7 This illustrates how the detector 114 changes the level of the power control signal SX before the display drive circuit 104 enters operation. For example... Figure 7 As shown, the power control signal SX provides a normal power supply for effective display data transmission and processing when it is at a logic "high" level, and a low power supply for non-operational periods when it is at a logic "low" level. In this example, the advance power control can be implemented using a counter, which starts calculating in response to the detector 114 detecting that the display driver circuit 104 has entered a non-operational state. The calculation period TS is less than the total period during which the display driver circuit 104 remains in the non-operational state. In response to the expiration of the counter, the power control signal SX can switch to a "high" level to instruct the power control circuit to control the corresponding internal circuit to exit the low power supply state. Therefore, the internal circuit can return to the normal power supply state and begin the initialization or power-on procedure to be ready for normal operation when the display driver circuit 104 begins its next operating state.

[0052] exist Figure 7 In the illustrated embodiment, the display driver circuit 104 is notified of the end time of the non-operating state (e.g., via a frame rate switching instruction FR_CMD), and thus can begin normal power supply before the end time of the non-operating state. In another embodiment, the display driver circuit 104 may not know when to switch from the non-operating state to the operating state. Therefore, a counter used for non-operating state detection can be set with an appropriate expiration time. When the counter expires, the power control circuit can wake up the internal circuitry, while the detector 114 continues to monitor the display state for a period of time to determine whether the display driver circuit 104 has returned to the operating state. If not, the power control circuit can again provide a low power supply state to control the internal circuitry.

[0053] The above operation can be implemented using another counter. For example, in Figure 8In another embodiment shown, while the display driving circuit 104 enters a non-operating state, the power control signal SX enters a "low" level to set the internal circuit to a low power supply state. At this time, a first counter begins to count a predetermined period TS. When the first counter expires, the power control signal SX switches to a "high" level to control the internal circuit to enter a normal power supply state. At this time, a second counter (or the same first counter) begins to count another period TM, and the detector 114 continuously monitors the display state to determine whether the display driving circuit 104 returns to the operating state. When the second counter expires (i.e., the counting period TM ends), if the detector 114 detects that the display driving circuit 104 is still in a non-operating state, the power control signal SX switches to a "low" level again, causing the power control circuit to stop providing normal power and setting the internal circuit to enter a low power supply state again.

[0054] Next, the display driver circuit 104 repeats a similar counter operation to calculate a period TS during which the low power supply state is maintained, and then calculates another period TM to detect whether the display state has resumed operation. When the detector 114 detects that the display driver circuit 104 has entered the operating state, the power control circuit will maintain the normal power supply state of the internal circuit, and the counter continues to calculate for subsequent operating states.

[0055] The lengths of TS and TM can be set to any appropriate value. Furthermore, the duration TM can be set according to the startup or power-on time required by the internal circuitry. Therefore, when the display driver circuit 104 switches from a non-operating state to an operating state, the internal circuitry is fully powered on and ready for normal operation.

[0056] It is worth noting that the operation of attempting to start the internal circuit using one or more counters after the predetermined period TS expires can be applied to scenarios indicating different display statuses. Figure 9 In another embodiment shown, the display driving circuit 104 can obtain this information by receiving a preset signal PCONF, which can be transmitted via a general purpose input / output port. It can also perform a similar counting operation using one or more counters in conjunction with the settings of TS and TM.

[0057] exist Figure 10 In another embodiment shown, the display driver circuit 104 can receive display data from the host 102 via a display interface 120 conforming to an embedded display port, and can also wake up the internal circuitry using a counting operation before the end of the non-operational state. Figure 10 As shown, when the main channel enters sleep mode in response to the sleep indication packet ML_PHY_SLEEP, a counter starts calculating a period TS, followed by another counter calculating a period TM. The detailed operation of the counters is similar to that in the above embodiment and will not be repeated here.

[0058] exist Figure 11 In another embodiment shown, the display driver circuit 104 can receive display data from the host 102 via a display interface 120 conforming to a mobile industry processor interface, and it can also wake up internal circuitry using a counting operation before the end of the non-operational state. For example... Figure 11 As shown, when the interface switches to low-power mode, a counter starts calculating a period TS, followed by another counter calculating a period TM. The detailed operation of the counters is similar to that in the above embodiment and will not be repeated here.

[0059] It is worth noting that the purpose of this invention is to provide a solution for reducing power consumption, which can reduce the static power consumption of the internal circuitry in the display driver circuit when the display driver circuit enters a non-operating state (where the display driver circuit stops receiving display data and refreshing the display screen). The above embodiments describe several detection methods for determining whether and when the display driver circuit enters a non-operating state and / or returns to an operating state. In addition, this invention further provides methods for controlling the power supply state of the internal circuitry to reduce power consumption.

[0060] The display driving circuit may include various types of internal circuits. Some internal circuits can be completely shut down when not processing display data; therefore, when the display driving circuit enters a non-operating state, the power supply to these internal circuits can be cut off. Other internal circuits cannot be completely shut down and need to operate in a low-power mode; therefore, when the display driving circuit enters a non-operating state, these internal circuits can receive a lower supply voltage and / or current to operate. As described above, the detector 114 can detect the display state of the display driving circuit 104 and output a power control signal SX to the power control circuit (or power supply device) based on whether the display driving circuit 104 is in a non-operating state. In one embodiment, the power control signal SX may be a 1-bit signal. When the display drive circuit 104 is in operation, the power control signal SX can be in a first state to control the power control circuit (or power supply device) to provide a normal supply voltage to the internal circuit; when the display drive circuit 104 enters a non-operational state, the power control signal SX can be in a second state to control the power control circuit (or power supply device) to provide another power supply state, wherein the power control circuit (or power supply device) can supply a lower supply voltage to the internal circuit, or even shut off the power supply to the internal circuit.

[0061] Figure 12AThis is a schematic diagram illustrating the operation of an internal circuit 1200 controlled by a power control circuit 1202 according to an embodiment of the present invention. The power control circuit 1202 can operate in a normal mode or a low-power mode based on a power control signal SX from a detector. The power control circuit 1202 receives a supply voltage VDD from a power supply and correspondingly supplies an internal supply voltage lower than the supply voltage VDD to the internal circuit 1200. In this example, when the display driving circuit is in operation, the power control signal SX is at a logic "high" level to control the power control circuit 1202 to operate in the normal mode, thereby setting the internal circuit 1200 to a normal power supply state. Conversely, when the display driving circuit is not in operation, the power control signal SX is at a logic "low" level to control the power control circuit 1202 to operate in the low-power mode, thereby setting the internal circuit 1200 to a low power supply state.

[0062] It is worth noting that the switching of the power control signal SX can be completely synchronized with the switching between the operating state and the non-operating state, as in some of the embodiments described above; or it may also exist as... Figure 12A The small delay or advance shown can be used, for example, to wake up internal circuitry earlier. As long as the power control signal SX has a voltage level (or digital value) corresponding to the operating state and another different voltage level (or different digital value) corresponding to the non-operating state, all related implementations should fall within the scope of this invention.

[0063] In this example, the power control circuit 1202 may include or control a variable resistor circuit disposed between the power supply used to provide the supply voltage VDD and the internal circuit 1200. When the detector detects that the display driver circuit has entered an operating state, the power control circuit 1202 can operate in a normal mode, wherein the power control signal SX controls the variable resistor circuit to generate a resistor R1, so that the power control circuit 1202 supplies an internal supply voltage VDD_INT1 to the internal circuit 1200. When the detector detects that the display driver circuit has entered a non-operating state, the power control circuit 1202 can operate in a low-power mode, wherein the power control signal SX controls the variable resistor circuit to generate a resistor R2 greater than the resistor R1, so that the power control circuit 1202 supplies an internal supply voltage VDD_INT2 lower than the internal supply voltage VDD_INT1 to the internal circuit 1200.

[0064] exist Figure 12B In another embodiment shown, the variable resistor circuit of the power control circuit 1202 may be disposed between another power supply used to provide the supply voltage VSS (which may be a negative voltage or a ground voltage) and the internal circuit 1200, and the power control circuit 1202 may be controlled by a power control signal SX via a similar method. Figure 12AThe control is achieved through a specific method. In normal mode, the power control signal SX controls the variable resistor circuit to generate a resistor R1, causing the power control circuit 1202 to supply an internal supply voltage VSS_INT1 to the internal circuit 1200. In low-power mode, the power control signal SX controls the variable resistor circuit to generate a resistor R2 larger than R1, causing the power control circuit 1202 to supply an internal supply voltage VSS_INT2, higher than the internal supply voltage VSS_INT1, to the internal circuit 1200. Figure 12A or Figure 12B In this way, the voltage V2 of the internal circuit 1200 in low power mode is controlled to be less than the voltage V1 of the internal circuit 1200 in normal mode, thereby reducing the power consumption of the internal circuit 1200.

[0065] Reducing power consumption can be achieved in any way. Figure 13A An embodiment of the power control circuit of the present invention is shown. A power control circuit 1302 includes a switch SW1 controlled by a power control signal SX. When the detector detects that the display driving circuit has entered an operating state, the power control circuit 1302 operates in normal mode. At this time, the power control signal SX turns on the switch SW1 to supply the supply voltage VDD as the internal supply voltage VDD_INT to an internal circuit 1300. When the detector detects that the display driving circuit has entered a non-operating state, the power control circuit 1302 operates in low-power mode. At this time, the power control signal SX turns off the switch SW1 to disconnect the power supply from the internal circuit 1300, that is, to cut off the path of the supply voltage VDD to the internal circuit 1300. Figure 13A As shown, when switch SW1 is turned off, the voltage level of the internal supply voltage VDD_INT will drop.

[0066] Figure 13B Another embodiment of the power control circuit of the present invention is shown. In this example, the power control circuit 1302 is disposed between the power supply for providing the supply voltage VSS and the internal circuit 1300, and includes a switch SW2. Controlled by the power control signal SX, the switch SW2 can be turned on when the power control circuit 1302 operates in normal mode and turned off when the power control circuit 1302 operates in low-power mode. Therefore, the path providing the supply voltage VSS is shut off in low-power mode. When the switch SW2 is turned off, the voltage level of the internal supply voltage VSS_INT rises. Therefore, when the display drive circuit is in a non-operating state, the static power consumption of the internal circuit 1300 is reduced.

[0067] In other embodiments, the power control circuitry can provide a lower voltage to the internal circuitry in a low-power mode, rather than shutting off the power supply. Figure 14AThis is a schematic diagram illustrating the operation of an internal circuit 1400 controlled by a power control circuit 1402 according to an embodiment of the present invention. Similarly, based on a power control signal SX from a detector, the power control circuit 1402 can operate in normal mode or low-power mode, and its control method is similar to that in the above embodiment, and will not be described again here.

[0068] In this example, the power control circuit 1402 can adjust the voltage across the internal circuit 1400 in different operating modes. When the detector detects that the display driver circuit has entered an operating state, the power control circuit 1402 can operate in a normal mode to supply a higher internal supply voltage VDD_INT1, thereby providing a larger voltage across the internal circuit 1400 V1. When the detector detects that the display driver circuit has entered a non-operating state, the power control circuit 1402 can operate in a low-power mode to supply a lower internal supply voltage VDD_INT2, thereby providing a smaller voltage across the internal circuit 1400 V2, where V2 is lower than V1.

[0069] Generally, the power consumption of an internal circuit is proportional to its voltage across the circuit. Therefore, a smaller voltage across the internal circuit 1400, V2, helps to reduce the power consumption of the internal circuit 1400.

[0070] exist Figure 14B In another embodiment shown, the power control circuit 1402 may be positioned between another power supply providing a supply voltage VSS (which may be a negative voltage or ground voltage) and the internal circuitry 1400. In this case, when operating in normal mode, the power control circuit 1402 may supply a lower internal supply voltage VSS_INT1, thereby providing a larger voltage across V1 to the internal circuitry 1400. When operating in low-power mode, the power control circuit 1402 may supply a higher internal supply voltage VSS_INT2, thereby providing a smaller voltage across V2 to the internal circuitry 1400.

[0071] Figure 15A The following is an embodiment of the power control circuit 1502 of the present invention, which is... Figure 14A The power control circuit 1402 shown is one embodiment. The power control circuit 1502 includes a switch SW3 and a voltage generator 1510. The switch SW3 is controlled by a power control signal SX. The voltage generator 1510 can generate an internal supply voltage VDD_INT based on a reference voltage VREF_VDD, and output the internal supply voltage VDD_INT to an internal circuit 1500.

[0072] When the power control circuit 1502 operates in normal mode, switch SW3 is turned on to supply the internal circuit 1500 with the supply voltage VDD as the internal supply voltage VDD_INT. In other words, the internal supply voltage VDD_INT is approximately equal to VDD. When the power control circuit 1502 operates in low-power mode, switch SW3 is turned off to disconnect the power supply from the internal circuit 1500, that is, to shut off the path providing the supply voltage VDD. At this time, voltage generator 1510 can output the internal supply voltage VDD_INT to the internal circuit 1500. The internal supply voltage VDD_INT provided by voltage generator 1510 can be set to be lower than VDD, thereby reducing the static power consumption of the internal circuit 1500 when the display drive circuit is not in operation.

[0073] Figure 15B An embodiment of the present invention is shown. Figure 14B Another embodiment of the power control circuit 1402 shown is described. In this example, a power control circuit 1502 is disposed between the power supply for providing the supply voltage VSS and the internal circuit 1500, and includes a switch SW4 and a voltage generator 1520. Controlled by the power control signal SX, the switch SW4 can be turned on when the power control circuit 1502 operates in normal mode and turned off when the power control circuit 1502 operates in low-power mode, i.e., the path providing the supply voltage VSS is turned off in low-power mode. In this case, the internal supply voltage VSS_INT is instead provided by the voltage generator 1520, and the level of the internal supply voltage VSS_INT can be higher than the supply voltage VSS (e.g., by appropriately setting the reference voltage VREF_VSS). This also reduces the voltage across the internal circuit 1500, thereby reducing the static power consumption of the internal circuit 1500 when the display driver circuit is not in operation.

[0074] The voltage generator 1510 or 1520 included in the power control circuit 1502 can be implemented using a low-dropout regulator, a switching regulator, or any regulator that can generate the desired output voltage, but is not limited thereto.

[0075] In one or more embodiments, the supply voltages VDD and / or VSS can be provided by an external power source, such as a power supply device, power management circuit, or power control circuit connected to the display driver circuit. In this case, under normal power supply conditions, the internal circuit 1500 can receive the supply voltages VDD or VSS from the external power source. Furthermore, under low power supply conditions, the internal circuit 1500 can receive the internal supply voltages VDD_INT or VSS_INT from voltage generators 1510 or 1520, where voltage generators 1510 and 1520 can be power control circuits included in the display driver circuit. In this way, depending on whether the display driver circuit is in an operating or non-operating state, the internal circuit 1500 can receive power from different power control circuits or power terminals, thereby reducing the power supply to the internal circuit 1500 when the display driver circuit enters a non-operating state.

[0076] In another embodiment, a voltage generator used to supply voltage to the internal circuitry can output different voltage levels to control the internal circuitry to operate in an appropriate manner. For example, Figure 16 An embodiment of the present invention is shown. Figure 14A Another embodiment of the power control circuit 1402 shown is presented. In this example, a power control circuit 1602 includes a voltage generator 1610. The voltage generator 1610 is disposed between a power supply for providing the supply voltage VDD and an internal circuit 1600. It receives a reference voltage VREF_VDD to generate an internal supply voltage VDD_INT, and then supplies the internal supply voltage VDD_INT to the internal circuit 1600. The voltage generator 1610 can adjust the level of the internal supply voltage VDD_INT by adjusting the level of the reference voltage VREF_VDD, controlled by a power control signal SX.

[0077] In detail, when the power control circuit 1602 operates in normal mode, the voltage generator 1610 can receive a higher reference voltage VREF_VDD or increase the level of the reference voltage VREF_VDD, thereby outputting an internal supply voltage VDD_INT with a higher level to the internal circuit 1600. When the power control circuit 1602 operates in low-power mode, the voltage generator 1610 can receive a lower reference voltage VREF_VDD or decrease the level of the reference voltage VREF_VDD, thereby outputting an internal supply voltage VDD_INT with a lower level to the internal circuit 1600. In low-power mode, the level of the internal supply voltage VDD_INT is lower than in normal mode, thereby reducing the static power consumption of the internal circuit 1600 when the display driver circuit is not in operation.

[0078] It is worth noting that the above embodiment provides a voltage generator 1610 disposed between the power supply used to provide the supply voltage VDD and the internal circuit 1600. In another embodiment, a voltage generator may also be disposed between the power supply used to provide the supply voltage VSS and the internal circuit to output different levels of the internal supply voltage VSS_INT in different operating modes. The related operation is similar to that in the above embodiment and will not be described in detail here.

[0079] Similarly, a voltage generator that can adjust the output voltage level for internal circuitry can be implemented using a low-dropout regulator, a switching regulator, or any regulator that can produce the desired output voltage, but is not limited to these.

[0080] Figure 17 The following is an embodiment of the power control circuit 1702 of the present invention, which is... Figure 14A Another embodiment of the power control circuit 1402 shown is presented. In this example, the power control circuit 1702 includes a switch SW5 and a diode circuit 1710. The switch SW5 is disposed between the power supply used to provide the supply voltage VDD and an internal circuit 1700, and is controlled by a power control signal SX. The diode circuit 1710 is configured to connect the power supply used to provide the supply voltage VDD and the internal circuit 1700 to form another power supply path, and may include several diodes connected in series. Figure 17 The diode circuit 1710 shown includes two diodes, but those skilled in the art will understand that a diode circuit may include any number of series diodes, and the number and arrangement of the diodes can determine the voltage drop, thereby determining the internal supply voltage VDD_INT level provided by the diode circuit 1710.

[0081] When the power control circuit 1702 operates in normal mode, switch SW5 is turned on to supply the supply voltage VDD as the internal supply voltage VDD_INT to the internal circuit 1700. In other words, the internal supply voltage VDD_INT is approximately equal to VDD. When the power control circuit 1702 operates in low-power mode, switch SW5 is turned off to disconnect the power supply from the internal circuit 1700, thereby shutting off the direct supply path of the supply voltage VDD. At this time, power can be supplied to the internal circuit 1700 through diode circuit 1710. Due to the voltage drop of the diode, the internal supply voltage VDD_INT received by the internal circuit 1700 will be lower than the supply voltage VDD, thereby reducing the static power consumption of the internal circuit 1700 when the display driver circuit is not in operation.

[0082] From another perspective, Figure 17The power control circuit 1702 can be implemented by providing a smaller resistance to supply power when the switch SW5 is on (corresponding to the normal power supply state), and a larger resistance to supply power when the switch SW5 is off (corresponding to the low power supply state). That is, the power supply path of the diode circuit 1710 has a larger resistance than the conducting switch path. The larger resistance will reduce the overall current consumption, thereby reducing the power consumption of the internal circuit 1700 when the display drive circuit is in a non-operating state.

[0083] In another embodiment, a diode circuit may be placed between the power supply used to provide the supply voltage VSS and the internal circuitry. The related implementation is similar to the embodiments described above and will not be repeated here.

[0084] In summary, this invention proposes a method to reduce power consumption, which can reduce the static power consumption of the internal circuitry in the display driver circuit when the display driver circuit enters a non-operating state (where the display driver circuit stops receiving display data and refreshing the display screen). The display driver circuit may include a detector for detecting the display state of the display driver circuit and / or the operating mode of the display interface. Based on the detection result, the power control circuit can be set to operate in a normal mode or a low-power mode to provide different power supply states to the corresponding internal circuitry. In one embodiment, when the internal circuitry is in a low-power state, a larger resistance value can be provided on the power supply path compared to the normal power supply state. Alternatively or additionally, the power control circuit can provide a lower internal circuitry voltage across the circuitry in the low-power mode compared to the normal mode. In this way, when the display driver circuit is in a non-operating state, the internal circuitry will have less static power consumption, thereby improving the power efficiency of the display system.

[0085] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for a display driving circuit, characterized in that, include: Receive display data through a display interface; Detect whether the display driver circuit has entered a non-operating state, in which the display driver circuit stops refreshing a display screen; as well as In response to the detection that the display driver circuit has entered the non-operational state, an internal circuit of the display driver circuit is set to a power-on state to save power consumption of the internal circuit.

2. The method as described in claim 1, characterized in that, The steps for detecting whether the display driver circuit has entered the non-operational state include: Detect whether the display interface has switched from a first operating mode to a second operating mode, wherein the display interface switches to the second operating mode in response to receiving an instruction packet indicating the second operating mode.

3. The method as described in claim 1, characterized in that, The steps for detecting whether the display driver circuit has entered the non-operational state include: Detect whether a counter has started counting, wherein the counter is used to calculate the period during which the display driver circuit remains in the non-operational state, which is determined according to a frame rate switching instruction.

4. The method as described in claim 1, characterized in that, The steps for detecting whether the display driver circuit has entered the non-operational state include: Detect whether a preset signal received by the display driver circuit changes from a first logic level to a second logic level; The preset signal at the first logic level corresponds to an operating state of the display driver circuit, and the preset signal at the second logic level corresponds to the non-operating state of the display driver circuit.

5. The method as described in claim 1, characterized in that, The steps for setting the internal circuit to this power supply state include: In response to the detection that the display driver circuit has entered the non-operating state, a power control signal having a second state is output to a power control circuit; and Based on the power control signal having the second state, a power supply state different from the one providing a first voltage is set, wherein the first voltage is provided by the power control circuit to the internal circuit based on the power control signal having the first state when the display driving circuit is in an operating state.

6. The method as described in claim 5, characterized in that, Setting the internal circuit to this power supply state disconnects a power supply from the internal circuit.

7. The method as described in claim 5, characterized in that, The internal circuit is configured to provide a second voltage that is lower than the first voltage in the power supply state.

8. The method as described in claim 5, characterized in that, Setting the internal circuit to this power supply state controls the internal circuit to receive a second voltage from another power control circuit.

9. The method as described in claim 1, characterized in that, Also includes: In response to the detection that the display driving circuit has entered the non-operating state, a first period is calculated, wherein the first period is shorter than the period during which the display driving circuit remains in the non-operating state; and In response to the expiration of the first period, the internal circuit is no longer set to the power supply state, and instead a first voltage is provided to the internal circuit.

10. The method as described in claim 9, characterized in that, Also includes: Calculate a second period that begins upon the expiration of the first period; as well as If the system detects that the display driver circuit remains in the non-operational state when the second period expires, it stops supplying the first voltage to the internal circuit and instead sets the internal circuit to the power supply state.

11. A display driving circuit, characterized in that, include: A receiver is used to receive display data through a display interface; A detector is used to detect whether the display driving circuit has entered a non-operating state, in which the display driving circuit stops refreshing a display screen; as well as A power control circuit, coupled to the detector, is used to respond to the detection that the display driver circuit has entered the non-operating state, and to set an internal circuit of the display driver circuit to a power supply state in order to save the power consumption of the internal circuit.

12. The display driving circuit as described in claim 11, characterized in that, The detector detects whether the display driving circuit has entered the non-operating state by detecting whether the display interface has switched from a first operating mode to a second operating mode, wherein the display interface switches to the second operating mode in response to receiving an instruction packet indicating the second operating mode.

13. The display driving circuit as described in claim 11, characterized in that, The detector detects whether the display driver circuit has entered the non-operational state by detecting whether a counter has started counting. The counter is used to calculate the period during which the display driver circuit remains in the non-operational state, which is determined according to a frame rate switching instruction.

14. The display driving circuit as described in claim 11, characterized in that, The detector detects whether the display driving circuit has entered the non-operation state by detecting whether a preset signal received by the display driving circuit changes from a first logic level to a second logic level. The preset signal at the first logic level corresponds to an operating state of the display driving circuit, and the preset signal at the second logic level corresponds to the non-operation state of the display driving circuit.

15. The display driving circuit as described in claim 11, characterized in that, In response to the detection that the display driving circuit has entered the non-operational state, the detector outputs a power control signal with a second state to the power control circuit, and the power control circuit sets a power supply state different from the supply of a first voltage according to the power control signal with the second state, wherein the first voltage is provided by the power control circuit to the internal circuit according to the power control signal with the first state when the display driving circuit is in an operating state.

16. The display driving circuit as described in claim 15, characterized in that, The power control circuit includes a variable resistor circuit disposed between a power supply and the internal circuit. The variable resistor circuit generates a first resistance in response to detecting that the display driver circuit has entered the operating state, and generates a second resistance greater than the first resistance in response to detecting that the display driver circuit has entered the non-operating state.

17. The display driving circuit as described in claim 15, characterized in that, The power control circuit uses a switch to disconnect a power supply from the internal circuit, thereby setting the internal circuit to the powered state.

18. The display driving circuit as described in claim 15, characterized in that, The power control circuit provides a second voltage lower than the first voltage to set the internal circuit to the power supply state.

19. The display driving circuit as described in claim 18, characterized in that, The power control circuit includes a switch and a voltage generator, which are disposed between a power supply and the internal circuit. In response to the detection that the display driving circuit has entered the non-operating state, the switch disconnects the power supply from the internal circuit, and the voltage generator outputs the second voltage to the internal circuit.

20. The display driving circuit as described in claim 18, characterized in that, The power control circuit includes a switch and a diode circuit, which are disposed between a power supply and the internal circuit. In response to the detection that the display driving circuit has entered the non-operating state, the switch disconnects the power supply and the internal circuit, and the diode circuit connects the power supply and the internal circuit.

21. The display driving circuit as described in claim 18, characterized in that, The power control circuit includes a voltage generator, wherein, in response to the detection that the display driver circuit has entered the non-operational state, the voltage generator outputs the second voltage to the internal circuit.

22. The display driving circuit as described in claim 15, characterized in that, The power control circuit controls the internal circuit to receive a second voltage from another power control circuit in order to set the internal circuit to the power supply state.

23. The display driving circuit as described in claim 11, characterized in that, Also includes: A first counter is used to calculate a first period in response to the detection that the display driving circuit has entered the non-operating state, wherein the first period is shorter than the period during which the display driving circuit remains in the non-operating state; In response to the expiration of the first counter, the power control circuit stops setting the internal circuit to the power supply state and instead provides a first voltage to the internal circuit.

24. The display driving circuit as described in claim 23, characterized in that, Also includes: A second counter is used to calculate a second period starting from the expiration of the first counter; In response to the detection that the display driver circuit remains in the non-operational state when the second counter expires, the power control circuit stops providing the first voltage to the internal circuit and instead sets the internal circuit to the power supply state.

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