A transistor-type active amplifier sensor device and its fabrication method

Abstract

This disclosure provides a transistor active amplification sensor device and its formation method. The transistor active amplification sensor device includes an optical sensing amplification circuit, which comprises a first complementary field-effect transistor (CFPT), a second complementary field-effect transistor (CFPT), and a sensing unit. The output terminal of the first CFPT is connected to the input terminal of the second CFPT. The first and second CFPTs are monolithically integrated three-dimensional structures. The optical sensing amplification circuit is used for forward signal amplification. The N-type semiconductor layer of the second CFPT and colloidal quantum dots form the sensing unit, which is used to sense the external environment and generate a potential input signal. This disclosure improves the integration density of the transistor active amplification sensor, reduces its size, achieves higher spatial resolution, enhances the sensor's response to weak signals, and improves the performance of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and more specifically, to a transistor-type active amplification sensor device and a method for forming the same. Background Technology

[0002] Over the past 50 years, the performance of integrated circuits (ICs) has improved rapidly, mainly due to the continuous reduction in the size and increase in the density of devices within ICs. However, with the increasing prominence of phenomena such as the short-channel effect, as well as limitations in the intrinsic properties of materials and processes, it has become increasingly difficult to further reduce the size of transistors in semiconductor structures, thus slowing down the pace of performance improvement in semiconductor structures.

[0003] Three-dimensional (3D) integration is one way to further improve integration density, achieved by stacking silicon wafers or dies and vertically interconnecting them using methods such as through-silicon vias (TSVs) or copper-copper connections. However, current mainstream 3D integration technologies, such as TSVs, are limited by the size of interconnects or TSVs, restricting the improvement of integration density and thus limiting further increases in semiconductor structure integration density. Furthermore, silicon-based chips cannot achieve monolithic 3D integration because single-crystal silicon lacks a bottom-up integration process and can only be integrated using bonding, further limiting the improvement of semiconductor structure integration density.

[0004] Therefore, how to improve the performance and integration of semiconductor structures so that they can be compatiblely fabricated on integrated circuits is a technical problem that urgently needs to be solved.

[0005] To achieve highly sensitive sensing (such as nucleic acid detection, ion detection, and photosensitive sensing), the front-end amplifier needs high integration in its structure. To achieve high spatial resolution, the front-end amplifier should have smaller pixels. Smaller pixels increase the number of detection units that can be accommodated on the chip, thereby improving spatial resolution. Simultaneously, the front-end amplifier should have a high amplification factor to enhance the sensor's response to weak signals. A higher amplification factor can amplify weak signals to a sufficient level for subsequent signal processing and analysis. Summary of the Invention

[0006] In view of the deficiencies in the prior art, the purpose of this disclosure is to provide a transistor-type active amplification sensor device and a method for forming the same.

[0007] To achieve the above objectives, according to one aspect of this disclosure, a transistor-type active amplification sensor device is provided, comprising: a photosensitive amplification circuit;

[0008] The optical sensing amplifier circuit includes a first complementary field-effect transistor, a second complementary field-effect transistor, and a sensing unit. The output terminal of the first complementary field-effect transistor is connected to the input terminal of the second complementary field-effect transistor. The first complementary field-effect transistor and the second complementary field-effect transistor are monolithic three-dimensional integrated structures. The optical sensing amplifier circuit is used for forward amplification of signals.

[0009] The sensing unit is formed by the N-type semiconductor layer of the second transistor of the first complementary field-effect transistor and colloidal quantum dots. The sensing unit is used to sense the external environment and generate a potential input signal.

[0010] Optionally, the semiconductor layer of the second transistor is made of one or more of ZnO, IZO, and IGZO, and the colloidal quantum dots are made of one or more of Ag2Te, InP, and AgS.

[0011] Optionally, the first complementary field-effect transistor includes a substrate, a first transistor, and a second transistor, wherein the first transistor is disposed above the substrate, and the second transistor is disposed above the first transistor;

[0012] The second complementary field-effect transistor includes a substrate, a first transistor, and a second transistor, wherein the first transistor is disposed above the substrate and the second transistor is disposed above the first transistor.

[0013] Optionally, the first transistor includes a first source, a first drain, a P-type semiconductor layer, and a first gate. The first source and the first drain are respectively disposed on opposite sides of the P-type semiconductor layer along a first direction. The first source and the first drain are respectively contacted and connected to the P-type semiconductor layer. The first gate is disposed above the P-type semiconductor layer along a second direction. The first direction is parallel to the top surface of the substrate, and the second direction is perpendicular to the top surface of the substrate.

[0014] The second transistor includes a second source, a second drain, an N-type semiconductor layer, and a second gate. The second source and the second drain are respectively disposed on opposite sides of the N-type semiconductor layer along the first direction. The second source and the second drain are respectively contacted and connected to the N-type semiconductor layer. The second gate is disposed below the N-type semiconductor layer along the second direction.

[0015] Optionally, the optical sensing amplifier circuit further includes a first interconnect structure, a second interconnect structure, and a third interconnect structure;

[0016] One end of the first interconnect structure is electrically connected to the first gate, and the other end of the first interconnect structure is electrically connected to the second gate.

[0017] One end of the second interconnect structure is electrically connected to the first drain, and the other end of the second interconnect structure is electrically connected to the second drain;

[0018] One end of the third interconnect structure is electrically connected to the first drain and the second drain of the first complementary field-effect transistor, and the other end of the third interconnect structure is electrically connected to the first gate and the second gate of the second complementary field-effect transistor.

[0019] Optionally, the first complementary field-effect transistor and the second complementary field-effect transistor further include a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer;

[0020] The first insulating layer is disposed on the substrate and covers the first source, the first drain and the P-type semiconductor layer, and the first gate is disposed on the upper surface of the first insulating layer;

[0021] The second insulating layer is disposed on the upper surface of the first insulating layer, and the first insulating layer covers the first gate.

[0022] The third insulating layer is disposed above the second insulating layer, and the third insulating layer covers the second gate.

[0023] The fourth insulating layer is disposed between the second insulating layer and the third insulating layer.

[0024] Optionally, the first complementary field-effect transistor and the second complementary field-effect transistor further include a first source plate, a first drain plate, a first gate plate, and an interconnect plate;

[0025] The first source electrode plate is disposed in the fourth insulating layer above the second insulating layer, and the first source electrode plate is electrically connected to the first source electrode.

[0026] The first drain electrode plate is disposed in the fourth insulating layer above the second insulating layer, and the first drain electrode plate is electrically connected to the first drain electrode.

[0027] The first gate electrode is disposed in the fourth insulating layer above the second insulating layer, and the first gate electrode is electrically connected to the first gate.

[0028] The interconnect plate is disposed in a fourth insulating layer above the second insulating layer. One end of the interconnect plate is electrically connected to the first drain plate of the first complementary field-effect transistor, and the interconnect plate is electrically connected to the first gate plate of the second complementary field-effect transistor.

[0029] Optionally, the sensing unit is disposed above the N-type semiconductor layer of the second transistor and is in contact with the external environment.

[0030] Optionally, the P-type semiconductor layer of the first transistor is made of P-type low-temperature polycrystalline silicon, and the N-type semiconductor layer of the second transistor is made of N-type oxide semiconductor.

[0031] According to a second aspect of this disclosure, a method for forming a transistor-type active amplification sensor device is provided, comprising:

[0032] Provide substrate;

[0033] A first transistor having a first complementary field-effect transistor and a second complementary field-effect transistor formed on the substrate, the first transistor comprising a first source, a first drain, a P-type semiconductor layer and a first gate, the first source and the first drain being formed on opposite sides of the P-type semiconductor layer along a first direction, and the first gate being formed above the P-type semiconductor layer along a second direction, the first direction being parallel to the top surface of the substrate and the second direction being perpendicular to the top surface of the substrate;

[0034] A first interconnect structure electrically connected to the first gate, a second interconnect structure electrically connected to the first drain, a second drain of the first complementary field-effect transistor, and a third interconnect structure electrically connected to the first gate of the second complementary field-effect transistor are formed above the first transistor.

[0035] A second transistor is formed above the first transistor of the first complementary field-effect transistor and the second complementary field-effect transistor. The second transistor includes a second source, a second drain, an N-type semiconductor layer and a second gate. The second source and the second drain are formed on opposite sides of the N-type semiconductor layer along the first direction. The second gate is formed below the N-type semiconductor layer along the second direction. The second gate is electrically connected to the first interconnect structure and the second drain is electrically connected to the second interconnect structure.

[0036] A colloidal quantum dot is formed above the N-type semiconductor of the first complementary field-effect transistor to generate a sensing unit.

[0037] Compared with the prior art, the embodiments disclosed herein have at least one of the following beneficial effects:

[0038] The above technical solution uses the output terminal of the first complementary field-effect transistor (CFPT) and the input terminal of the second CFPT to form a photosensitive amplifier circuit for forward signal amplification. The N-type semiconductor layer of the second CFPT and the colloidal quantum dot form a sensing unit to sense the external environment and generate a potential input signal, thereby achieving a response to weak signals. Both the first and second CFPTs adopt a monolithic three-dimensional integrated structure, which can effectively improve the integration of the transistor active amplifier sensor, reduce the size of the transistor active amplifier sensor, achieve higher spatial resolution, and improve the performance of the semiconductor structure.

[0039] In the embodiments of this disclosure, the transistor active amplification sensor device adopts a bottom-up monolithic three-dimensional integration fabrication method, in which the second transistor is fabricated above the region of the first transistor. Furthermore, the first transistor is a P-type transistor and the second transistor is an N-type transistor, which can improve the integration density inside the complementary field-effect transistor, reduce the size of the complementary field-effect transistor, and improve the performance of the semiconductor structure. Attached Figure Description

[0040] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0041] Figure 1 This is a schematic cross-sectional view of a transistor-type active amplification sensor device according to an exemplary embodiment.

[0042] Figure 2 This is a circuit diagram of a transistor-type active amplifier sensor device according to an exemplary embodiment.

[0043] Figure 3 This is an exemplary embodiment illustrating the input-output curves of a first complementary field-effect transistor, a second complementary field-effect transistor, the entire transistor-type active amplification sensor device, and a schematic diagram of the amplification of the target sensing signal.

[0044] Figure 4 This is a flowchart illustrating a method for forming a transistor-type active amplification sensor device according to an exemplary embodiment.

[0045] Explanation of reference numerals in the attached figures

[0046] 100-transistor active amplifier sensor device

[0047] 110 First Complementary Field-Effect Transistor

[0048] 11 Substrate

[0049] 12 First transistor

[0050] 13 First Source Pole

[0051] 14 First Drain

[0052] 15 P-type semiconductor layers

[0053] 16 First gate

[0054] 17 First Insulation Layer

[0055] 18 Second Insulation Layer

[0056] 19 Third Insulation Layer

[0057] 20 Fourth Insulation Layer

[0058] 21 First Source Plate

[0059] 22 First drain plate

[0060] 23 First gate plate

[0061] 24 Second transistor

[0062] 25 Second Source

[0063] 26 Second Drain

[0064] 27 N-type semiconductor layers

[0065] 28 Second gate

[0066] 29 First Interconnection Structure

[0067] 30 Second Interconnection Structure

[0068] 31 Third Interconnection Structure

[0069] 32 First contact plug

[0070] 33 Second contact plug

[0071] 34 Third contact plug

[0072] 35 Sensing layer

[0073] 120 Second Complementary Field-Effect Transistor Detailed Implementation

[0074] The present disclosure will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present disclosure, but do not limit the present disclosure in any way. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present disclosure. These all fall within the protection scope of the present disclosure.

[0075] Figure 1 This is a schematic cross-sectional view of a transistor-type active amplification sensor device according to an exemplary embodiment.

[0076] like Figure 1 As shown, this disclosure provides a transistor-type active amplification sensor device 100, including: a photosensitive amplification circuit.

[0077] The optical sensing amplifier circuit includes a first complementary field-effect transistor 110, a second complementary field-effect transistor 120, and a sensing unit. The output terminal of the first complementary field-effect transistor 110 is connected to the input terminal of the second complementary field-effect transistor 120. The first complementary field-effect transistor 110 and the second complementary field-effect transistor are monolithic three-dimensional integrated structures. The optical sensing amplifier circuit is used to amplify the signal in the forward direction.

[0078] Both the first complementary field-effect transistor 110 and the second complementary field-effect transistor 120 are monolithic three-dimensional integrated structures comprising a P-type low-temperature polysilicon transistor and an N-type atomic layer deposited oxide transistor. The first complementary field-effect transistor 110 is used for inverting signal amplification, and the second complementary field-effect transistor 120 is also used for inverting signal amplification. Thus, the photosensitive amplifier circuit has the function of forward signal amplification.

[0079] like Figure 1 As shown, in this disclosure, the first complementary field-effect transistor 110 is composed of a first transistor 12 and a second transistor 24 connected by a first interconnect structure 29 and a second interconnect structure 30, and the second complementary field-effect transistor 120 is composed of a first transistor 12 and a second transistor 24 connected by a first interconnect structure 29 and a second interconnect structure 30.

[0080] The N-type semiconductor layer 27 of the second transistor 24 of the first complementary field-effect transistor 110 forms a sensing unit with the colloidal quantum dot. The sensing unit is used to sense the external environment and generate a potential input signal.

[0081] The sensing unit comprises an N-type atomic layer deposited oxide transistor semiconductor layer and colloidal quantum dots, and the sensing unit is a heterogeneous structure.

[0082] Through the above technical solution, an optical sensing amplifier circuit is formed by connecting the output terminal of the first complementary field-effect transistor 110 and the input terminal of the second complementary field-effect transistor 120 to amplify the signal in the forward direction. The N-type semiconductor layer 27 of the second transistor 24 of the first complementary field-effect transistor 110 and the colloidal quantum dot form a sensing unit to sense the external environment and generate a potential input signal, thereby realizing the response to weak signals. Both the first complementary field-effect transistor 110 and the second complementary field-effect transistor 120 adopt a monolithic three-dimensional integrated structure, which can effectively improve the integration of the transistor active amplification sensor, reduce the size of the transistor active amplification sensor, achieve higher spatial resolution, and improve the performance of the semiconductor structure.

[0083] In one possible embodiment, the semiconductor layer of the second transistor 24 of the first complementary field-effect transistor 110 and the second transistor 24 of the second complementary field-effect transistor 120 is made of any one or more combinations of ZnO, IZO, and IGZO, and the material of the colloidal quantum dots is made of any one or more combinations of Ag2Te, InP, and AgS.

[0084] The semiconductor layer of the second transistor 24 in the heterojunction of the sensing unit is preferably made of a material with high mobility, and the colloidal quantum dot is preferably made of a non-toxic quantum dot material.

[0085] like Figure 1 As shown, in one possible embodiment, the first complementary field-effect transistor 110 includes a substrate 11, a first transistor 12, and a second transistor 24, with the first transistor 12 disposed above the substrate 11 and the second transistor 24 disposed above the first transistor 12.

[0086] The second complementary field-effect transistor 120 includes a substrate 11, a first transistor 12, and a second transistor 24. The first transistor 12 is disposed above the substrate 11, and the second transistor 24 is disposed above the first transistor 12.

[0087] In this disclosure, the first transistor 12 includes a first source 13, a first drain 14, a P-type semiconductor layer 15, and a first gate 16. The first source 13 and the first drain 14 are respectively disposed on opposite sides of the P-type semiconductor layer 15 along a first direction, and the first source 13 and the first drain 14 are respectively contacted and connected to the P-type semiconductor layer 15. The first gate 16 is disposed above the P-type semiconductor layer 15 along a second direction. The first direction is parallel to the top surface of the substrate 11, and the second direction is perpendicular to the top surface of the substrate 11.

[0088] The first direction can be represented as the direction where D1 is located, and the second direction can be represented as the direction where D2 is located. Specifically, the first source 13 can be located on the left side of the P-type semiconductor layer 15, and the first drain 14 can be located on the right side of the P-type semiconductor layer 15. Furthermore, the first source 13 is in contact with the P-type semiconductor layer 15, and the first drain 14 is in contact with the P-type semiconductor layer 15.

[0089] The P-type semiconductor layer 15 of the first transistor 12 is made of P-type low-temperature polycrystalline silicon semiconductor material, and the electron mobility of the P-type semiconductor layer 15 is greater than 50 cm⁻¹. 2 / V·s. The P-type semiconductor layer 15 is stable under high temperature conditions (e.g., 400°C) to prevent the fabrication process of the second transistor 24 from affecting the P-type semiconductor layer 15.

[0090] The second transistor 24 includes a second source 25, a second drain 26, an N-type semiconductor layer 27, and a second gate 28. The second source 25 and the second drain 26 are respectively disposed on opposite sides of the N-type semiconductor layer 27 along a first direction. The second source 25 and the second drain 26 are respectively contacted and connected to the N-type semiconductor layer 27. The second gate 28 is disposed below the N-type semiconductor layer 27 along a second direction.

[0091] The second source 25 is in contact with the N-type semiconductor layer 27, and the second drain 26 is in contact with the N-type semiconductor layer 27.

[0092] The N-type semiconductor layer 27 of the second transistor 24 is made of N-type oxide semiconductor material, and the electron mobility of the N-type semiconductor layer 27 is greater than 20 cm⁻¹. 2 / V·s. Furthermore, the N-type semiconductor layer 27 in the second transistor 24 is formed using an atomic layer deposition process.

[0093] Specifically, the material of the N-type semiconductor layer 27 can be indium oxide. The material of the N-type semiconductor layer 27 can be indium oxide prepared by atomic layer deposition (ALD) or a multi-component oxide material containing indium oxide, such as indium gallium zinc oxide (IGZO), prepared by ALD. Furthermore, the fabrication process of the N-type semiconductor is relatively low, typically below 400°C, which will not affect the performance of the first transistor 12 located in the lower layer, and the leakage current of the formed second transistor 24 is low, for example, less than 10 Ω·cm. -17 A / μm, which helps to improve the performance of semiconductor structures.

[0094] like Figure 1 As shown, in one possible embodiment, the optical sensing amplifier circuit further includes a first interconnect structure 29, a second interconnect structure 30, and a third interconnect structure 31.

[0095] One end of the first interconnect structure 29 is electrically connected to the first gate 16, and the other end of the first interconnect structure 29 is electrically connected to the second gate 28.

[0096] One end of the second interconnect structure 30 is electrically connected to the first drain 14, and the other end of the second interconnect structure 30 is electrically connected to the second drain 26.

[0097] One end of the third interconnect structure 31 is electrically connected to the first drain 14 and the second drain 26 of the first complementary field-effect transistor 110, and the other end of the third interconnect structure 31 is electrically connected to the first gate 16 and the second gate 28 of the second complementary field-effect transistor 120.

[0098] Specifically, one end of the third interconnect structure 31 is electrically connected to the second drain 26 of the first complementary field-effect transistor 110, and the second drain 26 of the first complementary field-effect transistor 110 is electrically connected to the first drain 14 of the first complementary field-effect transistor 110 through the second interconnect structure 30. Thus, one end of the third interconnect structure 31 is electrically connected to the first drain 14 and the second drain 26 of the first complementary field-effect transistor 110. The other end of the third interconnect structure 31 is electrically connected to the first gate 16 of the second complementary field-effect transistor 120, and the second gate 28 of the second complementary field-effect transistor 120 is electrically connected to the first gate 16 of the second complementary field-effect transistor 120 through the first interconnect structure 29. Thus, the other end of the third interconnect structure 31 is electrically connected to the first gate 16 and the second gate 28 of the second complementary field-effect transistor 120.

[0099] The semiconductor structures of the first complementary field-effect transistor 110 and the second complementary field-effect transistor 120 in this disclosure can be, but are not limited to, inverters. The following description uses a monolithic three-dimensional integrated semiconductor structure as an example of a monolithic three-dimensional integrated multi-stage inverter.

[0100] like Figure 1 As shown, a monolithic three-dimensional integrated semiconductor structure may include multiple complementary field-effect transistors. The first source 13, the first drain 14, and the P-type semiconductor layer 15 of the first transistor 12 of each complementary field-effect transistor are disposed on the same layer, and the first gate 16 is disposed above the P-type semiconductor layer 15 along the second direction D2 to form a top-gate transistor.

[0101] The second source 25, second drain 26, and N-type semiconductor layer 27 of the second transistor 24 of each complementary field-effect transistor are disposed on the same layer, and the second gate 28 is disposed below the N-type semiconductor layer 27 along the second direction D2 to form a bottom gate transistor. This enables the first gate 16 of the first transistor 12 and the second gate 28 of the second transistor 24 in each complementary field-effect transistor to be electrically connected by a through-hole structure, further reducing the size of the complementary field-effect transistor and simplifying the manufacturing process of the semiconductor structure.

[0102] In each complementary field-effect transistor (CFPT), the first gate 16 of the first transistor 12 is electrically connected to the second gate 28 of the second transistor 24 via a first interconnect structure 29, and the first drain 14 of the first transistor 12 is electrically connected to the second drain 26 of the second transistor 24 via a second interconnect structure 30, thereby forming an inverter circuit in the CFPT cell. The second drain 26 of the second transistor 24 of the first CFPT 110 is electrically connected to the first gate 16 of the first transistor 12 of the second CFPT 120 via a third interconnect structure 31, forming a two-stage inverter structure.

[0103] During the operation of the semiconductor structure, the first source 13 of the first complementary field-effect transistor 110 and the first source 13 of the second complementary field-effect transistor 120 are connected to a high level, the second source 25 of the first complementary field-effect transistor 110 and the second source 25 of the second complementary field-effect transistor 120 are grounded, the first gate 16 of the first complementary field-effect transistor 110 is connected to the input voltage, and the first drain 14 of the second complementary field-effect transistor 120 outputs the output voltage.

[0104] The above embodiments are illustrated using two complementary field-effect transistors as an example. In reality, a monolithic three-dimensional integrated semiconductor structure may include two or more complementary field-effect transistors.

[0105] In this disclosure, the top surface of substrate 11 represents the surface of substrate 11 facing the first transistor 12.

[0106] like Figure 1 As shown, the first transistor 12, the interconnect structure (including the first interconnect structure 29, the second interconnect structure 30, and the third interconnect structure 31), and the second transistor 24 are arranged sequentially from bottom to top. This ensures that the density of the first transistor 12 and the second transistor 24 in the semiconductor structure is not affected by the size of the interconnect structure, the size of other internal conductive lines, or the size of vias, achieving high-density monolithic three-dimensional integration. Simultaneously, this bottom-up monolithic three-dimensional integration method significantly improves the integration density of components within the complementary field-effect transistor and the overall semiconductor structure, contributing to a reduction in the size of the semiconductor structure.

[0107] To further reduce the size of complementary field-effect transistor (CFPT) cells and thus further improve the integration density of semiconductor structures, this disclosure uses the example of a second transistor 24 located directly above a first transistor 12 along the second direction D2 within the same CFPT cell. In other embodiments, the second transistor 24 and the first transistor 12 within the same CFPT cell can be staggered along the second direction D2; for example, the second transistor 24 may be located diagonally above the first transistor 12 along the second direction D2.

[0108] like Figure 1 As shown, in one possible embodiment, the first complementary field-effect transistor 110 and the second complementary field-effect transistor 120 further include a first insulating layer 17, a second insulating layer 18, a third insulating layer 19, and a fourth insulating layer 20.

[0109] The first insulating layer 17 is disposed on the substrate 11, and the first insulating layer 17 covers the first source 13, the first drain 14 and the P-type semiconductor layer 15, and the first gate 16 is disposed on the upper surface of the first insulating layer 17.

[0110] The first insulating layer 17 is disposed on the top surface of the substrate 11.

[0111] The second insulating layer 18 is disposed on the upper surface of the first insulating layer 17, and the first insulating layer 17 covers the first gate 16.

[0112] The third insulating layer 19 is disposed above the second insulating layer 18, and the third insulating layer 19 covers the second gate 28.

[0113] The second source electrode 25 and the second drain electrode 26 are disposed on the upper surface of the third insulating layer 19.

[0114] The fourth insulating layer 20 is disposed between the second insulating layer 18 and the third insulating layer 19.

[0115] like Figure 1 As shown, in one possible embodiment, the first complementary field-effect transistor 110 and the second complementary field-effect transistor 120 further include a first source plate 21, a first drain plate 22, a first gate plate 23, and an interconnect plate.

[0116] The first source electrode plate 21 is disposed in the fourth insulating layer 20 above the second insulating layer 18, and the first source electrode plate 21 is electrically connected to the first source electrode 13.

[0117] The first drain plate 22 is disposed in the fourth insulating layer 20 above the second insulating layer 18, and the first drain plate 22 is electrically connected to the first drain 14.

[0118] The first gate plate 23 is disposed in the fourth insulating layer 20 above the second insulating layer 18, and the first gate plate 23 is electrically connected to the first gate 16.

[0119] The interconnect plate is disposed in the fourth insulating layer 20 above the second insulating layer 18. One end of the interconnect plate is electrically connected to the first drain plate 22 of the first complementary field-effect transistor 110, and the interconnect plate is electrically connected to the first gate plate 23 of the second complementary field-effect transistor 120.

[0120] like Figure 1 As shown, the first interconnect structure 29 includes a first portion that penetrates the fourth insulating layer 20 along the second direction D2 and is in contact with and electrically connected to the first gate plate 23, and a second portion that is located on the surface of the fourth insulating layer 20 and is electrically connected to the first portion, with the second gate 28 located on the surface of the second portion.

[0121] The second interconnection structure 30 includes a third part that penetrates the fourth insulating layer 20 along the second direction D2 and is in contact with and electrically connected to the first drain plate 22, and a fourth part that is located on the surface of the fourth insulating layer 20 and is in contact with and electrically connected to the third part, and the fourth part is in contact with and electrically connected to the second drain 26.

[0122] The third interconnect structure 31 includes a fourth insulating layer 20 extending along the second direction D2, and the other end of the third interconnect structure 31 is electrically connected to the second drain 26 in the first complementary field-effect transistor 110, and one end of the third interconnect structure 31 is electrically connected to the first gate plate 23 in the second complementary field-effect transistor 120.

[0123] Specifically, such as Figure 1As shown, a first source 13, a first drain 14, and a P-type semiconductor layer 15 are disposed on the top surface of a substrate 11 in the same layer. A first insulating layer 17 is located on the top surface of the substrate 11 and covers the first source 13, the first drain 14, and the P-type semiconductor layer 15. A first gate 16 is located on the upper surface of the first insulating layer 17, i.e., on the surface of the first insulating layer 17 facing away from the substrate 11. A second insulating layer 18 is located on the upper surface of the first insulating layer 17 and covers the first gate 16. A first source plate 21, a first drain plate 22, and a first gate plate 23 are disposed in the same layer on the upper surface of the second insulating layer 18 facing away from the first insulating layer 17. The first source plate 21 is electrically connected to the first source 13 through a first contact plug 32 that continuously penetrates the first insulating layer 17 and the second insulating layer 18 along the second direction D2. The first drain plate 22 is electrically connected to the first drain 14 through a second contact plug 33 that continuously penetrates the first insulating layer 17 and the second insulating layer 18 along the second direction D2. During operation of the semiconductor structure (e.g., an inverter), the first drain plate 22 of the second complementary field-effect transistor 120 serves as the output voltage port of the inverter. The first gate plate 23 is electrically connected to the first gate 16 via a third contact plug 34 that continuously penetrates the first insulating layer 17 and the second insulating layer 18 along the second direction D2. The fourth insulating layer 20 is located on the upper surface of the second insulating layer 18, that is, on the surface of the second insulating layer 18 facing away from the first insulating layer 17, and the fourth insulating layer 20 covers the first source plate 21, the first drain plate 22, and the first gate plate 23.

[0124] A first portion of the first interconnect structure 29 penetrates the fourth insulating layer 20 along the second direction D2 and is electrically connected to the first gate plate 23. A second portion of the first interconnect structure 29 is located on the top surface of the first portion and on the top surface of a portion of the fourth insulating layer 20. A third portion of the second interconnect structure 30 penetrates the fourth insulating layer 20 along the second direction D2 and is electrically connected to the first drain plate 22. A fourth portion of the second interconnect structure 30 is located on the top surface of the third portion and on the top surface of a portion of the fourth insulating layer 20. A second gate 28 is located on the surface of the second portion of the first interconnect structure 29, i.e., the second gate 28 is electrically connected to the second portion of the first interconnect structure 29. A third insulating layer 19 is located on the surface of the fourth insulating layer 20 and covers the second gate 28, the first interconnect structure 29, and the second interconnect structure 30. The third insulating layer 19 exposes the opening of the fourth portion of the second interconnect structure 30. The second source 25, the second drain 26, and the N-type semiconductor layer 27 are located on the upper surface of the third insulating layer 19, that is, on the surface of the third insulating layer 19 opposite to the fourth insulating layer 20, and the second drain 26 extends into the opening to make contact with the second interconnect structure 30 for electrical connection.

[0125] The third insulating layer 19 is prepared by atomic layer deposition and is made of alumina or hafnium oxide, which are metal oxide materials with high dielectric constants.

[0126] The materials of the first interconnect structure 29 and the second interconnect structure 30 are both indium tin oxide (ITO), molybdenum (Mo), and aluminum (Al), or a combination of two or more of them.

[0127] In one example, the materials of the first interconnect structure 29 and the second interconnect structure 30 are both ITO, Mo / ITO (i.e., a combination of Mo and ITO materials) or Mo / Al / Mo (i.e., a combination of Mo and Al materials).

[0128] This embodiment is illustrated using the example of the second gate 28 being located on the surface of the first interconnect structure 29 (i.e., there is a contact interface between the second gate 28 and the first interconnect structure 29). In other embodiments, to further reduce the contact resistance between the second gate 28 and the first interconnect structure 29 and to further simplify the semiconductor fabrication process, the second gate 28 and 32 can be formed simultaneously with the first interconnect structure 29, i.e., there is no contact interface between the second portion of the first interconnect structure 29 and the second gate 28, and both are deposited through a one-step conductive material deposition process.

[0129] The materials of the second gate 28, the second source 25, and the second drain 26 are all nickel, gold, titanium, or a combination of two or more of them.

[0130] The material of the sensing layer 34 of the sensing unit located above the N-type semiconductor layer 27 of the second transistor 24 in the first complementary field-effect transistor 110 can be a material with excellent light absorption properties, such as quantum dots.

[0131] In one possible embodiment, the sensing unit is disposed above the N-type semiconductor layer 27 of the second transistor 24 of the first complementary field-effect transistor 110 and in contact with the external environment, and can be used to sense changes in ambient light and generate a potential input signal.

[0132] Figure 2 This is a circuit diagram of a transistor-type active amplifier sensor device according to an exemplary embodiment.

[0133] like Figure 2 As shown, in the circuit of the transistor-type active amplifier sensor device 100, V IN This indicates the voltage input terminal, V of the transistor-type active amplifier sensor device 100. OUT GND represents the voltage output terminal of the transistor-type active amplifier sensor device 100, and GND represents the ground terminal of the transistor-type active amplifier sensor device 100. DDThis indicates the driving voltage terminal of the transistor-type active amplifier sensor device 100.

[0134] Wherein, T1 represents the first transistor 12 of the first complementary field-effect transistor 110, T2 represents the second transistor 24 of the first complementary field-effect transistor 110, T3 represents the first transistor 12 of the second complementary field-effect transistor 120, and T4 represents the second transistor 24 of the second complementary field-effect transistor 120.

[0135] Figure 3 This is an exemplary embodiment illustrating the input-output curves of a first complementary field-effect transistor, a second complementary field-effect transistor, the entire transistor-type active amplification sensor device, and a schematic diagram of the amplification of the target sensing signal.

[0136] like Figure 3 As shown, the first complementary field-effect transistor 110 and the second complementary field-effect transistor 120 have reverse signal amplification function, which amplifies the target sensing signal in reverse. The entire transistor-type active amplification sensor device 100 has forward amplification function, which amplifies the target sensing signal in forward.

[0137] Figure 4 This is a flowchart illustrating a method for forming a transistor-type active amplification sensor device according to an exemplary embodiment.

[0138] like Figure 4 As shown, this disclosure also provides a method for forming a transistor-type active amplification sensor device, including steps S11 to S14.

[0139] S11 provides a substrate.

[0140] S12, a first transistor is formed on the substrate, comprising a first complementary field-effect transistor and a second complementary field-effect transistor. The first transistor includes a first source, a first drain, a P-type semiconductor layer and a first gate. The first source and the first drain are formed on opposite sides of the P-type semiconductor layer along a first direction. The first gate is formed above the P-type semiconductor layer along a second direction. The first direction is parallel to the top surface of the substrate and the second direction is perpendicular to the top surface of the substrate.

[0141] S13, a first interconnect structure electrically connected to the first gate is formed above the first transistor, a second interconnect structure electrically connected to the first drain is formed, a third interconnect structure electrically connected to the second drain of the first complementary field-effect transistor and the first gate of the second complementary field-effect transistor is formed.

[0142] S14, a second transistor is formed above the first transistor of the first complementary field-effect transistor and the second complementary field-effect transistor. The second transistor includes a second source, a second drain, an N-type semiconductor layer and a second gate. The second source and the second drain are formed on opposite sides of the N-type semiconductor layer along the first direction. The second gate is formed below the N-type semiconductor layer along the second direction. The second gate is electrically connected to the first interconnect structure and the second drain is electrically connected to the second interconnect structure.

[0143] The second source and the second drain are respectively connected to the N-type semiconductor, and the second drain of the first complementary field-effect transistor and the first gate of the second complementary field-effect transistor are electrically connected through the third interconnect structure.

[0144] S15, a colloidal quantum dot is formed above the N-type semiconductor of the first complementary field-effect transistor to generate a sensing unit.

[0145] Specifically, a sensing layer is prepared by forming colloidal quantum dots on the N-type semiconductor layer of the second transistor of the first complementary field-effect transistor, thereby generating a sensing unit.

[0146] The N-type semiconductor layer in the second transistor is formed using an atomic layer deposition process at a temperature of less than 400°C.

[0147] The N-type semiconductor layer of the upper transistor is fabricated at a lower temperature, which does not affect the performance of the lower first transistor. Furthermore, the N-type semiconductor layer of the first transistor is deposited using atomic layer deposition, which not only allows for large-area uniform deposition but also enables control over the thickness and properties of the semiconductor film, resulting in a high-performance transistor. The fabrication temperature of the complementary field-effect transistor is compatible with the manufacturing process of CMOS integrated circuits, thereby contributing to further improvements in the performance of monolithic 3D integrated semiconductor structures and expanding their application areas.

[0148] Through the above technical solution, the transistor active amplification sensor device adopts a bottom-up monolithic three-dimensional integration fabrication method, in which the second transistor is fabricated above the region of the first transistor. Furthermore, the first transistor is a P-type transistor and the second transistor is an N-type transistor, which can improve the integration density inside the complementary field-effect transistor, reduce the size of the complementary field-effect transistor, and improve the performance of the semiconductor structure.

[0149] The specific embodiments of this disclosure have been described above. It should be understood that this disclosure is not limited to the specific embodiments described above, and those skilled in the art can make various modifications or variations within the scope of the claims, which do not affect the substantive content of this disclosure. The above-described preferred features can be used in any combination without conflict.

Claims

1. A transistor-type active amplifier sensor device, characterized in that, include: Optical sensing amplifier circuit; The optical sensing amplifier circuit includes a first complementary field-effect transistor, a second complementary field-effect transistor, and a sensing unit. The output terminal of the first complementary field-effect transistor is connected to the input terminal of the second complementary field-effect transistor. The first complementary field-effect transistor and the second complementary field-effect transistor are monolithic three-dimensional integrated structures. The optical sensing amplifier circuit is used for forward amplification of signals. The sensing unit is formed by the N-type semiconductor layer of the second transistor of the first complementary field-effect transistor and colloidal quantum dots. The sensing unit is used to sense the external environment and generate a potential input signal.

2. The transistor-type active amplifier sensor device according to claim 1, characterized in that, The semiconductor layer of the second transistor is made of one or more of ZnO, IZO, and IGZO, and the colloidal quantum dots are made of one or more of Ag2Te, InP, and AgS.

3. The transistor-type active amplifier sensor device according to claim 1, characterized in that, The first complementary field-effect transistor includes a substrate, a first transistor, and a second transistor, wherein the first transistor is disposed above the substrate, and the second transistor is disposed above the first transistor. The second complementary field-effect transistor includes a substrate, a first transistor, and a second transistor, wherein the first transistor is disposed above the substrate and the second transistor is disposed above the first transistor.

4. The transistor-type active amplifier sensor device according to claim 3, characterized in that, The first transistor includes a first source, a first drain, a P-type semiconductor layer, and a first gate. The first source and the first drain are respectively disposed on opposite sides of the P-type semiconductor layer along a first direction. The first source and the first drain are respectively contacted and connected to the P-type semiconductor layer. The first gate is disposed above the P-type semiconductor layer along a second direction. The first direction is parallel to the top surface of the substrate, and the second direction is perpendicular to the top surface of the substrate. The second transistor includes a second source, a second drain, an N-type semiconductor layer, and a second gate. The second source and the second drain are respectively disposed on opposite sides of the N-type semiconductor layer along the first direction. The second source and the second drain are respectively contacted and connected to the N-type semiconductor layer. The second gate is disposed below the N-type semiconductor layer along the second direction.

5. The transistor-type active amplifier sensor device according to claim 4, characterized in that, The optical sensing amplifier circuit further includes a first interconnect structure, a second interconnect structure, and a third interconnect structure; One end of the first interconnect structure is electrically connected to the first gate, and the other end of the first interconnect structure is electrically connected to the second gate. One end of the second interconnect structure is electrically connected to the first drain, and the other end of the second interconnect structure is electrically connected to the second drain; One end of the third interconnect structure is electrically connected to the first drain and the second drain of the first complementary field-effect transistor, and the other end of the third interconnect structure is electrically connected to the first gate and the second gate of the second complementary field-effect transistor.

6. The transistor-type active amplifier sensor device according to claim 4, characterized in that, The first complementary field-effect transistor and the second complementary field-effect transistor further include a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer; The first insulating layer is disposed on the substrate and covers the first source, the first drain and the P-type semiconductor layer, and the first gate is disposed on the upper surface of the first insulating layer; The second insulating layer is disposed on the upper surface of the first insulating layer, and the first insulating layer covers the first gate. The third insulating layer is disposed above the second insulating layer, and the third insulating layer covers the second gate. The fourth insulating layer is disposed between the second insulating layer and the third insulating layer.

7. The transistor-type active amplifier sensor device according to claim 6, characterized in that, The first complementary field-effect transistor and the second complementary field-effect transistor further include a first source plate, a first drain plate, a first gate plate, and an interconnect plate; The first source electrode plate is disposed in the fourth insulating layer above the second insulating layer, and the first source electrode plate is electrically connected to the first source electrode. The first drain electrode plate is disposed in the fourth insulating layer above the second insulating layer, and the first drain electrode plate is electrically connected to the first drain electrode. The first gate electrode is disposed in the fourth insulating layer above the second insulating layer, and the first gate electrode is electrically connected to the first gate. The interconnect plate is disposed in a fourth insulating layer above the second insulating layer. One end of the interconnect plate is electrically connected to the first drain plate of the first complementary field-effect transistor, and the interconnect plate is electrically connected to the first gate plate of the second complementary field-effect transistor.

8. The transistor-type active amplifier sensor device according to claim 4, characterized in that, The sensing unit is disposed above the N-type semiconductor layer of the second transistor and is in contact with the external environment.

9. The transistor-type active amplifier sensor device according to claim 4, characterized in that, The P-type semiconductor layer of the first transistor is made of P-type low-temperature polycrystalline silicon, and the N-type semiconductor layer of the second transistor is made of N-type oxide semiconductor.

10. A method for forming a transistor-type active amplification sensor device, characterized in that, include: Provide substrate; A first transistor having a first complementary field-effect transistor and a second complementary field-effect transistor formed on the substrate, the first transistor comprising a first source, a first drain, a P-type semiconductor layer and a first gate, the first source and the first drain being formed on opposite sides of the P-type semiconductor layer along a first direction, and the first gate being formed above the P-type semiconductor layer along a second direction, the first direction being parallel to the top surface of the substrate and the second direction being perpendicular to the top surface of the substrate; A first interconnect structure electrically connected to the first gate is formed above the first transistor, a second interconnect structure electrically connected to the first drain is formed, a second drain of the first complementary field-effect transistor and a third interconnect structure electrically connected to the first gate of the second complementary field-effect transistor are formed. A second transistor is formed above the first transistor of the first complementary field-effect transistor and the second complementary field-effect transistor. The second transistor includes a second source, a second drain, an N-type semiconductor layer and a second gate. The second source and the second drain are formed on opposite sides of the N-type semiconductor layer along the first direction. The second gate is formed below the N-type semiconductor layer along the second direction. The second gate is electrically connected to the first interconnect structure and the second drain is electrically connected to the second interconnect structure. A colloidal quantum dot is formed above the N-type semiconductor of the first complementary field-effect transistor to generate a sensing unit.

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