Digital Hall effect IC, detection system and address allocation method

Abstract

This application provides a digital Hall effect IC, a detection system, and an address allocation method. The digital Hall effect IC includes a first interface, a second interface, and an address management module. The address management module is connected to a first device through the first interface and to a second device through the second interface. The address management module determines a new communication address based on a communication address sent by the first device and sends the new communication address to the second device. Through the address allocation function of the address management module of the digital Hall effect IC, and via the connection of the first and second interfaces, the digital Hall effect IC can allocate communication addresses to itself or its connected downstream digital Hall effect ICs, facilitating the management of addresses for multiple digital Hall effect ICs in the system.

Description

Technical Field

[0001] This application relates to the field of circuit detection technology, and in particular to a digital Hall effect IC, a detection system, and an address allocation method. Background Technology

[0002] In high-voltage direct current (HVDC) system branch insulation testing, leakage current detection schemes have gradually shifted from traditional analog Hall effect sensors to digital Hall effect sensors. Compared to analog Hall effect sensors, digital Hall effect sensors offer higher integration, stronger noise immunity, and self-calibration capabilities, providing a more reliable and accurate leakage current detection solution. In digital Hall effect sensors, the Hall effect sensor communicates with the main monitoring system via a digital interface, transmitting leakage current data. The main monitoring system then calculates the branch insulation resistance and further determines whether a branch insulation fault has occurred. Typically, serial communication is used between the digital Hall effect IC and the main monitoring system.

[0003] In a typical high-voltage direct current (HVDC) system, there are dozens of branches, and each branch's digital Hall effect IC needs to be configured with a different serial communication address to communicate with the main monitoring system. In this application scenario, the communication address for each branch's digital Hall effect IC is usually configured through the main monitoring system's address allocation function or the system's backend software. The former requires the main monitoring system to have address allocation capabilities, while the latter, due to its reliance on system backend software configuration, makes maintenance more complex when replacing the digital Hall effect IC in practical applications. Summary of the Invention

[0004] This application provides a digital Hall effect IC, a detection system, and an address allocation method to solve the problem of complex address allocation and maintenance in the prior art.

[0005] In a first aspect, this application provides a digital Hall IC, which includes a first interface (101), a second interface (102), and an address management module (103). The address management module (103) is connected to a first device (200) through the first interface (101) and to a second device (300) through the second interface (102).

[0006] The address management module (103) is used to determine a new communication address based on the communication address sent by the first device (200) and send the new communication address to the second device (300).

[0007] In one embodiment, the address management module (103) is further configured to configure the communication address sent by the first device (200) as the communication address of the digital Hall IC.

[0008] In one embodiment, the address management module (103) is also configured to set the new communication address as the communication address of the digital Hall IC.

[0009] In one embodiment, the address management module (103) is further configured to search for the communication address corresponding to the communication address sent by the first device (200) in a preset address set, and use it as the new communication address; the preset address set includes multiple different communication addresses.

[0010] In one embodiment, the address management module (103) is also used to determine a new communication address based on a preset address change rule and the communication address sent by the first device (200).

[0011] In one embodiment, a preset address change rule is used to characterize an incremental change in the communication address.

[0012] Secondly, this application provides a detection system, which includes a main control unit (400) and N digital Hall ICs, where N ≥ 2 and N is an integer; the digital Hall ICs include a first interface (101), a second interface (102) and an address management module (103), the address management module (103) being connected to the first interface (101) and the second interface (102), and the main control unit (400) including a third interface (401);

[0013] The first interface (101) of the first digital Hall IC in N digital Hall ICs is connected to the third interface (401), and the second interface (102) of the first N-1 digital Hall ICs is connected to the first interface (101) of the next level digital Hall IC, forming an address management link between the N digital Hall ICs and the main control unit (400).

[0014] The address management module (103) for N digital Hall ICs is used to configure communication addresses for the N digital Hall ICs.

[0015] In one embodiment, the address management module (103) of the first digital Hall IC is also used to determine the communication address of the first digital Hall IC according to the communication address assigned by the main control unit (400).

[0016] In one embodiment, the address management module (103) of the first digital Hall IC is also used to randomly generate the communication address of the first digital Hall IC.

[0017] In one embodiment, the address management module (103) of the first digital Hall IC is also used to determine the communication address of the first digital Hall IC based on the externally set address;

[0018] The external setting address is determined by at least one of three methods: DIP switch, dry contact input signal, and software parameter setting.

[0019] In one embodiment, the address management link uses UART communication.

[0020] Thirdly, this application provides an address allocation method, which is applied to a detection system. The detection system includes a main control unit (400) and N digital Hall ICs, where N ≥ 2 and N is an integer. The digital Hall ICs include a first interface (101), a second interface (102), and an address management module (103). The address management module (103) is connected to the first interface (101) and the second interface (102). The main control unit (400) includes a third interface (401).

[0021] The first interface (101) of the first digital Hall IC in N digital Hall ICs is connected to the third interface (401), and the second interface (102) of the first N-1 digital Hall ICs is connected to the first interface (101) of the next-level digital Hall IC, forming an address management link between the N digital Hall ICs and the main control unit (400); the method is applied to the address management module (103) of the digital Hall IC; the method includes:

[0022] Based on the communication address sent by the previous level digital Hall IC, determine the communication address of the current level digital Hall IC and the communication address to be sent to the next level digital Hall IC.

[0023] In one embodiment, determining the communication address of the current-level digital Hall IC based on the communication address sent by the previous-level digital Hall IC includes:

[0024] Configure the communication address sent by the previous level digital Hall IC as the communication address of the current level digital Hall IC.

[0025] In one embodiment, determining the communication address to be sent to the next-level digital Hall IC based on the communication address sent by the previous-level digital Hall IC includes:

[0026] A new communication address is determined based on the communication address sent by the previous level digital Hall IC;

[0027] The new communication address is sent to the next-level digital Hall IC.

[0028] In one embodiment, determining the communication address of the current-level digital Hall IC and the communication address to be sent to the next-level digital Hall IC based on the communication address sent by the previous-level digital Hall IC includes:

[0029] Based on the communication address sent by the previous level digital Hall IC, a new communication address is determined, and the new communication address is configured as the communication address of the current level digital Hall IC;

[0030] The new communication address is then sent to the communication address of the next-level digital Hall IC.

[0031] In one embodiment, determining a new communication address based on the communication address sent by the previous-level digital Hall IC includes:

[0032] The corresponding communication address sent by the previous level digital Hall IC is found in the preset address set and used as the new communication address; the preset address set includes multiple different communication addresses, and there is a mapping relationship between the multiple different addresses.

[0033] In one embodiment, determining a new communication address based on the communication address sent by the previous-level digital Hall IC includes:

[0034] Based on preset address change rules, the new communication address is determined according to the communication address sent by the previous level digital Hall IC.

[0035] In one embodiment, a preset address change rule is used to characterize an incremental change in the communication address.

[0036] In one embodiment, the method further includes:

[0037] The communication address of the first digital Hall IC is determined based on the communication address sent by the main control unit (400).

[0038] In one embodiment, the method further includes:

[0039] The communication address of the first digital Hall IC is randomly generated.

[0040] In one embodiment, the method further includes:

[0041] The communication address of the first digital Hall IC is determined based on the externally configured address;

[0042] The external setting address is determined by at least one of three methods: DIP switch, dry contact input signal, and software parameter setting.

[0043] Fourthly, embodiments of this application provide an electronic device, including: a memory and a processor;

[0044] The memory stores the instructions that the computer executes;

[0045] The processor executes computer execution instructions stored in memory, causing the processor to perform the third aspect and / or various possible implementations of the third aspect as described above.

[0046] Fifthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the third aspect and / or various possible implementations of the third aspect.

[0047] Sixthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the third aspect and / or various possible implementations of the third aspect as described above.

[0048] This application provides a digital Hall effect IC, a detection system, and an address allocation method. The digital Hall effect IC includes a first interface, a second interface, and an address management module. The address management module is connected to a first device through the first interface and to a second device through the second interface. The address management module determines a new communication address based on a communication address sent by the first device and sends the new communication address to the second device. The address management module enables the digital Hall effect IC to have address management functionality. The connection between the first and second interfaces allows the digital Hall effect IC to allocate communication addresses to itself or its connected downstream digital Hall effect ICs, facilitating the management of addresses for multiple digital Hall effect ICs in the system. Attached Figure Description

[0049] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0050] Figure 1 This is a basic schematic diagram of DC leakage current monitoring provided in one embodiment;

[0051] Figure 2 This is a block diagram of a high-voltage DC system branch insulation detection system provided in one embodiment;

[0052] Figure 3 This is a schematic diagram of the structure of a digital Hall IC provided in one embodiment;

[0053] Figure 4 This is a schematic diagram of the address management link of a detection system provided in one embodiment;

[0054] Figure 5 This is a flowchart illustrating an address allocation method provided in one embodiment;

[0055] Figure 6 This is a schematic diagram of a high-voltage direct current system branch insulation monitoring system provided in one embodiment;

[0056] Figure 7 This is an internal structural diagram of an electronic device provided in one embodiment.

[0057] Explanation of reference numerals in the attached figures:

[0058] 100 - Digital Hall IC; 101 - First interface; 102 - Second interface; 103 - Address management module; 200 - First device; 300 - Second device; 400 - Main control unit; 401 - Third interface.

[0059] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0060] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0061] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0062] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0063] In traditional power system secondary circuits, a 200V / 110V DC power supply system is generally used as the power supply circuit. To ensure high reliability of the secondary circuit power supply and avoid DC bus short circuits caused by grounding at one end due to a drop in insulation at one end, and also to prevent electric shock caused by an effective high DC voltage to ground at the other end due to a drop in insulation at one end and grounding, monitoring the insulation of the positive and negative busbars of the DC power supply system to ground is crucial. With the explosive growth of power consumption systems and the widespread application of high-voltage direct current (HVDC) power supply systems in various power systems, insulation testing of the positive and negative busbars of HVDC power supply systems is also very important from the perspective of maintaining the safety of the power supply system and its operation and maintenance.

[0064] In common DC power supply systems, AC power is typically converted to DC output via a rectifier. To ensure the safety of the DC power supply system and avoid creating a reference voltage to ground, DC power supply systems are generally designed with the positive and negative buses floating to ground. This differs from certain AC power supply standards that use a grounded neutral wire and from -48 / 24V DC communication power supply systems. Insulation testing of a DC power supply system includes insulation monitoring of the DC bus and insulation monitoring of each load branch.

[0065] The basic principle of busbar insulation monitoring is to measure the insulation resistance between the positive and negative poles of the busbar and ground. However, the resistance of a live conductor cannot be directly measured. Therefore, the busbar-to-ground insulation resistance is usually measured by switching sampling resistors between the positive and negative busbars. Different switching resistors and insulation resistances generate different DC voltages to ground. By observing the positive and negative busbar-to-ground voltages under different conditions, the busbar-to-ground insulation resistance can be indirectly calculated. Insulation monitoring of DC branches generally involves monitoring the leakage current of the branch output of the power system. The magnitude of the leakage current is used to determine the corresponding insulation resistance, and an alarm for branch insulation faults is issued.

[0066] Branch circuit insulation monitoring typically employs DC leakage current sensors, such as those using Hall effect sensors or general-purpose amplifiers, based on semiconductor technology. The basic principle of DC leakage current monitoring is as follows: Figure 1 As shown, cables of both positive and negative polarities pass through the leakage current sensor simultaneously. Without insulation degradation, the DC currents flowing through the positive and negative cables are equal in magnitude but opposite in direction, thus preventing the generation of an induced signal on the DC transformer. However, when insulation degradation occurs on one pole, the currents flowing through the positive and negative poles will no longer be equal. The transformer senses this current difference and compares it with the leakage current calculated by the correction resistors controlled by two 30kΩ resistors, K1 and K2. If the leakage current exceeds the alarm threshold, a branch alarm is issued.

[0067] In high-voltage direct current (HVDC) system branch insulation testing, leakage current detection methods are gradually shifting from traditional analog Hall effect sensors to digital Hall effect sensors. Compared to analog Hall effect sensors, digital Hall effect sensors offer higher integration, stronger noise immunity, and self-calibration capabilities, providing a more reliable and accurate leakage current detection solution. For example... Figure 2 As shown, the digital Hall effect IC communicates with the main monitoring unit via a digital interface, sending leakage current data. The main monitoring unit, acting as the master control unit, calculates the branch insulation resistance and further determines whether a branch insulation fault has occurred. Typically, serial communication is used between the digital Hall effect IC and the main control unit.

[0068] In a typical high-voltage direct current (HVDC) system, there are dozens of branches. Each branch's digital Hall effect IC needs to be connected to the main control unit via a serial cable for communication. In this application scenario, the communication address for each branch's digital Hall effect IC is typically configured using either the main control unit's address allocation function or the HVDC system's backend software. The former requires the main control unit to have address allocation capabilities, while the latter, due to its reliance on system backend software configuration, makes maintenance more complex when replacing or adding digital Hall effect ICs in practical applications.

[0069] To address the aforementioned technical problems, embodiments of this application provide a digital Hall effect IC, such as... Figure 3 As shown, the digital Hall IC 100 includes a first interface 101, a second interface 102, and an address management module 103. The address management module 103 is connected to the first device 200 through the first interface 101, and the address management module 103 is connected to the second device 300 through the second interface 102.

[0070] The address management module 103 is used to determine a new communication address based on the communication address sent by the first device 200, and send the new communication address to the second device 300.

[0071] The address management module 103 has the function of communication address management, and can determine a new communication address based on an existing communication address. The address management module 103 is connected to the first device 200 through the first interface 101 and to the second device 300 through the second interface, and is used to complete the transmission of communication addresses. In this embodiment, the first interface 101 and the second interface 102 are used to transmit and allocate communication addresses, and their forms are not limited. The first interface 101 and the second interface 102 can be ports on a digital Hall effect IC or terminal blocks.

[0072] Address management module 103 is connected to first device 200 through first interface 101, forming a one-to-one serial structure between digital Hall IC 100 and first device 200, thereby realizing the allocation and management of communication addresses. Similarly, address management module 103 is connected to second device 300 through second interface 102, forming a one-to-one serial structure between digital Hall IC 100 and second device 300, thereby realizing the allocation and management of communication addresses.

[0073] The first device 200 refers to a device with address transmission function, capable of sending a communication address to the digital Hall IC through the first interface 101. The second device 300 refers to a device with address reception function, to which the address management module 103 of the digital Hall IC sends a communication address through the second interface 102. The device types of the first device 200 and the second device 300 are not limited. In some embodiments, the first device 200 and the second device 300 can both be digital Hall ICs.

[0074] After receiving the communication address sent by the first device 200, the address management module 103 determines the communication address of the digital Hall IC based on the communication address sent by the first device 200, and then sends a new communication address to the second device 300, which determines its own communication address based on the new communication address. Thus, the address management module 103 based on the digital Hall IC can assign a communication address to either the digital Hall IC or the second device 300.

[0075] Specifically, the address management module can configure the communication address sent by the first device 200 as the communication address of the digital Hall IC. It can also configure a new communication address determined by the digital Hall IC as the communication address of the digital Hall IC.

[0076] The new communication address is determined based on the received communication address, and the new communication address is different from the received communication address.

[0077] For example, the address management module 103 is also used to find the corresponding communication address of the communication address sent by the first device 200 in the preset address set, and use it as the new communication address; the preset address set includes multiple different communication addresses. The preset address set refers to a set of multiple different communication addresses generated in advance and stored in a certain or fixed order. After the address management module 103 receives the communication address sent by the first device 200, it searches for the next corresponding communication address of the communication address sent by the first device 200 in the preset address set, uses it as the new communication address, and sends it to the second device 300.

[0078] The above requires a pre-defined set of addresses, and it is essential to ensure that the communication address sent by the first device 200 exists within this set in order to determine the new communication address. Furthermore, during the search, if all communication addresses in the pre-defined set have a specific order, the search can be for the next communication address corresponding to the communication address sent by the first device 200, or a communication address separated by m units, to ensure that the new communication address is different from the communication address sent by the first device 200.

[0079] However, in some specific application scenarios, if the address management module 103 of multiple digital Hall ICs needs to determine a new communication address based on the communication address sent by the first device 200, then all the address management modules 103 of the digital Hall ICs should preferably search in the same way to ensure that the new communication addresses determined by all the address management modules 103 of the digital Hall ICs are different.

[0080] Alternatively, the address management module 103 may also be used to determine a new communication address based on a preset address change rule and the communication address sent by the first device 200.

[0081] The preset address change rule is used to characterize the change relationship between the new communication address and the communication address sent by the first device 200. After receiving the communication address sent by the first device 200, the address management module 103 determines a new communication address based on the preset address change rule.

[0082] For example, the communication address changes incrementally, with the new communication address being larger than the communication address sent by the first device 200. This could be achieved by adding n (n≥1) to the communication address sent by the first device 200; or by adding 1, 2, 3, ... It should be noted that the preset address change rule also needs to ensure that the new communication address is different from the communication address sent by the first device 200, and that when multiple digital Hall effect ICs are present, the new communication addresses determined by the address management module 103 of all digital Hall effect ICs are different.

[0083] The digital Hall IC provided in the above embodiments has the function of address allocation and management. It can determine the communication address of itself and the next-level device according to the received communication address. In actual use, when it is necessary to allocate the address of the device, it can be directly connected to the digital Hall IC, which is convenient for expanding the number of devices.

[0084] Based on the same inventive concept, this application also provides a detection system that uses the digital Hall effect IC mentioned in the above embodiments to solve the address allocation problem. Figure 4As shown, the detection system includes a main control unit 400 and N digital Hall ICs (Hall1 ~ Hall N), where N ≥ 2 and N is an integer; the digital Hall ICs include a first interface 101, a second interface 102 and an address management module 103, the address management module 103 is connected to the first interface 101 and the second interface 102, and the main control unit 400 includes a third interface 401.

[0085] The first interface 101 of the first digital Hall IC (Hall1) among N digital Hall ICs (Hall1~Hall N) is connected to the third interface 401, and the second interface 102 of the first N-1 digital Hall ICs (Hall1~Hall N-1) is connected to the first interface 101 of the next level digital Hall IC, forming an address management link between the N digital Hall ICs (Hall1~Hall N) and the main control unit 400.

[0086] The address management module 103 for N digital Hall ICs (Hall1 to Hall N) is used to configure communication addresses for the N digital Hall ICs (Hall1 to Hall N).

[0087] For the first digital Hall IC (Hall1), the main control unit 400 is the first device 200, and Hall2 is the second device 300. For Hall2 to Hall N-1, the previous-level digital Hall IC is the first device 200, and the next-level digital Hall IC is the second device 300. Hall1 to Hall N form a one-to-one serial structure through their respective first interface 101 and second interface 102. The second interface 102 of Hall N is not externally connected, thereby establishing an address management link with the main control unit 400, and allocating a communication address for each digital Hall IC to the next-level digital Hall IC.

[0088] For example, when the digital Hall IC configures the communication address sent by the first device 200 as the communication address of this digital Hall IC, the address management module 103 of Hall1 receives the communication address assigned by the main control unit 400. Then, the address management module 103 of Hall1 determines a new communication address and assigns it to Hall2. After the address management module 103 of Hall2 determines the communication address, it determines the next new communication address and assigns it to Hall3, and so on, determining all the communication addresses of Hall1 to Hall N.

[0089] For example, when a digital Hall IC configures its own newly determined communication address as its own communication address, the address management module 103 of Hall1 configures its own communication address, and then sends the communication address of Hall1 to Hall2. The address management module 103 of Hall2 determines a new communication address based on the received communication address, configures it as the communication address of Hall2, and sends the communication address of Hall2 to Hall3. The address management module 103 of Hall3 then configures the communication address of Hall3, and so on, to determine the communication addresses of all Hall1 to Hall N.

[0090] Specifically, the address management module 103 for the first digital Hall IC (Hall1) can determine the communication address of the first digital Hall IC (Hall1) based on the communication address assigned by the main control unit 400. For example, the communication address assigned by the main control unit 400 can be directly configured as the communication address of Hall1; or a new communication address can be determined as the communication address of Hall1 based on the default communication address assigned by the main control unit 400.

[0091] If the main control unit 400 does not support address allocation, the address management module 103 of the first digital Hall IC (Hall1) can also randomly generate a communication address for the first digital Hall IC (Hall1). Alternatively, the communication address of the first digital Hall IC (Hall1) can be determined based on an externally set address; the externally set address is determined by at least one of three methods: DIP switch, dry contact input signal, and software parameter setting.

[0092] In the above embodiments, the address management link adopts UART communication, which can be a UART communication method that boosts the TTL level.

[0093] In the detection system provided in the above embodiments, the address management module of the digital Hall IC is used to automatically allocate communication addresses when multiple digital Hall ICs need to be assigned communication addresses. In particular, when a new digital Hall IC is added, its superior digital Hall IC can assign a communication address to it without the need for the main control unit or background software, which is more convenient.

[0094] This application embodiment also provides an address allocation method, which is applied to a detection system. The detection system includes a main control unit 400 and N digital Hall ICs, where N≥2 and N is an integer. The digital Hall ICs include a first interface (101), a second interface (102), and an address management module (103). The address management module (103) is connected to the first interface (101) and the second interface (102). The main control unit 400 includes a third interface 401.

[0095] The first interface 101 of the first digital Hall IC in N digital Hall ICs is connected to the third interface 401, and the second interface 102 of the first N-1 digital Hall ICs is connected to the first interface 101 of the next-level digital Hall IC, forming an address management link between the N digital Hall ICs and the main control unit 400; the method is applied to the address management module (103) of the digital Hall ICs; the method includes:

[0096] Based on the communication address sent by the previous level digital Hall IC, determine the communication address of the current level digital Hall IC and the communication address to be sent to the next level digital Hall IC.

[0097] In one embodiment, determining the communication address of the current-level digital Hall IC based on the communication address sent by the previous-level digital Hall IC includes:

[0098] Configure the communication address sent by the previous level digital Hall IC as the communication address of the current level digital Hall IC.

[0099] In one embodiment, determining the communication address to be sent to the next-level digital Hall IC based on the communication address sent by the previous-level digital Hall IC includes:

[0100] A new communication address is determined based on the communication address sent by the previous level digital Hall IC;

[0101] The new communication address is sent to the next-level digital Hall IC.

[0102] In one embodiment, determining the communication address of the current-level digital Hall IC and the communication address to be sent to the next-level digital Hall IC based on the communication address sent by the previous-level digital Hall IC includes:

[0103] Based on the communication address sent by the previous level digital Hall IC, a new communication address is determined, and the new communication address is configured as the communication address of the current level digital Hall IC;

[0104] The new communication address is then sent to the communication address of the next-level digital Hall IC.

[0105] In one embodiment, determining a new communication address based on the communication address sent by the previous-level digital Hall IC includes:

[0106] The corresponding communication address sent by the previous level digital Hall IC is found in the preset address set and used as the new communication address; the preset address set includes multiple different communication addresses, and there is a mapping relationship between the multiple different addresses.

[0107] In one embodiment, determining a new communication address based on the communication address sent by the previous-level digital Hall IC includes:

[0108] Based on preset address change rules, the new communication address is determined according to the communication address sent by the previous level digital Hall IC.

[0109] In one embodiment, a preset address change rule is used to characterize an incremental change in the communication address.

[0110] In one embodiment, the method further includes:

[0111] The communication address of the first digital Hall IC is determined based on the communication address sent by the main control unit (400).

[0112] In one embodiment, the method further includes:

[0113] The communication address of the first digital Hall IC is randomly generated.

[0114] In one embodiment, the method further includes:

[0115] The communication address of the first digital Hall IC is determined based on the externally configured address;

[0116] The external setting address is determined by at least one of three methods: DIP switch, dry contact input signal, and software parameter setting.

[0117] The steps in the above methods and method embodiments are explained with reference to the explanation of the digital Hall IC and detection system described above, and will not be repeated here.

[0118] To facilitate understanding of the above method steps, in one embodiment, such as Figure 5 As shown, the method may include:

[0119] Step 501: Hall1 is assigned a starting communication address, and at the same time, the next address is generated for Hall 2 and sent to Hall 2 through the address management link;

[0120] Step 502: After Hall 2 obtains the communication address assigned by Hall 1, it saves this communication address as the communication address of this Hall, and at the same time generates a communication address for the next level digital Hall IC, namely Hall 3.

[0121] Steps 503 to 50n-1, and so on;

[0122] In step 50N, after Hall N obtains the communication address assigned by Hall N-1, it saves this communication address as the communication address of this Hall.

[0123] The method provided in the above embodiments can achieve automatic allocation of communication addresses.

[0124] In one application scenario, a high-voltage direct current (HVDC) system branch insulation monitoring system is provided to realize HVDC branch insulation monitoring. The HVDC system has N branches, and a digital Hall IC is installed on each branch. The digital Hall IC includes a first interface 101, a second interface 102, and an address management module 103. The first interface 101 of the first digital Hall IC among the N digital Hall ICs is connected to the third interface 401 of the main control unit 400. The second interfaces 102 of the first N-1 digital Hall ICs are connected to the first interface 101 of the next level digital Hall IC, forming an address management link between the N digital Hall ICs and the main control unit 400.

[0125] like Figure 6 As shown, both the digital Hall IC and the main control unit 400 include wiring terminals. The wiring terminals of the digital Hall IC are connected to the wiring terminals of the main control unit 400 to form a one-to-many master-slave structure and a communication link. The main control unit 400 completes communication with each digital Hall IC according to the communication address of each digital Hall IC. The communication address of the digital Hall IC adopts the above-mentioned automatic address allocation method.

[0126] Specifically, Hall 1 is responsible for allocating the starting address. Based on a pre-set convention, it assigns a starting communication address to its own Hall and simultaneously generates the next address for Hall 2, sending it to Hall 2 via the address management link. After obtaining the address assigned by Hall 1, Hall 2 saves this address as its own communication address and simultaneously generates a communication address for the next-level Hall, Hall 3. This process continues until the communication address allocation for all digital Halls on the link is completed.

[0127] For example, the initial communication address of Hall 1 is set to 1, and subsequent digital Halls increment by 1, with the communication address of the final Hall n being n. Meanwhile, the factory default communication address of a Hall is 0 to ensure it does not conflict with the assigned communication address; alternatively, other preset address allocation schemes can also be used.

[0128] The starting address of Hall 1 can be issued by the main control unit 400; alternatively, it can be specified as Hall 1 on the digital Hall via a DIP switch, dry contact input signal, software parameters, or other means. The digital Hall will then automatically allocate a preset starting address based on this information, thus completing the address allocation process even in scenarios where the main control unit does not support address allocation.

[0129] In the high-voltage DC system branch insulation monitoring system described in the above embodiments, the communication link uses RS485 communication; other master-slave communication links can also be used. The address management link uses UART communication with TTL level boost; other point-to-point communication links can also be used.

[0130] In addition, the main control unit 400 communicates with each digital Hall sensor through a preset address allocation scheme. Furthermore, the main control unit 400 can determine the abnormal operation of a certain Hall sensor in the link based on the communication status of each digital Hall sensor.

[0131] The methods and systems provided in the above embodiments achieve automated allocation of digital Hall communication addresses through an address management link, eliminating the need for manual intervention and simplifying the system configuration process. This is particularly suitable for application scenarios involving dozens of digital Hall sensors in high-voltage DC systems. Furthermore, the automatically allocated addresses are preset and can be associated with the physical location of the branches, simplifying the fault location and replacement process for digital Hall sensors.

[0132] Figure 7 A schematic diagram of the structure of the electronic device provided in this application. Figure 7 As shown, the electronic device 70 provided in this embodiment includes at least one processor 701 and a memory 702. Optionally, the device 70 further includes a communication component 703. The processor 701, memory 702, and communication component 703 are connected via a bus 704.

[0133] In a specific implementation, at least one processor 701 executes computer execution instructions stored in memory 702, causing at least one processor 701 to perform the above-described method.

[0134] The specific implementation process of processor 701 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0135] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.

[0136] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0137] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0138] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0139] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the above-described method.

[0140] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0141] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.

[0142] The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0143] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0144] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0145] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0146] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0147] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A digital Hall effect IC, characterized in that, The digital Hall IC (100) includes a first interface (101), a second interface (102), and an address management module (103). The address management module (103) is connected to the first device (200) through the first interface (101) and to the second device (300) through the second interface (102). The address management module (103) is used to determine a new communication address based on the communication address sent by the first device (200) and send the new communication address to the second device (300).

2. The digital Hall IC according to claim 1, characterized in that, The address management module (103) is also used to configure the communication address sent by the first device (200) as the communication address of the digital Hall IC.

3. The digital Hall IC according to claim 1, characterized in that, The address management module (103) is also used to configure the new communication address as the communication address of the digital Hall IC.

4. The digital Hall IC according to claim 1, characterized in that, The address management module (103) is also used to find the corresponding communication address of the communication address sent by the first device (200) in the preset address set, and use it as the new communication address; the preset address set includes multiple different communication addresses, and there is a mapping relationship between the multiple different communication addresses.

5. The digital Hall IC according to claim 1, characterized in that, The address management module (103) is also used to determine a new communication address based on the communication address sent by the first device (200) according to a preset address change rule.

6. The digital Hall IC according to claim 5, characterized in that, The preset address change rule is used to characterize the incremental change of the communication address.

7. A detection system, characterized in that, The detection system includes a main control unit (400) and N digital Hall ICs, where N ≥ 2 and N is an integer; each digital Hall IC includes a first interface (101), a second interface (102), and an address management module (103), wherein the address management module (103) is connected to the first interface (101) and the second interface (102), and the main control unit (400) includes a third interface (401); The first interface (101) of the first digital Hall IC among the N digital Hall ICs is connected to the third interface (401), and the second interface (102) of the first N-1 digital Hall ICs is connected to the first interface (101) of the next level digital Hall IC, thus forming an address management link between the N digital Hall ICs and the main control unit (400). The address management module (103) of the N digital Hall ICs is used to configure communication addresses for the N digital Hall ICs.

8. The detection system according to claim 7, characterized in that, The address management module (103) of the first digital Hall IC is also used to determine the communication address of the first digital Hall IC according to the communication address allocated by the main control unit (400).

9. The detection system according to claim 7, characterized in that, The address management module (103) of the first digital Hall IC is also used to randomly generate the communication address of the first digital Hall IC.

10. The detection system according to claim 7, characterized in that, The address management module (103) of the first digital Hall IC is also used to determine the communication address of the first digital Hall IC according to the externally set address; The external setting address is determined by at least one of three methods: DIP switch, dry contact input signal, and software parameter setting.

11. The detection system according to claim 7, characterized in that, The address management link uses UART communication.

12. An address allocation method, characterized in that, The method is applied to a detection system, which includes a main control unit (400) and N digital Hall ICs, where N≥2 and N is an integer; The digital Hall IC includes a first interface (101), a second interface (102), and an address management module (103). The address management module (103) is connected to the first interface (101) and the second interface (102). The main control unit (400) includes a third interface (401). The first interface (101) of the first digital Hall IC among the N digital Hall ICs is connected to the third interface (401), and the second interface (102) of the first N-1 digital Hall ICs is connected to the first interface (101) of the next level digital Hall IC, thus forming an address management link between the N digital Hall ICs and the main control unit (400). The method is applied to the address management module (103) of the digital Hall IC; the method includes: Based on the communication address sent by the previous level digital Hall IC, determine the communication address of the current level digital Hall IC and the communication address to be sent to the next level digital Hall IC.

13. The method according to claim 12, characterized in that, Determining the communication address of the current-level digital Hall IC based on the communication address sent by the previous-level digital Hall IC includes: Configure the communication address sent by the previous level digital Hall IC as the communication address of the current level digital Hall IC.

14. The method according to claim 13, characterized in that, The step of determining the communication address to be sent to the next-level digital Hall IC based on the communication address sent by the previous-level digital Hall IC includes: A new communication address is determined based on the communication address sent by the previous-level digital Hall IC; The new communication address is sent to the next-level digital Hall IC.

15. The method according to claim 12, characterized in that, The step of determining the communication address of the current-level digital Hall IC and the communication address to be sent to the next-level digital Hall IC based on the communication address sent by the previous-level digital Hall IC includes: Based on the communication address sent by the previous level digital Hall IC, a new communication address is determined, and the new communication address is configured as the communication address of the current level digital Hall IC; The new communication address is then sent to the communication address of the next-level digital Hall IC.

16. The method according to claim 14 or 15, characterized in that, The step of determining a new communication address based on the communication address sent by the previous-level digital Hall IC includes: The communication address corresponding to the communication address sent by the previous-level digital Hall IC is found in the preset address set and used as the new communication address; the preset address set includes multiple different communication addresses, and there is a mapping relationship between the multiple different communication addresses.

17. The method according to claim 14 or 15, characterized in that, The step of determining a new communication address based on the communication address sent by the previous-level digital Hall IC includes: Based on preset address change rules, a new communication address is determined according to the communication address sent by the previous-level digital Hall IC.

18. The method according to claim 17, characterized in that, The preset address change rule is used to characterize the incremental change of the communication address.

19. The method according to claim 12, characterized in that, The method further includes: The communication address of the first digital Hall IC is determined based on the communication address sent by the main control unit (400).

20. The method according to claim 12, characterized in that, The method further includes: The communication address of the first digital Hall IC is randomly generated.

21. The method according to claim 12, characterized in that, The method further includes: The communication address of the first digital Hall IC is determined based on the externally configured address; The external setting address is determined by at least one of three methods: DIP switch, dry contact input signal, and software parameter setting.

22. An electronic device, characterized in that, include: Memory, processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory, causing the processor to perform the method as described in any one of claims 12-21.

23. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 12-21.

24. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the method described in any one of claims 12-21.

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