Method for manufacturing an integrated circuit comprising at least one select transistor with a vertical gate and at least one deep trench capacitor, including a non-volatile memory cell.

Abstract

This disclosure relates to a method of manufacturing an integrated circuit including at least one select transistor with a vertical gate and at least one deep trench capacitor, comprising a non-volatile memory cell. The semiconductor substrate includes a first trench and a second trench. The first trench forms at least one element of a first electronic component, wherein the first electronic component extends from a substrate surface to a first depth. The second trench forms at least one element of a second electronic component, different from the first electronic component. The second electronic component extends from a substrate surface to a second depth. The ratio between the first depth and the second depth is greater than or equal to 1.1.

Description

Cross-reference to related applications

[0001] This application claims priority to French patent application No. FR2412890, filed on November 25, 2024, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0002] This description relates to semiconductor substrates and methods for forming deep trenches in semiconductor substrates.

[0003] This description relates particularly to the fabrication of an integrated circuit comprising at least one select transistor with a vertical gate of a non-volatile memory cell and at least one deep trench capacitor. The invention is particularly applicable to the co-integration of a non-volatile memory cell and a high-density deep trench capacitor. Background Technology

[0004] Deep trench structures are widely used because they offer density and improved performance when used in semiconductor devices.

[0005] The stage of forming deep trenches in the semiconductor substrate of integrated circuits can also be used to manufacture the vertical gate of buried vertical gate transistors, or to manufacture vertical capacitive elements in semiconductor substrates.

[0006] In known examples of manufacturing deep trench structures for vertical gates of transistors and for vertical capacitive elements, two different methods (one for the gate and another for the capacitor) are typically used due to the different optimized depths for the vertical gate and the vertical capacitive element. This approach also results in longer semiconductor component manufacturing times and higher costs due to the two separate methods.

[0007] Therefore, conventional techniques propose a common method for fabricating deep trench structures for vertical gates of transistors and for vertical capacitive elements. However, this common method produces trenches with the same depth for both the vertical components. This depth is typically chosen to meet the optimized performance requirements of either the vertical gate or the vertical capacitive element of the transistor. For example, deep trenches with an example depth of 600 nm to 1200 nm are etched to include both the vertical gate and the vertical capacitive element of the transistor. However, the same depth of the deep trenches cannot be optimized for both electronic components.

[0008] In practice, the depth of the trench accommodating the vertical gate affects the performance of buried transistors, making this specific depth difficult to modify. For example, buried vertical gate transistors are used in memory cells of non-volatile memory.

[0009] However, it is advantageous that vertical capacitive elements benefit from deeper trenches in order to increase the surface capacitance of the capacitive element. In other words, it is desirable to manufacture trenches for the electrodes of vertical capacitive elements that are deeper than the trenches of buried vertical gate transistors at a lower cost. Deep trenches can be coated with an electrically insulating material on their side surfaces and then filled with a conductive material.

[0010] Therefore, a unique method is needed to form trenches of different and optimized depths for each electronic component in different electronic components.

[0011] In addition, a method for manufacturing an integrated circuit is also needed, the integrated circuit including at least one select transistor with a vertical gate (preferably multiple select transistors with vertical gates) of a non-volatile memory cell and at least one deep trench capacitor (preferably multiple deep trench capacitors). Summary of the Invention

[0012] In one embodiment, a method for etching a semiconductor substrate or manufacturing an integrated circuit includes: forming a first etch-resistant mask on the surface of an assembly including at least one wafer of the semiconductor substrate, the first mask including at least one opening positioned toward a location to be formed in at least one first deep trench in the substrate, and the first mask forming a barrier facing a location to be formed in at least one second deep trench in the substrate; performing a first etch on the assembly to partially form the at least one first trench; at least partially removing the first mask and forming a second etch-resistant mask on the surface of the assembly, the second mask including a plurality of openings, at least one first opening of the plurality of openings positioned toward the partially formed first deep trench, and at least one second opening of the plurality of openings positioned toward a location to be formed in at least one second deep trench; and performing a second etch on the assembly to form the at least one first deep trench and the at least one second deep trench.

[0013] Therefore, a portion of the vertical gate of the non-volatile memory cell selection transistor and a deep trench capacitor can be obtained.

[0014] According to one embodiment, the method further includes the following sequential steps: performing ion implantation at the bottom of the first deep trench and the second deep trench in a semiconductor substrate to form a first implantation region and a second implantation region; depositing a dielectric layer on the sidewalls and bottom of the deep trench; and depositing a conductive material to fill the deep trench.

[0015] According to one embodiment, the method further includes the step of filling the first trench formed by the portion with a planarizing material, wherein the planarizing material is amorphous carbon or a spin-coated carbon composition.

[0016] According to another embodiment, the method further includes the steps of: removing at least a portion of the second mask from the surface of the component prior to the second etching step, and depositing dielectric and conductive materials in the first and second formed trenches.

[0017] Preferably, the conductive material is doped polycrystalline silicon.

[0018] According to one embodiment, the component further includes at least one of the following elements: a protective layer, such as an oxide layer; a second mask, such as a silicon-containing antireflective coating; an antireflective coating, such as a dielectric antireflective coating; a hard mask layer, such as an amorphous carbon layer; and a dielectric layer, such as a silicon nitride layer.

[0019] According to another aspect, a component includes an integrated circuit manufactured according to the method.

[0020] According to another aspect, a method for manufacturing an integrated circuit is provided, the integrated circuit including at least one selection transistor with a vertical gate of a non-volatile memory cell and at least one deep trench capacitor. The manufacturing method includes the steps of: forming a stacked structure on a semiconductor substrate, the stacked structure including a hard mask layer and a first mask covering the hard mask layer, the first mask resisting a first main etch, having an opening in a first region facing a first deep trench to be formed, and forming a barrier in a second region facing a second deep trench to be formed; performing a preliminary partial etch through the opening of the first mask, such that the opening penetrates the hard mask layer; removing the first mask; performing the first main etch through the opening to form a partial trench on the semiconductor substrate; and depositing a filler material to fill the partial trench. A second mask is formed on a hard mask layer, the second mask being resistant to a second main etch, having a first opening in a first region facing a portion of the trench on one side, and a second opening in a second region facing a second deep trench to be formed on the other side; an intermediate partial etch is performed through the first opening of the second mask, the first opening extending through the hard mask layer, and the filler material in a portion of the trench is removed, and an intermediate partial etch is performed through the second opening of the second mask, the second opening extending through the hard mask layer; a second main etch is performed through the first opening, thereby forming a first deep trench in the semiconductor substrate, and a second deep trench is formed in the substrate through the second opening.

[0021] The manufacturing method may include, after the second main etching step, performing an ion implantation step in the semiconductor substrate through the first and second openings of the hard mask layer, thereby forming a first doped region (implantation region) extending from the bottom surface of the first deep trench and a second doped region (implantation region) extending from the bottom surface of the second deep trench.

[0022] The manufacturing method may include, after the ion implantation step, forming an electrically insulating layer covering the sidewalls and bottom of the deep trench.

[0023] The manufacturing method may include a step of forming a conductive material (e.g., polycrystalline silicon) that fills the deep trench after the step of forming an electrically insulating layer.

[0024] The deep trenches formed in this way, along with the insulating layer and conductive material, can form the vertical gate of the select transistor for a non-volatile memory cell. The doped (implanted) region can form the source region (also known as the source implantation region) of the select transistor.

[0025] The resulting deep trench, along with the insulating layer and conductive material, forms part of a deep trench capacitor.

[0026] The manufacturing method may include, after the step of forming a conductive material, the steps of manufacturing a selection transistor for a non-volatile memory cell and manufacturing a deep trench capacitor.

[0027] The first set of deep trench capacitors can be manufactured simultaneously, the deep trenches of which have the same depth as the deep trenches forming the vertical gate of the select transistor.

[0028] A second set of deep trench capacitors can be manufactured simultaneously, wherein the deep trenches of the second set of deep trench capacitors have the same depth as the first set of deep trenches, but not the same depth.

[0029] According to another aspect, an assembly includes: at least one semiconductor substrate, the substrate including at least one first trench and at least one second trench disposed therein. The first trench includes at least one element of a first electronic component extending from a surface of the assembly at a first depth. The second trench includes at least one element of a second electronic component, different from the first electronic component. The second electronic component extends from the surface of the assembly at a second depth.

[0030] According to another aspect, an integrated circuit assembly is provided, comprising: at least one semiconductor substrate including at least one first deep trench and at least one second deep trench disposed therein and having different depths; each of the first and second deep trenches including an electrically insulating layer covering the sidewalls and bottom of the first and second deep trenches, and a conductive material filling the deep trenches; a first implantation region extending from the bottom of the first deep trench into the semiconductor substrate, and a second implantation region extending from the bottom of the second deep trench into the semiconductor substrate; the first deep trench forming part of an element of a first electronic component, and the second deep trench forming part of an element of a second electronic component different from the first electronic component, wherein the element of the first electronic component and the element of the second electronic component are selected from the vertical gate of a select transistor of a non-volatile memory cell and a portion of a deep trench capacitor.

[0031] The first deep trench and the second deep trench have a first depth and a second depth, respectively, wherein the ratio between the first depth and the second depth is eleven-tenths or greater, for example, between 1.1 and 2.

[0032] In one embodiment, the elements of the first electronic component are selection transistor elements of a non-volatile memory cell of the embedded select in trench memory (eSTM) type, and the elements of the second electronic component are elements of a deep trench capacitor.

[0033] In one embodiment, the first depth is between 330nm and 1200nm, and the second depth is between 300nm and 600nm.

[0034] The integrated circuit may include a first set of deep trench capacitors, the deep trenches of which have the same depth as the deep trenches forming the vertical gate of the select transistor.

[0035] The integrated circuit may include a second set of deep trench capacitors, the deep trenches of the second set of deep trench capacitors having the same depth as the first set of deep trenches. Attached Figure Description

[0036] Other advantages and features of the invention will become apparent from the detailed description of the non-limiting embodiments and implementations and from the accompanying drawings, wherein:

[0037] Figures 1A to 1I The steps in the manufacturing method are shown;

[0038] Figure 2 The results of filling at least one trench with a planarizing material are shown;

[0039] Figure 3A top view of the substrate after the deep trenches have been formed is shown;

[0040] Figure 4A It is a schematic diagram and a partial cross-sectional view of a non-volatile memory cell including at least one selection transistor with a vertical gate; and

[0041] Figure 4B This is a schematic diagram and a partial cross-sectional view of a high-density deep trench capacitor. Detailed Implementation

[0042] Now for reference Figures 1A to 1I It illustrates the steps in a deep trench manufacturing method.

[0043] Figure 1A Component 1, including a semiconductor substrate 2 wafer, is shown.

[0044] The method may involve manufacturing an integrated circuit including at least one non-volatile memory cell selection transistor (access transistor or buried transistor) with a vertical gate and at least one deep trench capacitor.

[0045] The integrated circuit preferably includes several select transistors with vertical gates and high-density deep trench capacitors. For clarity, only one deep trench of the select transistors and one deep trench of the capacitors are shown here.

[0046] In this example, component 1 includes at least a stack formed by arranging the following elements from bottom to top: a semiconductor substrate 2; a hard mask layer 12; and a first mask 10.

[0047] In this example, component 1 further includes a buffer layer 7 and a dielectric layer 13 positioned between the semiconductor substrate 2 and the hard mask layer 12. Component 1 may also include a protective layer 11 located between the hard mask layer 12 and the first mask 10.

[0048] The semiconductor substrate 2 is formed of silicon, for example, and includes a first region Z1 and a second region Z2.

[0049] According to one embodiment, the first region Z1 may be intended to include vertically structured capacitive elements in the substrate 2, and the second region Z2 may be intended to include non-volatile memory regions, for example, both of which are incorporated into an integrated circuit or a system-on-a-chip such as a microcontroller.

[0050] For example, the first region Z1 can be used to form the vertical gate of a non-volatile memory cell, and the second region Z2 can be used to form a deep trench capacitor.

[0051] The substrate 2 includes a front side, which corresponds to the surface of the substrate 2 from which electronic components will be manufactured. The front side may be covered with a conventional buffer oxide layer 7. For example, the buffer oxide layer 7 comprises silicon dioxide obtained by deposition or growth.

[0052] A dielectric layer 13, such as a nitride layer or a silicon nitride layer, can be deposited on the buffer oxide layer 7. The dielectric layer 13 can have a thickness, for example, between 60 nm and 100 nm. The dielectric layer 13 can be used as a hard mask during the etching of the substrate 2.

[0053] A hard mask layer 12, such as an amorphous carbon layer (α-C, alpha-C, or aC), can be deposited on the dielectric layer 13. The amorphous carbon can be obtained in the form of an advanced patterned film (APF). The hard mask layer 12 has a thickness, for example, between 380 nm and 460 nm (e.g., 420 nm).

[0054] The protective layer 11 can be formed on the hard mask layer 12 and includes silicon oxide with a thickness between 20 nm and 50 nm (e.g., 35 nm).

[0055] A first photosensitive resin mask 10 is formed on the protective layer 11. The thickness of the first mask 10 is, for example, between 50 nm and 150 nm, such as 100 nm. Conventional photolithography techniques can be used to deposit, mold, and remove the first photosensitive mask 10.

[0056] The layer 10 forming the first mask (e.g., made of photosensitive resin) covers the protective layer 11. Its opening 9 is located only in region Z1 facing the deep trench 3 to be formed. In contrast, in region Z2 facing the deep trench 4 to be formed, the mask 10 is continuous.

[0057] Each layer of the stacked structure covers the semiconductor substrate 2 in both region Z1 and region Z2.

[0058] In this example, the semiconductor substrate 2 includes a doped region NISO-1 covered by a doped region NISO-2.

[0059] The NISO region can be used as the turn-on (source) function of the select transistor for non-volatile memory cells, thus forming a common "source plane".

[0060] Figure 1B The result of the step of etching (preliminary etching) a pattern in the hard mask layer 12 (and through the protective layer 11) in the opening 9 of the first photosensitive resin mask 10, which is located in the first region Z1 and aligned with the location where a trench is formed in the region Z1 of the substrate.

[0061] The step of etching the pattern of the hard mask 12 selectively forms openings 9 in the hard mask 12 to etch the protective layer 11 and the hard mask layer 12, and also to prevent reaction with the dielectric layer 13. This selective etching is achieved, for example, by so-called "dry" or "drying" etching.

[0062] In other words, the first mask 10 has an opening 9 through which a dry etching step causes localized etching of the underlying layers 11 and 12, where the etching stops at the dielectric layer 13.

[0063] Figure 1C The result of the first etch G1 (also referred to herein as the first master etch) is shown. In this step, the first mask 10 and layer 11 are removed in a conventional manner.

[0064] For example, the first etch G1 of the "dry" type by reactive ion etching (RIE) can etch the silicon of the dielectric layer 13, buffer oxide layer 7 and substrate 2 with greater dynamic selectivity than in the hard mask layer 12.

[0065] Apply the first etch G1 to the above regarding Figure 1B The described structure forms at least one partial trench 15 in the first region Z1 of the substrate 2 and in the opening 9 of the hard mask 12.

[0066] The at least one portion of the trench 15 is etched to a depth P1 in the substrate 2 relative to the front side of the substrate 2.

[0067] In other words, during the main etching G1 through the opening 9 of the hard mask layer 12, the dielectric layer 13 and the buffer layer 7 are partially etched, and the opening 9 becomes a through opening. The main etching G1 causes partial etching of the substrate 2 facing the opening 9, thereby forming a partial trench 15 of depth P1 from the upper surface of the substrate 2.

[0068] Figure 1D The result of filling at least one portion of the trench 15 with planarizing material 23 is shown. For example, in a first embodiment, planarizing material 23 may be a dielectric, such as amorphous carbon.

[0069] In one embodiment, the planarizing material 23 fills a portion of the trench 15 until it reaches and exceeds the level of the surface of the hard mask layer 12. In another example of the embodiment, the planarizing material 23 does not completely fill the portion of the trench 15 and does not reach the upper surface of the hard mask layer 12.

[0070] In this first embodiment, the planarization material 23 is the same material as the hard mask layer 12.

[0071] In the second embodiment, the planarization material 23 is made of a different material than the hard mask layer 12.

[0072] In this regard, refer to Figure 2 . Figure 2 The result of filling at least one portion of the trench 15 with planarization material 24 according to the second embodiment is shown. For example, in the second embodiment, planarization material 24 may be a spin-on carbon (SOC) material. In this embodiment, planarization material 24 may also be deposited on a hard mask layer 12 present on dielectric layer 13.

[0073] In the second embodiment, planarizing material 24 fills part of the trench 15 and can also be deposited on the hard mask layer 12 to form a layer with a planar surface.

[0074] The anti-reflective coating 16 can be deposited on the hard mask layer 12 and on the planarization material 23. Figure 1E ); or deposited on the planarization material layer 24 ( Figure 2 It covers the underlying stack and has a flat top surface. The antireflective coating 16 can be, for example, a dielectric antireflective coating (DARC) mask structure or a silicon-containing antireflective coating (SiARC) material.

[0075] Now referencing matters related to Figure 1D The first embodiment described Figure 1E However, the following is about Figures 1E to 1I The described steps are similarly applied to... Figure 2 The second embodiment described.

[0076] Figure 1E The result of the step of depositing the second mask 17 on the anti-reflective coating 16 is shown. In another embodiment, in the absence of the anti-reflective coating 16, the second mask 17 is deposited directly on the hard mask layer 12 and on the planarization material 23. Figure 1E ); or deposited on the planarization material layer 24 ( Figure 2 The second mask 17 is a photosensitive resin layer, which in one embodiment resists the second etch G2 (see...). Figure 1G ).

[0077] The second resin mask 17 includes a first opening 18 in a first region Z1 (aligned with the position of a portion of the trench 15) and a second opening 19 in a second region Z2, the second opening 19 being aligned with the position where a trench will be formed in region Z21 of the substrate.

[0078] The first opening 18 is aligned with the at least one partial trench 15 formed by the first etching G1 (as mentioned above). Figure 1C As described above), and this portion of the trench 15 is filled with material by planarizing materials 23, 24 (as mentioned above). Figure 1D or Figure 2(as described).

[0079] The first opening 18 and the second opening 19 are positioned to define the second etching G2 (see...). Figure 1G The positions of the first deep trench 3 and the second deep trench 4 formed during the process are specified. The width of the second opening 18 is substantially equal to the width of the previously formed opening 9. In another embodiment, the width of the first opening 18 is approximately 5% to 10% wider than the width of the opening 9, which allows for better control over the depth and width of the trenches to be formed.

[0080] Figure 1F The results illustrate the steps of etching (also referred to herein as intermediate etching) a pattern in the hard mask layer 12 (and through the anti-reflective coating 16) in the first opening 18 in the first region Z1 and the second opening 19 in the second region Z2 of the second mask 17. Thus, in region Z1, at least a portion of the planarizing materials 23, 24 is removed from the partial trenches 15. In the second region Z2, the step of etching the pattern of the hard mask 12 is selectively defined by the second opening 19 to etch both the anti-reflective coating 16 and the hard mask layer 12, and also to react little or not at all with the dielectric layer 13.

[0081] Therefore, after the step of etching the pattern in the hard mask layer 12, component 1 includes a first opening 18 in the hard mask 12 (and anti-reflective coating 16) facing the partial trench 15 in the substrate 2, and a second opening 19 in the hard mask layer 12 (and anti-reflective coating 16). The partial trench 15 has a non-zero depth P1 in the substrate 2, which allows for etching in the same etching step G2 (see... Figure 1G During this period, deep trenches 3 and 4 with different depths are formed in substrate 2.

[0082] Figure 1G The result of a second etch G2 (also referred to herein as a second master etch) in substrate 2 is shown. The second etch G2 is capable of etching silicon so that a portion of trench 15 extends in the first opening 18 of hard mask 12. The second etch G2 is also capable of etching the buffer oxide layer 7, dielectric layer 13, and silicon of substrate 2 in the second opening 19 of hard mask 12.

[0083] In this respect, for example, the second etch G2 of the "dry" type by reactive ion etching is configured to dynamically etch the silicon of the dielectric layer 13, the buffer oxide layer 7 and the substrate 2 with much greater selectivity than in the hard mask layer 12.

[0084] After the second etching step G2, at least a portion of the hard mask 12 may also be etched such that the remaining thickness after the second etching step G2 is less than the initial thickness of the hard mask 12. In one embodiment, the second mask 17 has been removed in a conventional manner prior to the second etching step G2.

[0085] Therefore, a first deep trench 3 in the first opening 18 and a second deep trench 4 in the second opening 19 are formed. The first deep trench 3 has a first depth H1 greater than the depth P1 of the previously formed partial trench 15. The first depth H1 can be, for example, between 330 nm and 1200 nm, and the second deep trench 4 has a second depth H2, for example, between 300 nm and 600 nm. Preferably, the ratio "H1 / H2" between the first depth H1 and the second depth H2 is eleven-tenths or greater, for example, between 1.1 and 2.

[0086] The first deep trench 3 includes a width W1, for example, between 30 nm and 50 nm. The width W1 of the first deep trench is substantially equal to or greater than the width of the second deep trench 4. The widths of the deep trenches 3 and 4 are measured at half the corresponding depths H1 and H2 in the substrate 2.

[0087] Figure 1H The results of implanting dopant in the bottom of deep trenches 3 and 4 are shown. If substrate 2 is P-type, the implanted dopant can be N-type, or if substrate is N-type, the implanted dopant can be P-type.

[0088] Therefore, an implantation region 30 (doped region) is obtained extending from the bottom surface of the deep trench 3 into the substrate 2. This implantation region 30 can contact the underlying NISO-2 region.

[0089] A second implantation region 40 (doped region) is also obtained, extending from the bottom surface of the deep trench 4 into the substrate 2. This implantation region 40 can be separated from the underlying NISO-2 region.

[0090] The implantation regions 30 and 40 can be formed simultaneously in the same ion implantation step.

[0091] The hard mask layer 12 here forms an implantation mask, which enables local ion implantation.

[0092] In this example, the injection region 30 can form the source injection portion of the access transistor. Here, it is in contact with the NISO region (source plane). Alternatively, it can be spaced apart from the NISO region.

[0093] In this example, the injection area 40 is separated from the NISO area, but alternatively, it may also contact the NISO area.

[0094] Figure 1I The results show the formation of a dielectric layer 25, such as silicon dioxide, on the sides and bottom of the deep trenches 3 and 4.

[0095] Prior to this, the hard mask layer 12 is removed, exposing the upper surface of the dielectric layer 13.

[0096] A dielectric layer 25 is conformally deposited on this structure. It extends continuously over the upper surface of the dielectric layer 13 and into the deep trenches 3 and 4 (on the sidewalls and bottom surface).

[0097] After forming the dielectric layer 25, the volumes of the deep trenches 3 and 4 are filled with a conductive material 26 (e.g., doped polysilicon). The deep trenches 3 and 4 are filled with doped polysilicon until they protrude above the surface of the hard mask layer 12.

[0098] Excess conductive material 26 protruding above dielectric layer 13 is typically removed by chemical mechanical polishing until it reaches dielectric layer 13, which acts as a barrier layer.

[0099] Therefore, a first electronic component 5 is formed in the first deep trench 3, and a second electronic component 6 is formed in the second deep trench 4.

[0100] In summary, the deep trench etching method described above enables the fabrication of an assembly 1 comprising at least one semiconductor substrate, the semiconductor substrate including at least one first deep trench 3 and at least one second deep trench 4 formed within a substrate 2. The first deep trench 3 forms at least one element of a first electronic component 5, the first electronic component 5 extending from the surface of the assembly 1 at a first depth H1. The second deep trench 4 includes at least one element of a second electronic component 6, distinct from the first electronic component 5. The second electronic component 6 extends from the surface of the assembly 1 at a second depth H2. The ratio between the first depth H1 and the second depth H2 is eleven-tenths or greater, for example, between 1.1 and 2.

[0101] The elements of the first electronic component 5 may be elements of a deep trench capacitor, and the elements of the second electronic component 6 may be vertical gates of selection transistors for non-volatile memory cells of the embedded trench select memory (eSTM) type. The vertical gate select transistor may be the same as or similar to the transistors described in U.S. Patent Application Publication Nos. 2025 / 185242 A1 and 2025 / 240953 A1 (both documents are incorporated herein by reference in their entirety).

[0102] “eSTM” non-volatile memory cells typically include a state transistor connected in series with a select transistor (also known as a selector, access transistor, or buried transistor). The state transistor includes a control gate and a floating gate, which is capable of storing charges representing binary data items in the floating gate.

[0103] A matrix organization of word lines connected to the vertical gate of the select transistor, control gate lines connected to the control gate, bit lines connected to the drain of the state transistor, and source lines or planes connected to the source of the select transistor (called a memory plane); enables the reading, erasing, and programming access of memory cells in the decode memory plane.

[0104] Before or after forming deep trenches 3 and 4, NISO-1 and NISO-2 regions are deeply implanted in semiconductor substrate 2. The NISO-1 deep implanted region, with a dopant type opposite to that of substrate 2, can provide the function of the conductive region (source) of the memory cell selection transistor belonging to a common "source plane".

[0105] Figure 3 A top view of the substrate 2 after the formation of deep trenches 3 and 4 is shown. Trenches 3 and 4, located in regions Z1 and Z2 respectively, can be formed at positions in different vertical planes. In other words, trenches 3 and 4 can be misaligned, that is, offset relative to each other.

[0106] The manufacturing method may include the steps of completing one or more vertical gate selection transistors and one or more deep trench capacitors.

[0107] Figure 4A This is a schematic diagram and a partial cross-sectional view of two memory cells CEL1 and CEL2 according to one embodiment.

[0108] Each memory cell CEL1 and CEL2 includes a state transistor TE and an access transistor TA. The state transistor TE can store charges representing binary data in its floating gate FG, and the access transistor TA can selectively access the memory cell for operations such as writing and reading.

[0109] To access memory cells CEL1 and CEL2, the drain region D of the state transistor TE is coupled to bit lines BL1 and BL2, while the source region 5 (source injection section) of the access transistor TA is coupled to the NISO region (source plane) below.

[0110] The vertical gate of the access transistor TA is formed by a deep trench 3, which includes an electrically insulating layer 25 and a conductive material 26.

[0111] Source region 5 extends from the bottom of the vertical gate to the NISO source plane.

[0112] In this example, source region 5 reaches the NISO source plane, but alternatively, it can also be spaced apart from the NISO source plane. As shown in U.S. Patent Publications 2025 / 185242A1 and 2025 / 240953A1, both of which are incorporated herein by reference in their entirety.

[0113] Figure 4B This is a schematic diagram and a partial cross-sectional view of a high-density deep trench capacitor.

[0114] A portion of the capacitor is formed by a corresponding deep trench 4, which includes an electrically insulating layer 25 and a conductive material 26.

[0115] Conductive material 26 (e.g., made of doped polycrystalline silicon) is coupled to a first layer P1, which forms a common upper electrode capable of achieving common bias.

[0116] Layer P2 is located above and electrically insulated from layer P1. This layer can be a dedicated layer for non-volatile memory. It is electrically coupled to a metal contact located on the doped region (here, an N-type doped region, i.e., an N+ region), which can bias the buried N-well layer Nw of substrate 2 (here, an N-type doped layer).

[0117] The voltage V1 applied to the P1 layer can bias the deep trench 4, and the voltage V2 applied to the P2 layer can bias the N-well Nw.

[0118] Obviously, other configurations are also possible in terms of conductivity type, arrangement, and trench depth. The trench 4 of the capacitor can be deeper or shallower than the trench 3 that forms the vertical gate of the transistor TA.

[0119] Therefore, thanks to this method of forming deep trenches of different depths, it is possible to simultaneously manufacture deep trenches optimized for memory cells, and at the same time, to manufacture deeper or shallower high-density capacitor trenches.

Claims

1. A method for manufacturing an integrated circuit, comprising: A first mask resistant to a first etch is formed on the surface of an assembly including at least one wafer of the semiconductor substrate, the first mask including at least one opening facing a location where at least one first deep trench will be formed in the substrate, and wherein the first mask forms a barrier facing a location where at least one second deep trench will be formed in the substrate. The component is first etched using the first mask to partially form the at least one first deep trench; The first mask is at least partially removed and a second mask resistant to second etch is formed on the surface of the component. The second mask includes a plurality of openings, including at least one first opening positioned toward the location of the partially formed first deep trench and at least one second opening positioned toward the location where the at least one second deep trench will be formed. The component is etched using the second mask to form at least one first deep trench and at least one second deep trench to different depths in the component; Ions are implanted at the bottom of the first deep trench and the second deep trench in the semiconductor substrate to form a first implantation region and a second implantation region; A dielectric layer is deposited on the bottom and sidewalls of the deep trench; as well as The deep trench is filled with a deposited conductive material; This allows us to obtain the vertical gate of the selection transistor for the non-volatile memory cell and a portion of the deep trench capacitor.

2. The method of claim 1, further comprising filling the partially formed first deep trench with a planarizing material.

3. The method of claim 2, wherein the planarizing material is selected from the group consisting of amorphous carbon or spin-coated carbon compositions.

4. The method according to claim 1, further comprising: After the second etching, at least a portion of the second mask is removed from the surface of the component; as well as Dielectric and conductive materials are deposited in the first and second deep trenches.

5. The method according to claim 4, wherein the conductive material is doped polycrystalline silicon.

6. The method of claim 1, wherein the component further comprises at least one element selected from the following: A protective layer made of oxides; A second mask made of a silicon-containing anti-reflective coating; Antireflective coating made of dielectric antireflective coating; Hard mask layer made of amorphous carbon layer; A dielectric layer made of silicon nitride.

7. The method according to claim 1, comprising the following steps: The forming step includes depositing a hard mask layer on the substrate and depositing a first mask covering the hard mask layer; Prior to the first etching, a preliminary local etching is performed on the hard mask layer through the opening of the first mask, such that the opening extends through the hard mask layer; Then, remove the first mask; Then, the first etching is performed through the opening to form a partial trench in the semiconductor substrate; Then, the deposited filler material fills the portion of the trench. Then, a second mask is formed on the hard mask layer; Intermediate partial etching is performed through the first opening of the second mask, the first opening extending through the hard mask layer, and the filler material is removed from the partial trench; and intermediate partial etching is performed through the second opening of the second mask, such that the second opening extends through the hard mask layer. The second etching is performed through the first opening of the second mask to form the deep trench, and the second etching is performed through the second opening of the second mask to form the deep trench.

8. The method of claim 1, wherein a first set of deep trench capacitors is simultaneously manufactured, the deep trenches of the first set having the same depth as the deep trenches forming the vertical gate of the select transistor.

9. The method of claim 1, wherein the second group of deep trench capacitors is manufactured simultaneously, the deep trenches of the second group having the same depth as the deep trenches of the first group.

10. An integrated circuit according to the method of claim 1.

11. An integrated circuit, comprising: At least one semiconductor substrate, including at least one first trench and at least one second trench disposed within the substrate; The first trench includes at least one element of a first electronic component, the first electronic component extending from the surface of the component to a first depth; The second trench includes at least one element of a second electronic component that is different from the first electronic component, the second electronic component extending from the surface of the component to a second depth; The ratio between the first depth and the second depth is greater than or equal to 1.

1.

12. The integrated circuit of claim 11, wherein the element of the first electronic component is a selection transistor for a non-volatile memory cell, and the element of the second electronic component is an element of a deep trench capacitor.

13. The integrated circuit of claim 11, wherein the first depth is between 330 nm and 1200 nm, and the second depth is between 300 nm and 600 nm.

14. An integrated circuit, comprising: A semiconductor substrate, including a first deep trench and a second deep trench disposed within the semiconductor substrate and having different depths; The first deep trench and the second deep trench each include an electrically insulating layer covering the sidewalls and bottom of the first deep trench and the second deep trench, and a conductive material filling the first deep trench and the second deep trench; A first injection region extends from the bottom of the first deep trench into the semiconductor substrate; And a second injection region extending from the bottom of the second deep trench into the semiconductor substrate; The first deep trench forms part of an element of a first electronic component, and the second deep trench forms part of an element of a second electronic component that is different from the first electronic component; The elements of the first electronic component and the elements of the second electronic component are selected from the vertical gate of the select transistor of the non-volatile memory cell and a portion of the deep trench capacitor.

15. The integrated circuit of claim 14, further comprising a first set of deep trench capacitors having deep trenches, the deep trenches of the first set of deep trench capacitors having the same depth as the deep trenches forming the vertical gate of the select transistor.

16. The integrated circuit of claim 15, further comprising a second set of deep trench capacitors, the second set of deep trench capacitors having deep trenches, the deep trenches of the second set of deep trench capacitors having the same depth as the deep trenches of the first set of deep trench capacitors.

Images