MOS devices with deep trench superjunctions and their fabrication methods
By forming a sacrificial layer and covering it with a second hard mask layer before repairing interface damage in deep trenches, the problem of N+ pre-contamination caused by silicon nitride warpage is solved, the doping concentration and charge matching of the P-type pillar region are improved, and the performance of superjunction devices is enhanced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI HUAHONG GRACE SEMICON MFG CORP
- Filing Date
- 2026-02-27
- Publication Date
- 2026-05-26
AI Technical Summary
Increased silicon nitride warpage leads to increased exposure and contamination risk during N+ fronting, affecting doping concentration and charge matching in the P-type pillar region and impacting the performance of superjunction devices.
By forming a sacrificial layer and covering a second hard mask layer before repairing damage to the sidewall and bottomwall interfaces of the deep trench, warping of the first hard mask layer is avoided. Then, the etch-back process and epitaxial process are performed to ensure that the formation of the deep trench superjunction is not affected by silicon nitride warping.
It effectively prevents the risk of source region contamination, improves the doping concentration and charge matching of the P-type pillar region, and enhances the performance of superjunction devices.
Smart Images
Figure CN122094150A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to a MOS device with a deep trench superjunction and its manufacturing method. Background Technology
[0002] Superjunction (SJ) technology is a core technology in the field of high-voltage power metal-oxide-semiconductor field-effect transistors (MOSFETs). Its basic principle is to create alternating P-type and N-type pillar regions in the drift region of the device, ensuring that the charges in these two types of pillar regions can mutually deplete each other when the device is off. This significantly increases the doping concentration in the drift region without reducing the device's breakdown voltage (BV), thereby significantly reducing the device's on-resistance.
[0003] To fabricate superjunction structures, the industry commonly employs deep trench (DT) etching technology. A typical manufacturing method involves first growing an N-type epitaxial layer as a drift region, then etching a deep trench within the N-type epitaxial layer, and finally filling the trench with a P-type semiconductor material as a P-type pillar region. This, together with the N-type epitaxial layer (i.e., the N-type pillar region) between the trenches, forms a superjunction.
[0004] Typically, the P-type pillar region is formed first, followed by the gate and source regions. However, during source region heat treatment, at high temperatures (typically >900℃, rapid thermal annealing (RTA) can reach 1050~1150℃), the lattice diffusion coefficient of boron atoms increases significantly, causing them to diffuse from the P-type pillar region to the N-type pillar region, resulting in a decrease in the effective doping concentration of the P-type pillar region. If the annealing time is too long, the outward diffusion of boron will intensify, and may even lead to a decrease in the punch-through voltage of the P-type pillar region (such as an increase in the source-drain punch-through risk of MOSFETs). Therefore, the step of forming the source region is moved forward (N+ forward), that is, the gate and source regions are formed first, followed by the deep trench P-type pillar region.
[0005] Figure 1 This is a SEM image of a MOS device with a deep trench superjunction and silicon nitride warping in the prior art. After photolithography and etching of the deep trench, the silicon nitride is first wet-etched with a pull-back, then the top TEOS residue is removed, and then sacrificial oxidation is performed to repair the sidewalls. However, due to the large thermal expansion coefficient of silicon nitride, the sacrificial oxidation will cause the silicon nitride to warp by 10°, resulting in N+ exposure and contamination of the P-type pillar region.
[0006] The performance of a superjunction is closely related to its charge-matching state. However, silicon nitride warpage exacerbates the risk of exposure contamination when N+ is fronted, directly affecting the doping concentration of the P-type pillar region and thus the charge-matching state. Preventing N+ exposure contamination is an important goal to ensure the performance of superjunction devices. Summary of the Invention
[0007] The purpose of this invention is to provide a MOS device with a deep trench superjunction and its manufacturing method, so as to solve the problem of increased exposure and contamination risk when silicon nitride warping exacerbates N+ front-mounting.
[0008] To solve the above-mentioned technical problems, the present invention provides a method for manufacturing a MOS device with a deep trench superjunction, comprising:
[0009] A substrate is provided on which a first epitaxial layer, a well region, a first hard mask layer and a second hard mask layer are sequentially formed, and a gate and source regions located on both sides of the gate are formed in the well region.
[0010] A deep trench is formed, which sequentially penetrates the second hard mask layer, the first hard mask layer and the well region, and extends into the first epitaxial layer. The sidewalls and bottom walls of the deep trench have interface damage.
[0011] Repair the interface damage of the sidewalls and bottomwalls of the deep trench, and the width of the deep trench located in the well region is greater than the width of the deep trench located in the first hard mask layer;
[0012] Perform a back etching process to etch the first hard mask layer so that the sidewalls of the deep trenches located in the first hard mask layer are flush with the sidewalls of the deep trenches located in the well region.
[0013] An epitaxial process is performed to fill the deep trench with a second epitaxial layer. The first epitaxial layer and the second epitaxial layer have different doping types, and the first epitaxial layer and the second epitaxial layer constitute a deep trench superjunction.
[0014] Optionally, the step of repairing the interface damage between the bottom wall and sidewalls of the deep trench includes:
[0015] A sacrificial layer is formed, which is located on the bottom and sidewalls of the deep trench;
[0016] Remove the sacrificial layer from the bottom and sidewalls of the deep trench to repair the interface damage to the bottom and sidewalls of the deep trench.
[0017] Optionally, the sacrificial layer is made of silicon oxide, the first epitaxial layer is made of silicon, and the bottom and sidewalls of the deep trench are oxidized into the sacrificial layer using a thermal oxidation process.
[0018] Optionally, the material of the second hard mask layer is silicon oxide, and when removing the sacrificial layer of the bottom wall and sidewall of the deep trench, a portion of the second hard mask layer is also removed.
[0019] Optionally, a wet etching process can be used to remove the sacrificial layer and part of the second hard mask layer from the bottom and sidewalls of the deep trench.
[0020] Optionally, after performing the etch-back process and before performing the epitaxial process, the method further includes: removing the second hard mask layer.
[0021] Optionally, the first epitaxial layer and the substrate have the same doping type, while the second epitaxial layer and the substrate have different doping types.
[0022] Optionally, the material of the first hard mask layer is silicon nitride.
[0023] Optionally, the etching process is a wet etching process.
[0024] Based on the same inventive concept, the present invention also provides a MOS device with a deep trench superjunction, which is prepared by the manufacturing method of the MOS device with a deep trench superjunction described in any of the above claims.
[0025] In a method for manufacturing a MOS device with a deep trench superjunction provided by the present invention, a first epitaxial layer, a well region, a first hard mask layer, and a second hard mask layer are sequentially formed on a substrate, and a gate and source regions located on both sides of the gate are formed in the well region; then a deep trench is formed, the deep trench sequentially penetrating the second hard mask layer, the first hard mask layer, and the well region, and extending into the first epitaxial layer, and interface damage is formed on the sidewalls and bottom wall of the deep trench; the interface damage on the sidewalls and bottom wall of the deep trench is repaired, and the width of the deep trench located in the well region is greater than that of the first hard mask layer. The deep trench width of the hard mask layer; in the step of repairing the interface damage of the sidewalls and bottom walls of the deep trench, a second hard mask layer is protected on the first hard mask layer to prevent warping of the first hard mask layer; then, a back etching process is performed to etch the first hard mask layer so that the sidewalls of the deep trench located on the first hard mask layer are flush with the sidewalls of the deep trench located in the well region; then, an epitaxial process is performed to fill the deep trench with a second epitaxial layer. The first and second epitaxial layers have different doping types, and the first and second epitaxial layers form a deep trench superjunction. In this way, by prioritizing the step of repairing the interface damage of the sidewalls and bottom walls of the deep trench, warping of the first hard mask layer is avoided, thereby preventing the risk of contamination in the source region. Attached Figure Description
[0026] Figure 1 This is a SEM image of a silicon nitride warped MOS device with a deep trench superjunction in the prior art.
[0027] Figure 2 This is a flowchart of a method for manufacturing a MOS device with a deep trench superjunction according to an embodiment of the present invention.
[0028] Figures 3 to 8 This is a schematic diagram showing the structural steps corresponding to the manufacturing method of a MOS device with a deep trench superjunction according to an embodiment of the present invention. Wherein:
[0029] Figure 3 This is a schematic diagram of the structure of the MOS device after forming a deep trench according to an embodiment of the present invention.
[0030] Figure 4 This is a schematic diagram of the structure of the MOS device after the formation of the sacrificial layer according to an embodiment of the present invention.
[0031] Figure 5 This is a schematic diagram of the structure of the MOS device after removing the sacrificial layer according to an embodiment of the present invention.
[0032] Figure 6 This is a schematic diagram of the structure of the MOS device after the first hard mask layer is etched back according to an embodiment of the present invention.
[0033] Figure 7 This is a schematic diagram of the structure of the MOS device after removing the second hard mask layer according to an embodiment of the present invention.
[0034] Figure 8 This is a schematic diagram of the structure of a MOS device after forming a deep trench superjunction according to an embodiment of the present invention.
[0035] Figure 9 This is a SEM image of a MOS device with a deep trench superjunction that improves silicon nitride warpage according to an embodiment of the present invention.
[0036] In the picture:
[0037] 10-Silicon nitride warpage;
[0038] 20-Substrate; 21-First epitaxial layer; 22-Well region; 23-Gate; 24-Source region; 25-First hard mask layer; 26-Second hard mask layer; 27-Deep trench; 27a-Second epitaxial layer; 28-Sacrificial layer. Detailed Implementation
[0039] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a more detailed account of the MOS device with a deep trench superjunction and its manufacturing method. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise scales, used only to facilitate and clarify the illustration of the embodiments of the present invention. Furthermore, the structures shown in the drawings are often part of the actual structure. In particular, different figures may emphasize different aspects and sometimes use different scales.
[0040] Figure 2 This is a flowchart illustrating a method for manufacturing a MOS device with a deep trench superjunction according to an embodiment of the present invention. Figure 2 As shown, this embodiment of the invention provides a method for manufacturing a MOS device with a deep trench superjunction, comprising:
[0041] Step S10: A substrate is provided, on which a first epitaxial layer, a well region, a first hard mask layer and a second hard mask layer are sequentially formed, and a gate and source regions located on both sides of the gate are formed in the well region.
[0042] Step S20: A deep trench is formed, which sequentially penetrates the second hard mask layer, the first hard mask layer and the well region, and extends into the first epitaxial layer. Interface damage is formed on the sidewalls and bottom wall of the deep trench.
[0043] Step S30: Repair the interface damage of the sidewall and bottom wall of the deep trench, and the width of the deep trench located in the well region is greater than the width of the deep trench located in the first hard mask layer.
[0044] Step S40: Perform a back etching process to etch the first hard mask layer so that the sidewalls of the deep trenches located in the first hard mask layer are flush with the sidewalls of the deep trenches located in the well region.
[0045] Step S50: Perform an epitaxial process to fill the deep trench with a second epitaxial layer. The first epitaxial layer and the second epitaxial layer have different doping types. The first epitaxial layer and the second epitaxial layer constitute a deep trench superjunction.
[0046] Figures 3 to 8 This is a schematic diagram showing the manufacturing steps of a MOS device with a deep trench superjunction according to an embodiment of the present invention. To make the above-mentioned objectives, features, and beneficial effects of the present invention more apparent and understandable, the following description is provided in conjunction with the appendix to the specification. Figures 3 to 8 Specific embodiments of the present invention will be described in detail below.
[0047] Figure 3 This is a schematic diagram of the structure of a MOS device after forming a deep trench according to an embodiment of the present invention. (Combined with...) Figure 3 Steps S10 and S20 will be described in detail. Figure 3 As shown, a substrate 20 is provided. Substrate 20 provides an operating platform for subsequent processes. It can be any substrate known to those skilled in the art for supporting semiconductor integrated circuit components, such as a bare die or a wafer processed by epitaxial growth. Specifically, substrate 20 is, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a germanium substrate, a germanium-silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate, etc. In this embodiment, substrate 20 is a silicon substrate. The doping type of substrate 20 is a first doping type. In this embodiment, the first doping type is, for example, N-type; in other embodiments, the first doping type can also be P-type.
[0048] Please continue to refer to this. Figure 3 A first epitaxial layer 21, a well region 22, a first hard mask layer 25, and a second hard mask layer 26 are sequentially formed on the substrate 20. A gate 23 and source regions 24 located on both sides of the gate 23 are formed within the well region 22. The gate 23 penetrates the well region 22 and extends into the first epitaxial layer 21. The first epitaxial layer 21 is doped with a first doping type, i.e., N-type. The well region 22 is doped with a second doping type, such as P-type, i.e., the well region 22 is a P-well. The source region 24 is doped with a first doping type, i.e., N-type, and the doping concentration of the source region 24 is relatively high. Therefore, the formation step of the source region 24 is an N+ formation step. The formation of source region 24 typically involves first performing an ion implantation process to dope the source region, followed by a heat treatment process to activate the doped ions and repair damage. The heat treatment process temperature is typically between 800°C and 1100°C. In existing technologies, a P-type pillar region is formed first, followed by the source region. However, during the heat treatment process for forming the source region, the P-type pillar region is subjected to high temperatures, causing it to diffuse into the N-type pillar region, resulting in a decrease in the effective doping concentration of the P-type pillar region and even a decrease in its punch-through voltage. In this embodiment, forming source region 24 first is referred to as the N+ step pre-process. The N+ step pre-process reduces one thermal step in the subsequently formed P-type pillar region, thereby increasing the punch-through voltage of the P-type pillar region.
[0049] Please continue to refer to this. Figure 3 A deep trench 27 is formed, which sequentially penetrates the second hard mask layer 26, the first hard mask layer 25, and the well region 22, and extends into the first epitaxial layer 21. The depth of the deep trench 27 exceeds half the thickness of the first epitaxial layer 21. In this embodiment, the depth of the deep trench 27 in the first epitaxial layer 21 is, for example, 80% to 90% of the thickness of the first epitaxial layer 21. The deep trench 24 is formed using a dry etching process. The dry etching process affects the silicon interface, that is, the sidewalls and bottom walls of the deep trench 27 have interface damage, which is not conducive to the subsequent filling of the P-type pillar region.
[0050] Figure 4 This is a schematic diagram of the structure of the MOS device after the formation of the sacrificial layer according to an embodiment of the present invention. Figure 5 This is a schematic diagram of the MOS device structure after removing the sacrificial layer according to an embodiment of the present invention. (Combined with...) Figure 4 and Figure 5 Step S30 will be described in detail. For example... Figure 4 and Figure 5 As shown, the interface damage between the sidewalls and bottom wall of the deep trench 27 is repaired, and the width of the deep trench located in the well region 22 is greater than the width of the deep trench located in the first hard mask layer 25. Exemplarily, the steps for repairing the interface damage between the bottom wall and sidewalls of the deep trench 27 include: as... Figure 4As shown, a sacrificial layer 28 is formed, located on the bottom and sidewalls of the deep trench 27. The material of the sacrificial layer 28 is, for example, silicon oxide, while the material of the first epitaxial layer 21 is silicon. A thermal oxidation process is used to oxidize the silicon with interface damage on the bottom and sidewalls of the deep trench into silicon oxide, i.e., the sacrificial layer 28. The process temperature range of the thermal oxidation process is, for example, 800~1200℃. In the prior art, the second hard mask layer is removed first, and then the sacrificial layer is formed. During the formation of the sacrificial layer, due to the large coefficient of thermal expansion of silicon nitride (the first hard mask layer), and the absence of a second hard mask layer covering the first hard mask layer, the oxidation temperature of the thermal oxidation process can cause the silicon nitride (the first hard mask layer) to warp. In this embodiment, the sacrificial layer is placed first. During the formation of the sacrificial layer, the first hard mask layer is covered by a second hard mask layer. The second hard mask layer protects the first hard mask layer, preventing warping and thus avoiding the risk of source region exposure and contamination. Figure 5 As shown, the sacrificial layer 28 of the bottom and sidewalls of the deep trench 27 is removed. A wet etching process is used to remove the sacrificial layer 28 of the bottom and sidewalls of the deep trench. The solution used in the wet etching process is, for example, hydrofluoric acid. The material of the second hard mask layer 26 is, for example, silicon oxide; therefore, when removing the sacrificial layer 28 of the bottom and sidewalls of the deep trench 27, a portion of the second hard mask layer 26 is also removed. Therefore, after repairing the interface damage of the sidewalls and bottom of the deep trench 27, the width of the deep trench located in the well region 22 is greater than the width of the deep trench located in the first hard mask layer 25, meaning that the first hard mask layer 25 protrudes into the deep trench.
[0051] Figure 6 This is a schematic diagram of the structure of the MOS device after etching back the first hard mask layer according to an embodiment of the present invention. Combined with... Figure 6 Step S40 will be described in detail. For example... Figure 6 As shown, a back etching process is performed to etch the first hard mask layer 25 so that the sidewalls of the deep trenches located in the first hard mask layer 25 are flush with the sidewalls of the deep trenches located in the well region 22. The material of the first hard mask layer 25 is silicon nitride. The back etching process is a wet etching process, and the etching solution for the wet etching process is, for example, phosphoric acid.
[0052] Figure 7 This is a schematic diagram of the structure of a MOS device after removing the second hard mask layer according to an embodiment of the present invention. After performing the etch-back process and before performing the epitaxial process, the method further includes: removing the second hard mask layer. The second hard mask layer is removed using a wet etching process, and the solution used in the wet etching process is, for example, hydrofluoric acid.
[0053] Figure 8 This is a schematic diagram of the structure of a MOS device after forming a deep trench superjunction according to an embodiment of the present invention. (Combined with...) Figure 8 Step S50 will be described in detail. For example... Figure 8As shown, an epitaxial process is performed to fill the deep trench 27 with a second epitaxial layer 27a. The first epitaxial layer 21 and the second epitaxial layer 27a have different doping types. The first epitaxial layer 21 is doped with the first doping type, and the second epitaxial layer 27a is doped with the second doping type. That is, the first epitaxial layer 21 is doped with N-type, also known as an N-type pillar region, and the second epitaxial layer 27a is doped with P-type, also known as a P-type pillar region. The first epitaxial layer 21 and the second epitaxial layer 27a constitute a deep trench superjunction.
[0054] Please continue to refer to this. Figure 8 This invention also provides a MOS device with a deep trench superjunction, fabricated using the manufacturing method of the MOS device with a deep trench superjunction described in any one of the above embodiments, comprising:
[0055] Substrate 20, the doping type of substrate 20 is the first doping type;
[0056] The first epitaxial layer 21 is located on the substrate 20, and the doping type of the first epitaxial layer 21 is the first doping type.
[0057] Well region 22 is located on the first epitaxial layer 21, and the doping type of well region 22 is the second doping type;
[0058] Gate 23 penetrates the well region 22 and extends into the first epitaxial layer;
[0059] Source region 24 is located within the well region 22 on both sides of gate 23;
[0060] The first hard mask layer 25 is located on the well region 22 and covers the gate 23 and the source region 24;
[0061] The deep trenches sequentially penetrate the first hard mask layer 25 and the well region 22, and extend into the first epitaxial layer 21;
[0062] The second epitaxial layer 27a fills the deep trench and is in direct contact with the first epitaxial layer 21. The first epitaxial layer 21 and the second epitaxial layer 27a have different doping types. The first epitaxial layer 21 and the second epitaxial layer 27a constitute a deep trench superjunction.
[0063] Figure 9This is a SEM image of a MOS device with a deep trench superjunction that improves silicon nitride warpage according to an embodiment of the present invention. This embodiment reduces the primary thermal process in the P-type pillar region and increases the punch-through voltage of the P-type pillar region by forming the source region 22 first and then forming the deep trench superjunction. Furthermore, this embodiment avoids warping of the first mask layer due to the thermal process during sacrificial layer formation because the first mask layer is covered by the second mask layer, thus avoiding the risk of source region exposure and contamination. Figure 9 As shown, the warpage problem of the first mask layer silicon nitride in the MOS device with deep trench superjunction formed in this embodiment is significantly improved.
[0064] In summary, in the manufacturing method of a MOS device with a deep trench superjunction provided in this embodiment of the invention, a first epitaxial layer, a well region, a first hard mask layer, and a second hard mask layer are sequentially formed on the substrate, and a gate and source regions located on both sides of the gate are formed in the well region; then a deep trench is formed, which sequentially penetrates the second hard mask layer, the first hard mask layer, and the well region, and extends into the first epitaxial layer, and interface damage is formed on the sidewalls and bottom wall of the deep trench; the interface damage on the sidewalls and bottom wall of the deep trench is repaired, and the width of the deep trench located in the well region is greater than... The width of the deep trench located in the first hard mask layer; in the step of repairing the interface damage of the sidewalls and bottom walls of the deep trench, a second hard mask layer is used to protect the first hard mask layer and prevent warping of the first hard mask layer; then, a back etching process is performed to etch the first hard mask layer so that the sidewalls of the deep trench located in the first hard mask layer are flush with the sidewalls of the deep trench located in the well region; then, an epitaxial process is performed to fill the deep trench with a second epitaxial layer. The first epitaxial layer and the second epitaxial layer have different doping types, and the first epitaxial layer and the second epitaxial layer constitute a deep trench superjunction. In this way, by bringing the step of repairing the interface damage of the sidewalls and bottom walls of the deep trench forward, warping of the first hard mask layer is avoided, thereby preventing the risk of contamination in the source region front.
[0065] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, different parts between embodiments can also be combined with each other, and this invention does not limit this.
[0066] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A method for manufacturing a MOS device with a deep trench superjunction, characterized in that, include: A substrate is provided on which a first epitaxial layer, a well region, a first hard mask layer and a second hard mask layer are sequentially formed, and a gate and source regions located on both sides of the gate are formed in the well region. A deep trench is formed, which sequentially penetrates the second hard mask layer, the first hard mask layer and the well region, and extends into the first epitaxial layer. The sidewalls and bottom walls of the deep trench have interface damage. Repair the interface damage of the sidewalls and bottomwalls of the deep trench, and the width of the deep trench located in the well region is greater than the width of the deep trench located in the first hard mask layer; Perform a back etching process to etch the first hard mask layer so that the sidewalls of the deep trenches located in the first hard mask layer are flush with the sidewalls of the deep trenches located in the well region. An epitaxial process is performed to fill the deep trench with a second epitaxial layer. The first epitaxial layer and the second epitaxial layer have different doping types, and the first epitaxial layer and the second epitaxial layer constitute a deep trench superjunction.
2. The method for manufacturing a MOS device with a deep trench superjunction as described in claim 1, characterized in that, The steps for repairing the interface damage to the bottom and sidewalls of the deep trench include: A sacrificial layer is formed, which is located on the bottom and sidewalls of the deep trench; Remove the sacrificial layer from the bottom and sidewalls of the deep trench to repair the interface damage to the bottom and sidewalls of the deep trench.
3. The method for manufacturing a MOS device with a deep trench superjunction as described in claim 2, characterized in that, The sacrificial layer is made of silicon oxide, and the first epitaxial layer is made of silicon. The bottom and sidewalls of the deep trench are oxidized into the sacrificial layer using a thermal oxidation process.
4. The method for manufacturing a MOS device with a deep trench superjunction as described in claim 2, characterized in that, The material of the second hard mask layer is silicon oxide. When removing the sacrificial layer of the bottom wall and sidewall of the deep trench, a portion of the second hard mask layer is also removed.
5. The method for manufacturing a MOS device with a deep trench superjunction as described in claim 4, characterized in that, The sacrificial layer and part of the second hard mask layer on the bottom and sidewalls of the deep trench are removed by a wet etching process.
6. The method for manufacturing a MOS device with a deep trench superjunction as described in claim 1, characterized in that, After performing the etch-back process and before performing the epitaxial process, the method further includes: removing the second hard mask layer.
7. The method for manufacturing a MOS device with a deep trench superjunction as described in claim 1, characterized in that, The first epitaxial layer and the substrate have the same doping type, while the second epitaxial layer and the substrate have different doping types.
8. The method for manufacturing a MOS device with a deep trench superjunction as described in claim 1, characterized in that, The material of the first hard mask layer is silicon nitride.
9. The method for manufacturing a MOS device with a deep trench superjunction as described in claim 1, characterized in that, The etching process is a wet etching process.
10. A MOS device with a deep trench superjunction, characterized in that, It is prepared by the manufacturing method of the MOS device with deep trench superjunction as described in any one of claims 1 to 9.