Silicon wafer evaluation method, manufacturing method, device, and silicon wafer

Abstract

This invention provides a silicon wafer evaluation method, manufacturing method, apparatus, storage medium, and electronic device. The silicon wafer evaluation method includes acquiring contour data of the silicon wafer to be evaluated in the cutting direction after wire cutting; determining mechanical evaluation parameters based on the contour data, the mechanical evaluation parameters characterizing the mechanical response of the silicon wafer to be evaluated during pressure processing; comparing the mechanical evaluation parameters with preset thresholds to obtain comparison results; and determining and outputting evaluation results for the nanostructure quality of the silicon wafer to be evaluated based on the comparison results. This invention enables effective evaluation of the nanostructure quality of silicon wafers after wire cutting.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a silicon wafer evaluation method, manufacturing method, apparatus, silicon wafer, storage medium, and electronic device. Background Technology

[0002] In the semiconductor silicon wafer manufacturing process, after the silicon wafer undergoes wire saw cutting, it typically requires multiple pressure processing steps, such as lapping, double fine grinding (DFG), double side polishing (DSP), and final polishing (FP). Because the shape of a silicon wafer after wire cutting is uneven, some areas are difficult to flatten during pressure processing, resulting in poor nanostructure quality. Therefore, it is usually necessary to evaluate the shape quality of the silicon wafer after wire cutting to ensure stable subsequent processing.

[0003] However, there is currently no method to accurately evaluate the quality of the shape of silicon wafers after wire cutting. Summary of the Invention

[0004] In view of this, the present invention aims to provide a silicon wafer evaluation method, manufacturing method, apparatus, storage medium, and electronic device to solve the problem in the prior art that the quality of the geometry of silicon wafers after wire cutting cannot be accurately evaluated.

[0005] This invention provides a silicon wafer evaluation method, the method comprising: Obtain the contour data of the silicon wafer to be evaluated in the cutting direction after wire cutting; Based on the contour data, mechanical evaluation parameters are determined, which characterize the mechanical response of the silicon wafer to be evaluated during pressure processing. The mechanical evaluation parameters are compared with preset thresholds to obtain the comparison results; Based on the comparison results, the evaluation results for the nano-morphology quality of the silicon wafer to be evaluated are determined and output.

[0006] In one embodiment, determining the mechanical evaluation parameters based on the contour data includes: Based on the contour data, a static model of the silicon wafer to be evaluated is constructed to obtain the silicon wafer model; Contact simulation during the pressure processing is performed based on the silicon wafer model to obtain contact results, which include the contact pressure on multiple nodes on the surface of the silicon wafer model. Based on the contact results, the mechanical evaluation parameters are determined.

[0007] In one embodiment, determining the mechanical evaluation parameters based on the contact results includes: The nodes with a contact pressure of 0 among the plurality of nodes are identified as non-contact nodes; Calculate the ratio of the number of uncontacted nodes to the number of multiple nodes to obtain the proportion of uncontacted area corresponding to the silicon wafer model; The percentage of non-contact area is determined as the mechanical evaluation parameter.

[0008] In one embodiment, the preset threshold includes a ratio threshold, and the step of determining and outputting the evaluation result for the nanostructure quality of the silicon wafer to be evaluated based on the comparison result includes: If the comparison result indicates that the proportion of the non-contact area is less than the proportion threshold, then the evaluation result indicates that the nano-morphological quality of the silicon wafer to be evaluated meets the preset quality requirements.

[0009] In one embodiment, the step of constructing a static model of the silicon wafer to be evaluated based on the contour data to obtain a silicon wafer model includes: The contour data is fitted with a polynomial to obtain a first fitting function; The first curve corresponding to the first fitting function is magnified by a specified factor and then translated by a specified distance, and the trajectory of the first curve during the translation process is determined as the first surface; A second surface is extracted from the first surface according to a specified cut area, and the second surface is determined as the silicon wafer model.

[0010] In one embodiment, the silicon wafer model includes a constraint portion, which includes a first constraint point and a second constraint point; The first constraint point is set at the first corner point in the infeed direction of the silicon wafer model, and is used to constrain the translational degree of freedom of the first corner point in the infeed direction; The second constraint point is set at the second corner point in the target direction of the silicon wafer model, and is used to constrain the translational degree of freedom of the second corner point in the target direction, wherein the target direction is perpendicular to the infeed direction.

[0011] In one embodiment, determining the mechanical evaluation parameters based on the contour data includes: The contour data is fitted using a first-order polynomial to obtain a second fitting function; The second curve corresponding to the second fitting function is de-sloped to obtain the de-sloped second curve. The second curve after deskewing is subjected to double Gaussian low-pass filtering to obtain the main contour and corrugation contour of the silicon wafer to be evaluated. Determine the first curvature energy corresponding to the main body contour and the second curvature energy corresponding to the wavy contour; The first curvature energy and the second curvature energy are determined as the mechanical evaluation parameters.

[0012] In one embodiment, determining the first curvature energy corresponding to the main body contour and the second curvature energy corresponding to the wavy contour includes: The main body contour is subjected to a second difference process to obtain a first difference curve, and the wavy contour is subjected to a second difference process to obtain a second difference curve. Based on the specified dividing radius, the first difference curve is divided into a first sub-difference curve corresponding to the central region and a second sub-difference curve corresponding to the edge region; Based on the specified dividing radius, the second difference curve is divided into a third sub-difference curve corresponding to the central region and a fourth sub-difference curve corresponding to the edge region; Calculate the first sub-curvature energy corresponding to the first sub-difference curve, the second sub-curvature energy corresponding to the second sub-difference curve, the third sub-curvature energy corresponding to the third sub-difference curve, and the fourth sub-curvature energy corresponding to the fourth sub-difference curve; The first sub-curvature energy and the second sub-curvature energy are determined as the first curvature energy, and the third sub-curvature energy and the fourth sub-curvature energy are determined as the second curvature energy.

[0013] In one embodiment, calculating the first sub-curvature energy corresponding to the first sub-difference curve, the second sub-curvature energy corresponding to the second sub-difference curve, the third sub-curvature energy corresponding to the third sub-difference curve, and the fourth sub-curvature energy corresponding to the fourth sub-difference curve includes: The curvatures of the first sub-difference curve, the second sub-difference curve, the third sub-difference curve, and the fourth sub-difference curve are respectively squared, summed, and logarithmized to obtain the energy of the first sub-curvature, the energy of the second sub-curvature, the energy of the third sub-curvature, and the energy of the fourth sub-curvature.

[0014] In one embodiment, the preset threshold includes a curvature energy threshold, and the determination and output of the evaluation result for the nanostructure quality of the silicon wafer to be evaluated based on the comparison result includes: If the comparison result indicates that at least one of the energy curvatures of the first sub-curvature energy, the second sub-curvature energy, the third sub-curvature energy, and the fourth sub-curvature energy is less than its corresponding curvature energy threshold, then the evaluation result indicates that the nanomorphic quality of the silicon wafer to be evaluated meets the preset quality requirements.

[0015] In one embodiment, determining and outputting the evaluation result of the nanomorphological quality of the silicon wafer to be evaluated based on the comparison result includes: If the first sub-curvature energy is less than -3, then the evaluation result indicates that the nano-morphological quality of the silicon wafer to be evaluated meets the preset quality requirements. Alternatively, if the second sub-curvature energy is less than -2.5, then the evaluation result indicates that the nano-morphological quality of the silicon wafer to be evaluated meets the preset quality requirements. Alternatively, if the first sub-curvature energy is less than -3 and the second sub-curvature energy is less than -2.5, then the evaluation result indicates that the nano-morphological quality of the silicon wafer to be evaluated meets the preset quality requirements.

[0016] Another aspect of the present invention provides a method for manufacturing a silicon wafer, the method comprising: Obtain the contour data of the silicon wafer in the cutting direction after wire cutting process; Based on the contour data, mechanical evaluation parameters are determined, which characterize the mechanical response of the silicon wafer during pressure processing. The mechanical evaluation parameters are compared with preset thresholds to obtain the comparison results; Based on the comparison results, an evaluation result for the nanostructure quality of the silicon wafer is determined and output. If the evaluation results indicate that the nano-morphology quality of the silicon wafer does not meet the preset quality requirements, the process parameters of the wire cutting process are adjusted based on the comparison results, so that the silicon wafer is manufactured based on the adjusted wire cutting process.

[0017] In one embodiment, adjusting the process parameters of the wire EDM process based on the comparison results includes: The target area of ​​the silicon wafer is determined based on the comparison results. The target area is the area of ​​the silicon wafer that is difficult to flatten during the pressure processing. The temperature of the coolant applied to the target area during the wire cutting process is adjusted.

[0018] In another aspect, the present invention provides a silicon wafer evaluation apparatus, the silicon wafer evaluation apparatus comprising: The acquisition module is used to acquire the contour data of the silicon wafer to be evaluated in the cutting direction after wire cutting; The determination module is used to determine mechanical evaluation parameters based on the contour data, wherein the mechanical evaluation parameters characterize the mechanical response of the silicon wafer to be evaluated during the pressure processing process; The comparison module is used to compare the mechanical evaluation parameters with a preset threshold to obtain the comparison result; The evaluation module is used to determine and output the evaluation results of the nano-morphology quality of the silicon wafer to be evaluated based on the comparison results.

[0019] In another aspect, the present invention provides a silicon wafer manufactured by the silicon wafer manufacturing method of the above embodiments, wherein the intermediate state of the silicon wafer after wire cutting has the following process parameters: the first sub-curvature energy is less than -3, and the second sub-curvature energy is less than -2.5; In some embodiments, the final product parameters of the silicon wafer satisfy the following: the surface nano-topography height measured within a 10mm × 10mm area is less than 15nm; wherein, the first sub-curvature energy is the curvature energy corresponding to the central region of the main contour obtained after the silicon wafer is wire-cut, and the second sub-curvature energy is the curvature energy corresponding to the edge region of the main contour obtained after the silicon wafer is wire-cut.

[0020] In another aspect, the present invention provides a computer-readable storage medium having stored thereon computer-executable instructions which, when executed by a processor, implement the silicon wafer evaluation method as described in any of the above embodiments.

[0021] In another aspect, the present invention provides an electronic device, the electronic device comprising: processor; Memory used to store the processor's executable instructions; The processor is used to execute the silicon wafer evaluation method described in any of the above embodiments.

[0022] Compared with related technologies, the silicon wafer evaluation method provided by this invention has the following advantages: The silicon wafer evaluation method provided by this invention acquires the contour data of the wire-cut silicon wafer in the cutting direction; based on the contour data, mechanical evaluation parameters are determined, which characterize the mechanical response of the silicon wafer during pressure processing; the mechanical evaluation parameters are compared with preset thresholds to obtain comparison results; and based on the comparison results, the evaluation results for the nano-morphological quality of the silicon wafer are determined and output. This method transforms wire-cut contour data into evaluation parameters characterizing the mechanical response of pressure processing and compares them with preset thresholds to predict and evaluate the processing effect of the wire-cut silicon wafer during pressure processing from the perspective of mechanical response. This allows for accurate evaluation of the nano-morphological quality of the cut silicon wafer based on the processing effect, and also enables precise identification of early-stage defects in silicon wafer processing, avoiding subsequent ineffective processing costs. Attached Figure Description

[0023] Figure 1 The diagram shown is a structural schematic of a static model provided in an embodiment of the present invention.

[0024] Figure 2 The image shown is a nanostructure diagram of a silicon wafer obtained after wire cutting, according to an embodiment of the present invention.

[0025] Figure 3 The diagram shows the flattening result of a silicon wafer after a pressure processing process, according to an embodiment of the present invention.

[0026] Figure 4 The diagram shown is a schematic diagram of the flattening result of a silicon wafer after a pressure processing process according to another embodiment of the present invention.

[0027] Figure 5 The image shown is a nanomorphological mapping diagram of a silicon wafer that has undergone a pressure processing process according to an embodiment of the present invention.

[0028] Figure 6 The diagram shown is a schematic flowchart of a silicon wafer evaluation method provided in an embodiment of the present invention.

[0029] Figure 7 The figure shown is a schematic diagram of polynomial fitting of contour data according to an embodiment of the present invention.

[0030] Figure 8 The figure shown is a schematic diagram of the geometric model of a silicon wafer model provided in an embodiment of the present invention.

[0031] Figure 9 The image shown is a top view of a silicon wafer model provided in an embodiment of the present invention.

[0032] Figure 10 The image shown is a contact state cloud diagram of a silicon wafer model provided in an embodiment of the present invention.

[0033] Figure 11 The image shown is an original outline diagram of the cutting direction of a silicon wafer provided in an embodiment of the present invention.

[0034] Figure 12 The image shown is a detrended contour diagram provided in an embodiment of the present invention.

[0035] Figure 13 The figure shown is a main body outline diagram provided in an embodiment of the present invention.

[0036] Figure 14 The image shown is a corrugated profile diagram provided in an embodiment of the present invention.

[0037] Figure 15 The figure shown is a curve diagram of the main body outline provided in an embodiment of the present invention.

[0038] Figure 16 The figure shown is a ripple profile curvature diagram provided in an embodiment of the present invention.

[0039] Figure 17 The diagram shows a linear fitting relationship between the body-center-curvature energy and the scatter plot of the nanostructure (NT) provided in an embodiment of the present invention.

[0040] Figure 18 The diagram shown is a schematic flow chart of a silicon wafer manufacturing method according to an embodiment of the present invention.

[0041] Figure 19 The diagram shown is a schematic diagram of the flattening result of a silicon wafer after a pressure processing process, according to another embodiment of the present invention.

[0042] Figure 20 The diagram shows the distribution of cooling water temperature in various regions of a silicon wafer during a conventional Wire Saw processing procedure according to an embodiment of the present invention.

[0043] Figure 21 The diagram shows the distribution of cooling water temperature in various regions of the silicon wafer during the adjusted Wire Saw processing according to an embodiment of the present invention.

[0044] Figure 22 The diagram shown is a comparison of the original contour, the curvature of the main contour, and the curvature of the wavy contour provided in an embodiment of the present invention.

[0045] Figure 23 The diagram shown is a schematic block diagram of a silicon wafer evaluation device provided in an embodiment of the present invention.

[0046] Figure 24 The diagram shown is a block diagram of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0047] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0048] After wire saw processing, silicon wafers undergo multiple pressure processing steps (such as lapping, DFG, DSP, FP, etc.). These processes can be achieved through methods such as... Figure 1 The static model shown is used for representation. Specifically, in Figure 1 In this process, silicon wafers can be placed on a pad (such as...) Figure 1 On a fixed rigid pad, the upper surface of the silicon wafer is subjected to a stable pressure (such as...). Figure 1 The uniform load P in the process is provided by a processing disk used in the pressure processing of the silicon wafer. The processing disk and the pad below it then move together to perform grinding, polishing and other processing on the silicon wafer.

[0049] One issue is that the shape of a silicon wafer becomes uneven after wire cutting. This can cause some areas to be difficult to flatten during pressure processing. These areas that are difficult to flatten will have insufficient processing pressure in subsequent grinding or polishing processes, thus failing to achieve the expected processing effect and ultimately resulting in poor nano-morphology of the silicon wafer.

[0050] As an example, such as Figure 2 As shown, Figure 2 The image shows the nanostructure of a silicon wafer obtained after wire dicing. Figure 2 The cutting direction in the diagram is the same as the cutting direction of the silicon wafer during wire saw processing. Figure 2 In the diagram, the purple areas represent regions on the silicon wafer with poor nanostructure quality (hereinafter referred to as defects). The schematic diagram of the flattening result of the silicon wafer after the pressure processing process is shown below. Figure 3 As shown, Z represents the entry path (i.e., along) in the wire EDM process. Figure 3 The shape along the path in the infeed direction. UZ represents the deformation that occurs during the flattening stage of the silicon wafer, and Z+UZ represents the final shape of the silicon wafer after flattening. From Figure 3 This reveals that silicon wafers with relatively curved sections in their original shape are not easily flattened. This, in turn, leads to poor processing results in subsequent pressure processing steps. Figure 3 The horizontal axis represents the radial position, that is, the radius distance from the center of the silicon wafer, and the vertical axis represents the height of the silicon wafer surface.

[0051] Furthermore, the applicant discovered in their actual research that during the flattening process of silicon wafers, it is necessary to overcome the bending strain energy of the material. The more curved the area, the more difficult it is to flatten; the greater the bending strain energy at that point, the more work is required for flattening, and the greater the difficulty of flattening. Specifically, in the field of mechanics, the strain energy of a simple beam is shown in the following formula: in, U The total bending strain energy of the beam. M(x) For a certain position on the beam x The bending moment at the point (the moment generated by the bending force); E The elastic modulus of a material is used to reflect its ability to resist elastic deformation. I It is the moment of inertia of the cross section, which is related to the cross section size and shape, and is used to reflect the cross section shape's resistance to bending deformation; the integration interval is the entire length of the beam.

[0052] Since the morphology of a silicon wafer is a non-uniform curve (i.e., the undulations are different in different places), it can be specifically represented by the following formula: in, κ Curvature is a geometric quantity representing the degree of bending of the beam's axis.

[0053] Furthermore, the applicant also discovered in their actual research that the edges of the silicon wafer are often more difficult to flatten during the wafer flattening process. Specifically, for example... Figure 4 As shown, at -150mm, the shape does not exhibit significant bending, but unflattened areas still appear. These edge effects can be attributed to the following factors: First, the edges are less constrained, more free, and harder to flatten.

[0054] Second, the edges are squeezed by the central region of the silicon wafer, which exacerbates the disorder. The ease with which the edges are flattened is no longer simply determined by the strain energy of the edge region.

[0055] Third, during the processing, the stability and uniformity of pressure applied to the edges are not as good as those in the central area of ​​the silicon wafer.

[0056] Based on the above analysis, it can be determined that defects in nanostructures often occur near the edges. As an example, for instance, ... Figure 5 As shown, Figure 5 This image shows a nanostructure mapping of a silicon wafer after a pressure processing process, as demonstrated in a real-world test. Specifically, in... Figure 5 In the image, the purple defect areas are mainly concentrated at the edges, primarily along the cut direction and in directions perpendicular to the cut. The edge defects along the diameter perpendicular to the cut direction are due to the high point at the center of the silicon wafer's cut shape. Figure 5 The defects are caused by the large curvature of the edge; and the edge defects in the tangent direction are also affected by the morphology of the tangent edge.

[0057] In summary, when the shape of the silicon wafer surface fluctuates due to the wire cutting process, the processing pressure cannot be properly applied to the silicon wafer surface during the subsequent pressure processing stage, resulting in poor pressure processing effect and affecting the nano-morphological quality of the processed silicon wafer.

[0058] In view of the above problems, one embodiment of the present invention provides a silicon wafer evaluation method, which can be executed by a computer device (e.g., a server or a user terminal). Figure 6 As shown, the silicon wafer evaluation method may include: 110. Obtain the contour data of the silicon wafer to be evaluated in the cutting direction after wire cutting.

[0059] In some implementations, the raw silicon wafer that has undergone wire cutting but has not yet undergone any subsequent pressure processing (such as grinding or polishing) is used as the silicon wafer to be evaluated.

[0060] For the silicon wafer to be evaluated, its surface profile can be scanned using a contact profilometer or a non-contact optical profilometer, and the profile data in the tangential direction can be extracted from the scanned surface profile. Then, the profile data is uploaded to a computer device.

[0061] The contour data can be a sequence of height values ​​and their corresponding positions collected at fixed intervals along a pre-defined measurement path that traverses the silicon wafer surface (i.e., along the tangential direction). This contour data describes a surface contour line on the silicon wafer. As an example, specific contour data can be found in [reference needed]. Figure 3 or Figure 4 The Z-curve in the diagram.

[0062] 120. Based on the contour data, determine the mechanical evaluation parameters, which characterize the mechanical response of the silicon wafer under evaluation during the pressure processing.

[0063] In some embodiments, the specific implementation of determining the mechanical evaluation parameters based on the contour data in step 120 may include: 121a. Based on the contour data, construct a static model of the silicon wafer to be evaluated to obtain the silicon wafer model.

[0064] Since the static response of silicon wafers during pressure processing can be well simulated in the finite element method, a finite element model of the silicon wafer can be constructed based on its contour data. This finite element model can be implemented using methods such as... Figure 1 The static model shown.

[0065] In some implementations, in step 121, a static model of the silicon wafer to be evaluated is constructed based on the contour data to obtain the silicon wafer model. Specific implementations may include: The contour data is fitted with a polynomial to obtain the first fitting function.

[0066] The first curve corresponding to the first fitting function is magnified by a specified factor and then translated by a specified distance. The trajectory of the first curve during the translation process is determined as the first surface.

[0067] The second surface is cut out from the first surface according to the specified cut area, and the second surface is determined as the silicon wafer model.

[0068] For example, such as Figure 7 As shown, this contour data (such as...) can be... Figure 7 Polynomial fitting is performed on the solid line in the graph to obtain a first fitting function of a sixth-degree polynomial. The first curve corresponding to the first fitting function is shown in Figure 1. Figure 7 The dashed line in the middle.

[0069] Because the original shape thickness of the silicon wafer is too small, after obtaining the first curve corresponding to the first fitting function, the first curve can be magnified by a specified factor to make the shape thickness characteristics more significant and facilitate subsequent analysis. Optionally, the specified factor can be 10 times. The specified factor can be set according to actual needs and is not limited here.

[0070] After magnifying the first curve by a specified factor, the magnified first curve can be translated a specified distance along a specified direction, and the trajectory traversed by the first curve during the translation process can be defined as the first surface. The specified direction can be perpendicular to the plane containing the first curve.

[0071] For example, the specified cut area can be a circular area with a diameter of 300 mm. In practical applications, after obtaining the first surface, a cylinder with a diameter of 300 mm can be used to cut a 300 mm circular surface from the first surface, and this circular surface can be used as the second surface. As an example, the cut second surface can be as follows: Figure 8 As shown, Figure 8 The geometric model shown can be used as the geometric model of the silicon wafer to be evaluated, i.e., the silicon wafer model described above. Optionally, the second surface can also be meshed, where the mesh size can be 1 mm, and the finite element type can be a reduced integral quadrilateral element.

[0072] Considering the large diameter and small thickness of silicon wafers, in this embodiment, a first fitting function is obtained by polynomial fitting of the contour data. The first curve corresponding to the first fitting function is then magnified by a specified factor and translated by a specified distance, and the trajectory traversed by the first curve during the translation is determined as a first surface. A second surface is then extracted from the first surface according to a specified area, and this second surface is determined as the silicon wafer model. This abstracts the silicon wafer into a surface, which accelerates the simulation speed and improves evaluation efficiency in subsequent finite element simulations.

[0073] In some implementations, the silicon wafer model includes a constraint portion, which includes a first constraint point and a second constraint point.

[0074] The first constraint point is set at the first corner point in the tangent direction of the silicon wafer model, and is used to constrain the translational degree of freedom of the first corner point in the tangent direction.

[0075] The second constraint point is set at the second corner point in the target direction of the silicon wafer model. It is used to constrain the translational degree of freedom of the second corner point in the target direction, which is perpendicular to the infeed direction.

[0076] For example, a top view of a silicon wafer model is as follows: Figure 9 As shown, the tangent direction can be the direction from the left vertex of the silicon wafer model to the center of the silicon wafer model (i.e., Figure 9 (In the X-axis direction), the first corner point can be located at the left vertex of the silicon wafer model, and the second corner point can be located at the top vertex of the silicon wafer model. The target direction is... Figure 9 In the Y-axis direction.

[0077] In this embodiment, by applying constraints to two corner points of the silicon wafer model (such as the point at the tangent direction and the point perpendicular to the tangent direction), the rigid body displacement of the silicon wafer model in the subsequent contact simulation process can be effectively eliminated, ensuring the stability of the solution.

[0078] 122a. Based on the silicon wafer model, a contact simulation of the pressure processing process is performed to obtain the contact results, which include the contact pressure on multiple nodes on the surface of the silicon wafer model.

[0079] For example, when simulating contact on a silicon wafer model, a circular wafer model slightly larger than the silicon wafer diameter (with a diameter of 301 mm) can be modeled below the silicon wafer model (at a distance of approximately 0.6 mm) to act as a rigid pad model. A contact pair is established between the rigid pad model and the silicon wafer model. Then, uniform pressure (which can be set to 80 kPa) is applied to each node on the silicon wafer model to simulate the contact process of the silicon wafer during pressure processing.

[0080] Optionally, during contact simulation, the material parameters of the silicon wafer model can be the single-crystal silicon stiffness matrix, specifically C11=165.7GPa, C12=63.9GPa, and C44=79.6GPa.

[0081] 123a. Based on the contact results, determine the mechanical evaluation parameters.

[0082] In some implementations, the determination of mechanical evaluation parameters based on the contact results in step 123a may include: The node with zero contact pressure among multiple nodes is identified as the non-contact node.

[0083] Calculate the ratio of non-contact nodes to multiple nodes to obtain the proportion of non-contact area corresponding to the silicon wafer model.

[0084] The percentage of non-contact area was determined as a mechanical evaluation parameter.

[0085] For example, the contact pressure at each node on the silicon wafer model can be obtained by solving the static model of the contact process described above, and the contact result can be generated based on the contact pressure at each node. Optionally, as... Figure 10 As shown, Figure 10 The contact state cloud map is shown. Figure 10 In this context, the contact pressure value ranges from 1.00 to 3.00, indicating the degree of contact. A higher contact pressure value indicates a tighter contact.

[0086] Following the example above, it can be done by... Figure 10 The percentage of nodes with zero contact pressure (considered as non-contact) within a radius of 130-150 on the edge is statistically analyzed. This percentage is then used as the mechanical evaluation parameter.

[0087] In other embodiments, the specific implementation of determining the mechanical evaluation parameters based on the contour data in step 120 may include: 121b. The contour data is fitted using a first-order polynomial to obtain the second fitting function.

[0088] 122b. The second curve corresponding to the second fitting function is de-sloped to obtain the de-sloped second curve.

[0089] For example, with Figure 11 Taking the original contour shown as contour data as an example, a first-order polynomial can be used to fit the contour data to obtain a second fitting function. Then, the fitted first-order polynomial is subtracted from the second fitting function to obtain the de-sloping (or detrended) curve, i.e., the de-sloping second curve. The de-sloping second curve can be shown as follows: Figure 12 As shown, Figure 12The detrending curve in the graph is the second curve after desloping.

[0090] 123b. Perform double Gaussian low-pass filtering on the second curve after deskewing to obtain the main contour and corrugation contour of the silicon wafer to be evaluated.

[0091] Using the example above, we can... Figure 12 The de-tilted second curve is subjected to a double Gaussian low-pass filter, wherein the cutoff wavelength can be selected from 30mm to 70mm, preferably 40mm. Then, the low-pass profile obtained by filtering is denoted as the main profile. Subtracting the main profile from the de-tilted second curve yields the high-pass profile, which is denoted as the corrugated profile. For example, the main profile and the corrugated profile are respectively as follows: Figure 13 and Figure 14 As shown.

[0092] 124b. Determine the first curvature energy corresponding to the main contour and the second curvature energy corresponding to the wavy contour.

[0093] In some implementations, the specific implementation of determining the first curvature energy corresponding to the main body contour and the second curvature energy corresponding to the ripple contour in step 124b may include: B1. Perform a second difference process on the main outline to obtain the first difference curve, and perform a second difference process on the wavy outline to obtain the second difference curve.

[0094] B2. Based on the specified dividing radius, the first difference curve is divided into a first sub-difference curve corresponding to the central region and a second sub-difference curve corresponding to the edge region.

[0095] B3. Based on the specified dividing radius, the second difference curve is divided into a third sub-difference curve corresponding to the central region and a fourth sub-difference curve corresponding to the edge region.

[0096] B4. Calculate the energy of the first sub-curvature corresponding to the first sub-difference curve, the energy of the second sub-curvature corresponding to the second sub-difference curve, the energy of the third sub-curvature corresponding to the third sub-difference curve, and the energy of the fourth sub-curvature corresponding to the fourth sub-difference curve.

[0097] In some implementations, the specific implementation of calculating the first sub-curvature energy corresponding to the first sub-difference curve, the second sub-curvature energy corresponding to the second sub-difference curve, the third sub-curvature energy corresponding to the third sub-difference curve, and the fourth sub-curvature energy corresponding to the fourth sub-difference curve in step B4 may include: The curvatures of the first, second, third, and fourth sub-difference curves are respectively squared, summed, and logarithmized to obtain the energy of the first, second, third, and fourth sub-curvatures.

[0098] B5. Determine the first sub-curvature energy and the second sub-curvature energy as the first curvature energy, and determine the third sub-curvature energy and the fourth sub-curvature energy as the second curvature energy.

[0099] For example, the main contour and the corrugated contour can be subdivided twice, and the resulting curves can be divided into regions. Optionally, division point 1 and division point 2 can be used to divide the curves into regions. For example, division point 1 can be located on a radius of 125mm to 145mm, specifically 120mm. Division point 1 can be used to divide the corresponding central regions (e.g., radius r: 0mm-120mm) from the main contour and the corrugated contour respectively. Division point 2 can be located on a radius of 80mm to 120mm, specifically 100mm. Division point 2 can be used to divide the corresponding edge regions (e.g., radius r: 100mm-150mm) from the main contour and the corrugated contour respectively. Then, for each contour in the main contour and the ripple contour, the curvature in its center and edge regions is squared and summed (squared first, then summed), followed by a logarithmic operation. This yields four curvature energies: main-center curvature energy (i.e., the first sub-curvature energy mentioned above), main-edge curvature energy (i.e., the second sub-curvature energy mentioned above), ripple-center curvature energy (i.e., the third sub-curvature energy mentioned above), and ripple-edge curvature energy (i.e., the fourth sub-curvature energy mentioned above). For example, the contour curvature corresponding to the main contour can be as follows: Figure 15 As shown, the contour curvature corresponding to the wavy profile can be as follows: Figure 16 As shown.

[0100] 125b. The first curvature energy and the second curvature energy are determined as mechanical evaluation parameters.

[0101] Following the example above, the first sub-curvature energy, the second sub-curvature energy, the third sub-curvature energy, and the fourth sub-curvature energy can be determined as mechanical evaluation parameters.

[0102] 130. Compare the mechanical evaluation parameters with the preset thresholds to obtain the comparison results.

[0103] In some implementations, the preset thresholds include a proportional threshold and a curvature energy threshold. In this implementation, the proportion of non-contact area can be compared with the proportional threshold to obtain a comparison result. Alternatively, the first sub-curvature energy, the second sub-curvature energy, the third sub-curvature energy, and the fourth sub-curvature energy can be compared with their corresponding curvature energy thresholds to obtain a comparison result.

[0104] 140. Based on the comparison results, determine and output the evaluation results of the nano-morphology quality of the silicon wafer to be evaluated.

[0105] In some implementations, the preset threshold includes a proportional threshold. In step 140, a specific implementation of determining and outputting the evaluation result for the nanostructure quality of the silicon wafer to be evaluated based on the comparison result may include: If the comparison results indicate that the proportion of non-contact area is less than the proportion threshold, then the evaluation results indicate that the nano-morphological quality of the silicon wafer to be evaluated meets the preset quality requirements.

[0106] If the nano-morphology quality of the silicon wafer meets the preset quality requirements, the nano-morphology quality of the silicon wafer can be determined to be good.

[0107] For example, if the proportion threshold is 30%, when the proportion of non-contact area is less than 30%, it can be determined that silicon wafers with good nano-morphological quality can be obtained by the current wire cutting process.

[0108] In other embodiments, the preset threshold includes a curvature energy threshold. In step 140, specific implementations of determining and outputting the evaluation results for the nanostructure quality of the silicon wafer to be evaluated based on the comparison results may include: If the comparison results indicate that at least one of the energy curvatures of the first sub-curvature energy, the second sub-curvature energy, the third sub-curvature energy, and the fourth sub-curvature energy is less than its corresponding curvature energy threshold, then the evaluation results indicate that the nanomorphic quality of the silicon wafer to be evaluated meets the preset quality requirements.

[0109] Optionally, if the first sub-curvature energy is less than -3, the evaluation result indicates that the nano-morphological quality of the silicon wafer to be evaluated meets the preset quality requirements; or, if the second sub-curvature energy is less than -2.5, the evaluation result indicates that the nano-morphological quality of the silicon wafer to be evaluated meets the preset quality requirements; or, if the first sub-curvature energy is less than -3 and the second sub-curvature energy is less than -2.5, the evaluation result indicates that the nano-morphological quality of the silicon wafer to be evaluated meets the preset quality requirements.

[0110] As an example, one or more of the four curvature energies mentioned above can be combined to control the quality of the silicon wafer after wire saw. For instance, when using body-center curvature energy (i.e., the first sub-curvature energy) and body-edge curvature energy (i.e., the second sub-curvature energy) for control, if the body-center curvature energy is less than -3 and the body-edge curvature energy is less than -2.5, it can be determined that the nanostructure quality of the silicon wafer being evaluated meets the preset quality requirements, and a silicon wafer with good nanostructure quality can be obtained through the current wire saw process. The curvature energy thresholds corresponding to the third and fourth sub-curvature energies can be set according to actual needs and are not limited here.

[0111] As another example, the curvature energy thresholds corresponding to each curvature can be determined based on specific process requirements to assess whether the evaluation results characterize the nanostructure quality of the silicon wafer under evaluation, meeting preset quality requirements. Specifically, the usage of the four curvature energies can be determined based on the subsequent processes after wire cutting. For example, if the wire cutting is followed by Double Disk Surface Grinding (DDSG), since this process provides good edge finishing of the silicon wafer, the body-center curvature energy (first sub-curvature energy) can be used for control, and it is acceptable when the first sub-curvature energy is less than -3. As another example, for the Lapping process, since this process provides poor edge finishing of the silicon wafer, the body-edge curvature energy (i.e., second sub-curvature energy) can be used for control, and it is acceptable when the second sub-curvature energy is less than -2.5. Furthermore, for higher quality silicon wafers, both the first sub-curvature energy and the second sub-curvature energy can be required to be less than -3 and less than -2.5 simultaneously.

[0112] In some implementations, a fitting relationship between curvature energy and the corresponding scatter points of the silicon wafer's nanostructure can be obtained in advance, and a curvature energy threshold can be set based on this fitting relationship. For example, a fitting relationship can be obtained in advance such as... Figure 17 The linear fit between the body-center-curvature energy and the scatter plot of the nanostructure (NT) is shown, and then the quality requirements of the nanostructure are determined from... Figure 17 The corresponding curvature energy is determined as the curvature energy threshold.

[0113] As can be seen, in this embodiment, the contour data of the silicon wafer to be evaluated after wire cutting in the cutting direction is acquired; based on the contour data, mechanical evaluation parameters are determined, which characterize the mechanical response of the silicon wafer to be evaluated during pressure processing; the mechanical evaluation parameters are compared with preset thresholds to obtain comparison results; and based on the comparison results, the evaluation results of the nano-morphology quality of the silicon wafer to be evaluated are determined and output. Thus, by converting wire cutting contour data into evaluation parameters characterizing the mechanical response of pressure processing and comparing them with preset thresholds, the processing effect of the silicon wafer to be evaluated after wire cutting during pressure processing can be predicted and evaluated from the perspective of mechanical response. This allows for accurate evaluation of the nano-morphology quality of the cut silicon wafer and enables precise identification of early-stage defects in silicon wafer processing, avoiding subsequent ineffective processing costs.

[0114] One embodiment of the present invention provides a silicon wafer manufacturing method, which can be executed by computer equipment (e.g., a server or user terminal). Figure 18 As shown, the silicon wafer manufacturing method may include: 210. Obtain the contour data of the silicon wafer in the cutting direction after wire cutting.

[0115] 220. Based on the contour data, determine the mechanical evaluation parameters, which characterize the mechanical response of the silicon wafer during the pressure processing.

[0116] 230. Compare the mechanical evaluation parameters with the preset thresholds to obtain the comparison results.

[0117] 240. Based on the comparison results, determine and output the evaluation results of the nano-morphology quality of silicon wafers.

[0118] The specific implementation methods of steps 210 to 240 can be referred to steps 110 to 140, and therefore will not be repeated here.

[0119] 250. If the evaluation results indicate that the nano-morphology quality of the silicon wafer does not meet the preset quality requirements, the process parameters of the wire cutting process shall be adjusted based on the comparison results, and the silicon wafer shall be manufactured based on the adjusted wire cutting process.

[0120] In some implementations, the specific implementation of adjusting the process parameters of the wire EDM process based on the comparison results in step 250 may include: The target area of ​​the silicon wafer is determined based on the comparison results. The target area is the part of the silicon wafer that is difficult to flatten during the pressure processing.

[0121] Adjusting the temperature of the coolant applied to the target area in the wire EDM process.

[0122] As an example, when the proportion of non-contact area at the edge exceeds the standard, the morphological and displacement profiles along the cutting direction can be used to determine whether the problem lies in the central or edge region of the silicon wafer. Subsequently, the process parameters (such as cooling water temperature or cutting fluid temperature) for the corresponding problem area (i.e., the target area mentioned above) in the wire cutting process can be adjusted. For instance, when the non-contact area ratio is greater than 30%, it can be determined based on... Figure 19 To determine whether the problem lies in the edge or center area of ​​the silicon wafer, specifically... Figure 19 In Figure A, the original contour curve Z is the central bulge, and the flattened curve has many burrs at its center, indicating a problem in the central region. Figure 19 In Figure B, the original contour curve Z curve curves upwards on the left, and after flattening, the center is very flat with burrs at the edges, which indicates that there is a problem in the edge area.

[0123] Following the example above, Figure 20 This illustrates the distribution of cooling water temperature across various regions of the silicon wafer during a typical wire saw machining process. In this example, if adjustments are needed to the cut profile of the processed silicon wafer, for example… Figure 19 For Figure B, the starting point of the processing needs to be adjusted. Figure 20The temperature at -150 on the horizontal axis was adjusted to be close to the midpoint temperature. Finally, the distribution of the adjusted cooling water temperature across different regions of the silicon wafer is shown below. Figure 21 As shown.

[0124] As another example, when the body curvature energy parameter exceeds the limit, the original contour, the body contour curvature, and the corrugated contour curvature can be compared, and then the parameter contour (cooling water temperature or cutting fluid temperature) can be controlled based on the comparison results. For example, as shown in Figure 22, from Figure 22 It can be clearly seen that the curvature at -150 (the point of entry) is too large (i.e.) Figure 22 (The bending strain energy in the dashed area of ​​the main body's contour curvature is too large). To adjust this, simply adjust the corresponding cooling water temperature. For specific adjustment methods, please refer to [reference needed]. Figure 21 The adjustment method in the example is not described in detail here.

[0125] As can be seen, in this embodiment, by accurately assessing the potential problems that may arise in the subsequent pressure process due to the nano-morphology quality of the silicon wafer after the wire cutting process, the process parameters of the wire cutting process can be adjusted in a timely manner to ensure the manufacturing efficiency and quality of the silicon wafer.

[0126] An embodiment of the present invention also provides a silicon wafer, which can be manufactured by the silicon wafer manufacturing method of the above embodiment, wherein the intermediate state of the silicon wafer after wire cutting has the following process parameters: the first sub-curvature energy is less than -3, and the second sub-curvature energy is less than -2.5; In some implementations, the final product parameters of the silicon wafer satisfy the following: the height of the surface nano-topography measured in a 10mm×10mm area is less than 15nm; wherein, the first sub-curvature energy is the curvature energy corresponding to the central region of the main contour obtained after the silicon wafer is wire-cut, and the second sub-curvature energy is the curvature energy corresponding to the edge region of the main contour obtained after the silicon wafer is wire-cut.

[0127] Figure 23 The diagram shown is a block diagram of a silicon wafer evaluation apparatus provided in an embodiment of the present invention. Figure 23 As shown, the silicon wafer evaluation device 300 includes: The acquisition module 310 is used to acquire the contour data of the silicon wafer to be evaluated in the cutting direction after wire cutting; The determination module 320 is used to determine mechanical evaluation parameters based on the contour data, wherein the mechanical evaluation parameters characterize the mechanical response of the silicon wafer to be evaluated during the pressure processing process; The comparison module 330 is used to compare the mechanical evaluation parameters with a preset threshold to obtain the comparison result; Evaluation module 340 is used to determine and output the evaluation result of the nano-morphology quality of the silicon wafer to be evaluated based on the comparison result.

[0128] In some implementations, the determining module 320 is specifically used for: Based on the contour data, a static model of the silicon wafer to be evaluated is constructed to obtain the silicon wafer model; Contact simulations were performed on a silicon wafer model during the pressure processing to obtain contact results, which included the contact pressures on multiple nodes on the surface of the silicon wafer model. Based on the contact results, determine the mechanical evaluation parameters.

[0129] In one embodiment, the determining module 320 is specifically used for: The nodes with zero contact pressure among multiple nodes are identified as non-contact nodes; Calculate the ratio of non-contact nodes to multiple nodes to obtain the proportion of non-contact area corresponding to the silicon wafer model; The percentage of non-contact area was determined as a mechanical evaluation parameter.

[0130] In one embodiment, the preset threshold includes a proportional threshold, and the evaluation module 340 is specifically used for: If the comparison results indicate that the proportion of non-contact area is less than the proportion threshold, then the evaluation results indicate that the nano-morphological quality of the silicon wafer to be evaluated meets the preset quality requirements.

[0131] In one embodiment, the determining module 320 is specifically used for: The contour data is fitted with a polynomial to obtain the first fitting function; The first curve corresponding to the first fitting function is magnified by a specified factor and then translated by a specified distance. The trajectory of the first curve during the translation process is determined as the first surface. The second surface is cut out from the first surface according to the specified cut area, and the second surface is determined as the silicon wafer model.

[0132] In one embodiment, the silicon wafer model includes a constraint portion, which includes a first constraint point and a second constraint point. The first constraint point is set at the first corner point in the infeed direction of the silicon wafer model, and is used to constrain the translational degree of freedom of the first corner point in the infeed direction. The second constraint point is set at the second corner point in the target direction of the silicon wafer model. It is used to constrain the translational degree of freedom of the second corner point in the target direction, which is perpendicular to the infeed direction.

[0133] In one embodiment, the determining module 320 is specifically used for: The contour data were fitted using a first-order polynomial to obtain the second fitting function; The second curve corresponding to the second fitted function is de-sloped to obtain the de-sloped second curve. The second curve after deskewing is subjected to double Gaussian low-pass filtering to obtain the main contour and corrugation contour of the silicon wafer to be evaluated. Determine the first curvature energy corresponding to the main body contour and the second curvature energy corresponding to the wavy contour; The first curvature energy and the second curvature energy are determined as mechanical evaluation parameters.

[0134] In one embodiment, the determining module 320 is specifically used for: The main outline is subjected to a second difference process to obtain the first difference curve, and the wavy outline is subjected to a second difference process to obtain the second difference curve. Based on the specified dividing radius, the first difference curve is divided into a first sub-difference curve corresponding to the central region and a second sub-difference curve corresponding to the edge region; Based on the specified dividing radius, the second difference curve is divided into a third sub-difference curve corresponding to the central region and a fourth sub-difference curve corresponding to the edge region; Calculate the first subcurvature energy corresponding to the first sub-difference curve, the second subcurvature energy corresponding to the second sub-difference curve, the third subcurvature energy corresponding to the third sub-difference curve, and the fourth subcurvature energy corresponding to the fourth sub-difference curve; The first sub-curvature energy and the second sub-curvature energy are defined as the first curvature energy, and the third sub-curvature energy and the fourth sub-curvature energy are defined as the second curvature energy.

[0135] In one embodiment, the determining module 320 is further configured to: The curvatures of the first, second, third, and fourth sub-difference curves are respectively squared, summed, and logarithmized to obtain the energy of the first, second, third, and fourth sub-curvatures.

[0136] In one embodiment, the preset threshold includes a curvature energy threshold, and the evaluation module 340 is further used for: If the comparison results indicate that at least one of the energy curvatures of the first sub-curvature energy, the second sub-curvature energy, the third sub-curvature energy, and the fourth sub-curvature energy is less than its corresponding curvature energy threshold, then the evaluation results indicate that the nanomorphic quality of the silicon wafer to be evaluated meets the preset quality requirements.

[0137] In one embodiment, the evaluation module 340 is further configured to: if the first sub-curvature energy is less than -3, determine that the evaluation result indicates that the nano-morphological quality of the silicon wafer to be evaluated meets the preset quality requirements; or, if the second sub-curvature energy is less than -2.5, determine that the evaluation result indicates that the nano-morphological quality of the silicon wafer to be evaluated meets the preset quality requirements; or, if the first sub-curvature energy is less than -3 and the second sub-curvature energy is less than -2.5, determine that the evaluation result indicates that the nano-morphological quality of the silicon wafer to be evaluated meets the preset quality requirements.

[0138] The specific implementation process of the functions and roles of each module in the above-mentioned device can be found in the implementation process of the corresponding steps of the silicon wafer evaluation method in the above embodiments, and will not be repeated here.

[0139] Figure 24 The diagram shown is a block diagram of an electronic device 500 provided in an embodiment of the present invention.

[0140] Reference Figure 24 The electronic device 500 includes a processing component 510, which further includes one or more processors, and memory resources represented by memory 520 for storing instructions, such as application programs, that can be executed by the processing component 510. The application programs stored in memory 520 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processing component 510 is configured to execute instructions to perform the aforementioned silicon wafer evaluation method.

[0141] Electronic device 500 may also include a power supply component configured to perform power management of electronic device 500, a wired or wireless network interface configured to connect electronic device 500 to a network, and an input / output (I / O) interface. Electronic device 500 may operate on an operating system stored in memory 520, such as Windows Server™, Mac OSX™, Unix™, Linux™, FreeBSD™, or similar.

[0142] A non-transitory computer-readable storage medium, wherein when the instructions in the storage medium are executed by the processor of the aforementioned electronic device 500, the electronic device 500 is able to perform the aforementioned silicon wafer evaluation method.

[0143] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0144] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0145] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0146] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0147] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0148] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program verification codes, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0149] Furthermore, it should be noted that the combination of the various technical features in this case is not limited to the combination methods described in the claims of this case or the combination methods described in the specific embodiments. All technical features described in this case can be freely combined or combined in any way, unless they contradict each other.

[0150] It should be noted that the above examples are merely specific embodiments of the present invention, and the present invention is obviously not limited to the above embodiments, with many similar variations. All modifications that can be directly derived or conceived by those skilled in the art from the content disclosed in this invention should fall within the protection scope of this invention.

[0151] It should be understood that the terms "first," "second," etc., mentioned in the embodiments of the present invention are merely for the purpose of more clearly describing the use of the technical solutions in the embodiments of the present invention, and are not intended to limit the scope of protection of the present invention.

[0152] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for evaluating silicon wafers, characterized in that, include: Obtain the contour data of the silicon wafer to be evaluated in the cutting direction after wire cutting; Based on the contour data, mechanical evaluation parameters are determined, which characterize the mechanical response of the silicon wafer to be evaluated during pressure processing. The mechanical evaluation parameters are compared with preset thresholds to obtain the comparison results; Based on the comparison results, the evaluation results for the nano-morphology quality of the silicon wafer to be evaluated are determined and output.

2. The method according to claim 1, characterized in that, The determination of mechanical evaluation parameters based on the contour data includes: Based on the contour data, a static model of the silicon wafer to be evaluated is constructed to obtain the silicon wafer model; Contact simulation during the pressure processing is performed based on the silicon wafer model to obtain contact results, which include the contact pressure on multiple nodes on the surface of the silicon wafer model. Based on the contact results, the mechanical evaluation parameters are determined.

3. The method according to claim 2, characterized in that, Determining the mechanical evaluation parameters based on the contact results includes: The nodes with a contact pressure of 0 among the plurality of nodes are identified as non-contact nodes; Calculate the ratio of the number of uncontacted nodes to the number of multiple nodes to obtain the proportion of uncontacted area corresponding to the silicon wafer model; The percentage of non-contact area is determined as the mechanical evaluation parameter.

4. The method according to claim 3, characterized in that, The preset threshold includes a ratio threshold, and the determination and output of the evaluation result for the nano-morphology quality of the silicon wafer to be evaluated based on the comparison result includes: If the comparison result indicates that the proportion of the non-contact area is less than the proportion threshold, then the evaluation result indicates that the nano-morphological quality of the silicon wafer to be evaluated meets the preset quality requirements.

5. The method according to claim 2, characterized in that, The step of constructing a static model of the silicon wafer to be evaluated based on the contour data to obtain a silicon wafer model includes: The contour data is fitted with a polynomial to obtain a first fitting function; The first curve corresponding to the first fitting function is magnified by a specified factor and then translated by a specified distance, and the trajectory of the first curve during the translation process is determined as the first surface; A second surface is extracted from the first surface according to a specified cut area, and the second surface is determined as the silicon wafer model.

6. The method according to claim 2, characterized in that, The silicon wafer model includes a constraint section, which includes a first constraint point and a second constraint point. The first constraint point is set at the first corner point in the infeed direction of the silicon wafer model, and is used to constrain the translational degree of freedom of the first corner point in the infeed direction; The second constraint point is set at the second corner point in the target direction of the silicon wafer model, and is used to constrain the translational degree of freedom of the second corner point in the target direction, wherein the target direction is perpendicular to the infeed direction.

7. The method according to claim 1, characterized in that, The determination of mechanical evaluation parameters based on the contour data includes: The contour data is fitted using a first-order polynomial to obtain a second fitting function; The second curve corresponding to the second fitting function is de-sloped to obtain the de-sloped second curve. The second curve after deskewing is subjected to double Gaussian low-pass filtering to obtain the main contour and corrugation contour of the silicon wafer to be evaluated. Determine the first curvature energy corresponding to the main body contour and the second curvature energy corresponding to the wavy contour; The first curvature energy and the second curvature energy are determined as the mechanical evaluation parameters.

8. The method according to claim 7, characterized in that, Determining the first curvature energy corresponding to the main body contour and the second curvature energy corresponding to the wavy contour includes: The main body contour is subjected to a second difference process to obtain a first difference curve, and the wavy contour is subjected to a second difference process to obtain a second difference curve. Based on the specified dividing radius, the first difference curve is divided into a first sub-difference curve corresponding to the central region and a second sub-difference curve corresponding to the edge region; Based on the specified dividing radius, the second difference curve is divided into a third sub-difference curve corresponding to the central region and a fourth sub-difference curve corresponding to the edge region; Calculate the first sub-curvature energy corresponding to the first sub-difference curve, the second sub-curvature energy corresponding to the second sub-difference curve, the third sub-curvature energy corresponding to the third sub-difference curve, and the fourth sub-curvature energy corresponding to the fourth sub-difference curve; The first sub-curvature energy and the second sub-curvature energy are determined as the first curvature energy, and the third sub-curvature energy and the fourth sub-curvature energy are determined as the second curvature energy.

9. The method according to claim 8, characterized in that, The calculation of the first sub-curvature energy corresponding to the first sub-difference curve, the second sub-curvature energy corresponding to the second sub-difference curve, the third sub-curvature energy corresponding to the third sub-difference curve, and the fourth sub-curvature energy corresponding to the fourth sub-difference curve includes: The curvatures of the first sub-difference curve, the second sub-difference curve, the third sub-difference curve, and the fourth sub-difference curve are respectively squared, summed, and logarithmized to obtain the energy of the first sub-curvature, the energy of the second sub-curvature, the energy of the third sub-curvature, and the energy of the fourth sub-curvature.

10. The method according to claim 9, characterized in that, The preset threshold includes a curvature energy threshold, and the evaluation result for the nanostructure quality of the silicon wafer to be evaluated, determined and output based on the comparison result, includes: If the comparison result indicates that at least one of the energy curvatures of the first sub-curvature energy, the second sub-curvature energy, the third sub-curvature energy, and the fourth sub-curvature energy is less than its corresponding curvature energy threshold, then the evaluation result indicates that the nanomorphic quality of the silicon wafer to be evaluated meets the preset quality requirements.

11. The method according to claim 10, characterized in that, The process of determining and outputting the evaluation result for the nanostructure quality of the silicon wafer to be evaluated based on the comparison result includes: If the first sub-curvature energy is less than -3, then the evaluation result indicates that the nano-morphological quality of the silicon wafer to be evaluated meets the preset quality requirements. Alternatively, if the second sub-curvature energy is less than -2.5, then the evaluation result indicates that the nano-morphological quality of the silicon wafer to be evaluated meets the preset quality requirements. Alternatively, if the first sub-curvature energy is less than -3 and the second sub-curvature energy is less than -2.5, then the evaluation result indicates that the nano-morphological quality of the silicon wafer to be evaluated meets the preset quality requirements.

12. A method for manufacturing a silicon wafer, characterized in that, include: Obtain the contour data of the silicon wafer in the cutting direction after wire cutting process; Based on the contour data, mechanical evaluation parameters are determined, which characterize the mechanical response of the silicon wafer during pressure processing. The mechanical evaluation parameters are compared with preset thresholds to obtain the comparison results; Based on the comparison results, an evaluation result for the nanostructure quality of the silicon wafer is determined and output. If the evaluation results indicate that the nano-morphology quality of the silicon wafer does not meet the preset quality requirements, the process parameters of the wire cutting process are adjusted based on the comparison results, so that the silicon wafer is manufactured based on the adjusted wire cutting process.

13. The method according to claim 12, characterized in that, The adjustment of the process parameters of the wire EDM process based on the comparison results includes: The target area of ​​the silicon wafer is determined based on the comparison results. The target area is the area of ​​the silicon wafer that is difficult to flatten during the pressure processing. The temperature of the coolant applied to the target area during the wire cutting process is adjusted.

14. A silicon wafer, characterized in that, The silicon wafer is manufactured by the silicon wafer manufacturing method as described in claim 12 or 13, wherein the intermediate state of the silicon wafer after wire cutting has the following process parameters: the first sub-curvature energy is less than -3, and the second sub-curvature energy is less than -2.

5. Wherein, the first sub-curvature energy is the curvature energy corresponding to the central region of the main contour obtained after the silicon wafer is cut online, and the second sub-curvature energy is the curvature energy corresponding to the edge region of the main contour obtained after the silicon wafer is cut online.

15. The silicon wafer according to claim 14, characterized in that, The final product parameters of the silicon wafer meet the following requirement: the height of the surface nanomorphology measured in a 10mm × 10mm area is less than 15nm.

16. A silicon wafer evaluation device, characterized in that, include: The acquisition module is used to acquire the contour data of the silicon wafer to be evaluated in the cutting direction after wire cutting; The determination module is used to determine mechanical evaluation parameters based on the contour data, wherein the mechanical evaluation parameters characterize the mechanical response of the silicon wafer to be evaluated during the pressure processing process; The comparison module is used to compare the mechanical evaluation parameters with a preset threshold to obtain the comparison result; The evaluation module is used to determine and output the evaluation results of the nano-morphology quality of the silicon wafer to be evaluated based on the comparison results.

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