Printed wiring board

Abstract

The printed wiring board disclosed herein comprises a first base film, a first wiring, an adhesive layer, a second base film, and a seed layer. The first wiring is disposed on the first base film. The adhesive layer is disposed on the first base film to cover the first wiring. The second base film is disposed on the adhesive layer. The seed layer is disposed on the second base film. Through-holes are formed in the adhesive layer, the second base film, and the seed layer, exposing a portion of the first wiring. The seed layer is made of a zinc-containing nickel-chromium alloy. In the seed layer located on the inner wall surface of the through-hole, the zinc concentration in the constituent material of the seed layer is 5 atomic% or more. The seed layer has a main surface opposite the second base film. The surface roughness of the main surface is 1.5 μm or less.

Description

Technical Field

[0001] This disclosure relates to printed wiring boards. This application claims priority based on Japanese Patent Application No. 2023-185588, filed October 30, 2023. All descriptions of that Japanese patent application are incorporated herein by reference. Background Technology

[0002] Printed wiring boards have a base film and wiring disposed on the base film. To enable multi-layer wiring, a substrate is sometimes laminated on the printed wiring board. More specifically, an adhesive layer is disposed on the base film to cover the wiring, and a substrate is disposed on the adhesive layer.

[0003] The substrate described in Japanese Patent Application Publication No. 2005-48269 (Patent Document 1) has an insulating layer, a rust-preventive treatment layer disposed on the insulating layer, and a copper layer disposed on the rust-preventive treatment layer.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2005-48269 Summary of the Invention

[0007] The printed wiring board disclosed herein comprises a first base film, a first wiring, an adhesive layer, a second base film, and a seed layer. The first wiring is disposed on the first base film. The adhesive layer is disposed on the first base film to cover the first wiring. The second base film is disposed on the adhesive layer. The seed layer is disposed on the second base film. Through-holes are formed in the adhesive layer, the second base film, and the seed layer, exposing a portion of the first wiring. The seed layer is made of a zinc-containing nickel-chromium alloy. In the seed layer located on the inner wall surface of the through-hole, the zinc concentration in the constituent material of the seed layer is 5 atomic% or more. The seed layer has a main surface opposite the second base film. The surface roughness of the main surface is 1.5 μm or less. Attached Figure Description

[0008] Figure 1 This is a top view of the printed wiring board 100.

[0009] Figure 2 From and Figure 1 A top view of the printed wiring board 100 as seen from the opposite side.

[0010] Figure 3 This is a top view of the printed wiring board 100 with the adhesive layer 30, base film 40, and wiring 50 omitted.

[0011] Figure 4 yes Figure 1 The cross-sectional view at point IV-IV.

[0012] Figure 5 This is a manufacturing process diagram of the printed wiring board 100.

[0013] Figure 6 This is a cross-sectional view illustrating the conductive layer formation process S2.

[0014] Figure 7 This is a cross-sectional view illustrating the resist pattern formation process S3.

[0015] Figure 8 This is a cross-sectional diagram illustrating the electroplating process S4.

[0016] Figure 9 This is a cross-sectional view illustrating the resist pattern removal process S5.

[0017] Figure 10 This is a cross-sectional view used to illustrate etching process S6.

[0018] Figure 11 This is a cross-sectional view illustrating the substrate bonding process S7.

[0019] Figure 12 This is a cross-sectional view illustrating the through-hole forming process S8.

[0020] Figure 13 This is a cross-sectional view illustrating the conductive layer formation process S9.

[0021] Figure 14 This is a cross-sectional view illustrating the resist pattern formation process S10.

[0022] Figure 15 This is a cross-sectional diagram illustrating the electroplating process S11.

[0023] Figure 16 This is a cross-sectional view illustrating the resist pattern removal process S12.

[0024] Figure 17 This is a cross-sectional view of a modified example 1 of the printed wiring board 100.

[0025] Figure 18 This is a cross-sectional view of the printed wiring board 100A.

[0026] Figure 19 This is an enlarged cross-sectional view of the printed wiring board 100A near the inner wall surface of the through hole 40a.

[0027] Figure 20 This is an enlarged cross-sectional view of the printed wiring board 100 near the inner wall surface of the through hole 40a. Detailed Implementation

[0028] [The technical problem this disclosure aims to solve]

[0029] When the substrate described in Patent Document 1 is laminated to achieve multi-layer wiring, through-holes are formed in the adhesive layer, insulating layer, anti-rust treatment layer, and copper layer to expose a portion of the wiring. However, in this case, a protrusion made of the anti-rust treatment layer sometimes remains on the inner wall surface of the through-hole. Such protrusions can reduce the reliability of the multi-layer wiring.

[0030] The printed wiring board disclosed herein was made in view of the problems of the prior art as described above. More specifically, this disclosure provides a printed wiring board capable of improving the reliability of multilayer wiring.

[0031] [The Effects of This Disclosure]

[0032] The printed wiring board according to this disclosure can improve the reliability of multi-layered wiring.

[0033] [Description of embodiments of this disclosure]

[0034] First, embodiments of this disclosure will be described.

[0035] (1) A printed wiring board according to one embodiment includes a first base film, a first wiring, an adhesive layer, a second base film, and a seed layer. The first wiring is disposed on the first base film. The adhesive layer is disposed on the first base film to cover the first wiring. The second base film is disposed on the adhesive layer. The seed layer is disposed on the second base film. Through holes are formed in the adhesive layer, the second base film, and the seed layer to expose a portion of the first wiring. The seed layer is made of a zinc-containing nickel-chromium alloy. In the seed layer located on the inner wall surface of the through hole, the zinc concentration in the seed layer's constituent material is 5 atomic% or more. The seed layer has a main surface opposite to the second base film. The surface roughness of the main surface is 1.5 μm or less. According to the printed wiring board of (1) above, the reliability between multilayer wirings can be improved.

[0036] (2) In the printed wiring board of (1) above, there may also be a protrusion made of a seed layer on the inner wall surface of the through hole. Alternatively, the height of the protrusion may be 2.0 μm or less. According to the printed wiring board of (2) above, the reliability of multilayer wiring can be improved.

[0037] (3) In the printed wiring board of (1) or (2) above, the zinc concentration in the constituent material of the seed layer may also be 0.42 μg / cm³. 2 above.

[0038] (4) Alternatively, the printed wiring board of (1) to (3) above may also have a second wiring, which has a seed layer, a conductive layer disposed on the seed layer, and an electrolytic plating layer disposed on the conductive layer.

[0039] (5) In the printed wiring board described in (1) to (4) above, the first wiring may have a first coil portion that is wound into a vortex shape when viewed from above, and the second wiring may have a second coil portion that is wound into a vortex shape when viewed from above. The first wiring may have a top surface. The thickness of the adhesive layer between the top surface and the second base film may be 1 μm or more and 50 μm or less. The thickness of the second base film may be 1 μm or more and 35 μm or less. According to the printed wiring board described in (5) above, the reliability between multilayer wirings can be improved while improving the performance of the coil device.

[0040] [Details of the embodiments of this disclosure]

[0041] Details of embodiments of this disclosure will be described with reference to the accompanying drawings. In the following drawings, the same or equivalent parts will be labeled with the same reference numerals, and repeated descriptions will not be provided. The printed wiring board involved in the embodiments will be designated as printed wiring board 100.

[0042] <Composition of Printed Wiring Board 100>

[0043] The following describes the structure of the printed wiring board 100.

[0044] Figure 1 This is a top view of the printed wiring board 100. Figure 2 From and Figure 1 A top view of the printed wiring board 100 as seen from the opposite side. Figure 3 This is a top view of the printed wiring board 100 with the adhesive layer 30, base film 40, and wiring 50 omitted. Figure 4 yes Figure 1 The cross-sectional view at point IV-IV. (See diagram below.) Figures 1 to 4 As shown, the printed wiring board 100 has a base film 10, wiring 20 and wiring 21, adhesive layer 30 and adhesive layer 31, base film 40, wiring 50 and base film 60.

[0045] The base film 10 has a main surface 10a and a main surface 10b. Main surfaces 10a and 10b are end faces of the base film 10 in the thickness direction. Main surface 10b is the surface opposite to main surface 10a. The base film 10 is made of a flexible, electrically insulating material. For example, the base film 10 is made of polyimide.

[0046] Wiring 20 is disposed on the main surface 10a. Wiring 20 has a coil portion 20a. The coil portion 20a is formed by winding the wiring 20 into a spiral shape when viewed from above. Wiring 21 is disposed on the main surface 10b. Wiring 21 has a coil portion 21a. The coil portion 21a is formed by winding the wiring 21 into a spiral shape when viewed from above.

[0047] The first end and the second end of wiring 20 are located at the outermost and innermost circumferences of coil portion 20a, respectively. The first end and the second end of wiring 21 are located at the innermost and outermost circumferences of coil portion 21a, respectively.

[0048] Wiring 20 and wiring 21 each have a seed layer 22, a conductive layer 23, and an electroplated layer 24. The seed layer 22 is disposed on the main surfaces (main surfaces 10a and 10b) of the base film 10. The material constituting the seed layer 22 is, for example, a nickel-chromium alloy.

[0049] A conductive layer 23 is disposed on a seed layer 22. A through-hole 10c (not shown) is formed on a base film 10, a seed layer 22 located at the second end of a wiring 20, and a seed layer 22 located at the first end of a wiring 21. In addition to being formed on the seed layer 22, the conductive layer 23 is also formed on the inner wall surface of the through-hole 10c.

[0050] The conductive layer 23 is made of, for example, copper. An electroplated layer 24 is disposed on the conductive layer 23. The electroplated layer 24 is also made of, for example, copper. The second end of the wiring 20 and the first end of the wiring 21 are electrically connected to each other through the conductive layer 23 and the electroplated layer 24 disposed on the inner wall surface of the through hole 10c.

[0051] Adhesive layer 30 is disposed on main surface 10a in a manner that covers wiring 20. Adhesive layer 31 is disposed on main surface 10b in a manner that covers wiring 21. The constituent materials of adhesive layer 30 and adhesive layer 31 are, for example, epoxy-based adhesives.

[0052] A base film 40 is disposed on the adhesive layer 30. The base film 40 is made of a flexible, electrically insulating material. For example, the base film 40 is made of polyimide. The wiring 20 has a top surface 20b. The thickness of the adhesive layer 30 located between the top surface 20b and the base film 40 is defined as thickness T. Thickness T can be 1 μm or more and 50 μm or less. Thickness T can also be 1 μm or more and 5 μm or less. The thickness of the base film 40 is defined as thickness T1. Thickness T1 is, for example, 1 μm or more and 35 μm or less. Thickness T1 can be 5 μm or more and 25 μm or less, or 12 μm or more and 18 μm or less.

[0053] Wiring 50 is disposed on base film 40. Wiring 50 has coil portion 50a. Coil portion 50a is formed by winding wiring 50 into a spiral shape when viewed from above.

[0054] The wiring 50 has a seed layer 51, a copper layer 52, a conductive layer 53, and an electroplated layer 54. The seed layer 51 is disposed on the base film 40. The material constituting the seed layer 51 is a nickel-chromium alloy containing zinc. The zinc concentration in the material constituting the seed layer 51 is, for example, 0.42 μg / cm³. 2The zinc concentration in the constituent materials of the seed layer 51 was determined as follows. First, a piece of wiring 50 of arbitrary size was cut. Next, the cut wiring 50 was treated with a mixture of 80 g / L hydrogen peroxide and 60 g / L sulfuric acid to remove the copper layers (copper layer 52, conductive layer 53, electroplated layer 54), exposing the seed layer 51. Then, the exposed seed layer 51 was dissolved in 10 g / L hydrochloric acid, and the hydrochloric acid containing the seed layer 51 was analyzed by ICP (Inductively Coupled Plasma) to determine the zinc concentration in the constituent materials of the seed layer 51.

[0055] The seed layer 51 has a main surface 51a and a main surface 51b. Main surfaces 51a and 51b are end faces in the thickness direction of the seed layer 51. Main surface 51a is opposite to the base film 40. Main surface 51b is the surface opposite to main surface 51a. The surface roughness of main surface 51a is 1.5 μm or less. For example, the surface roughness of main surface 51a can be 1.3 μm or less, or 1.1 μm or less. The surface roughness of main surface 51a is measured by the following method: First, a cross-sectional image is acquired using a scanning electron microscope (SEM). Second, a straight line parallel to the interface between the seed layer 51 and the base film 40 is drawn on the acquired cross-sectional image. In the case where there are microscopic irregularities at the interface between the seed layer 51 and the base film 40, the average line of the cross-sectional curve of that interface is this straight line. It should be noted that the average line is a straight line drawn in such a way that the area divided by the average line and the portion of the cross-sectional curve above the average line is equal to the area divided by the average line and the portion of the cross-sectional curve below the average line. Third, calculate the maximum and minimum values ​​of the distance between this line and the main surface 51a. The difference between this maximum and minimum value is the surface roughness of the main surface 51a.

[0056] A copper layer 52 is disposed on the seed layer 51. The copper layer 52 is made of copper. A conductive layer 53 is disposed on the seed layer 51, with the copper layer 52 in between. The conductive layer 53 is also made of copper, for example. The wiring 50 may also not have a copper layer 52. In this case, the conductive layer 53 is disposed directly above the seed layer 51.

[0057] The first and second ends of the wiring 50 are located at the outermost and innermost circumferences of the coil portion 50a, respectively. A through-hole 40a is formed on the adhesive layer 30, the base film 40, and the seed layer 51 and copper layer 52 located at the first end of the wiring 50. The wiring 20 is partially exposed from the through-hole 40a (more specifically, the top surface 20b of the first end of the wiring 20 is exposed). A conductive layer 53 is also formed on the top surface 20b exposed from the through-hole 40a and on the inner wall surface of the through-hole 40a. The zinc concentration in the constituent material of the seed layer 51 on the inner wall surface of the through-hole 40a is, for example, 5 atomic% or more. The zinc concentration in the constituent material of the seed layer 51 on the inner wall surface of the through-hole 40a can be 10 atomic% or more, or 20 atomic% or more. The zinc concentration in the constituent material of the seed layer 51 on the inner wall surface of the through-hole 40a was determined by cross-sectional observation using a transmission electron microscope (TEM) and EDX (Energy Dispersive X-ray Spectroscopy) analysis during the cross-sectional observation. The measurement range was set to a distance of 5 μm from the inner wall surface of the through-hole 40a in the plane direction of the substrate (the plane direction of the base film 40).

[0058] An electroplated layer 54 is disposed on the conductive layer 53. The second end of the wiring 20 and the first end of the wiring 50 are electrically connected to each other through the conductive layer 53 and the electroplated layer 54 disposed on the inner wall surface of the through hole 40a and on the top surface 20b exposed from the through hole 40a. The electroplated layer 54 is made of, for example, copper.

[0059] The base film 60 is disposed on the adhesive layer 31. The base film 60 is made of a flexible, electrically insulating material. For example, the base film 60 is made of polyimide.

[0060] <Manufacturing Method of Printed Wiring Board 100>

[0061] The following describes the manufacturing method of the printed wiring board 100.

[0062] Figure 5 This is a manufacturing process diagram of printed wiring board 100. (Example) Figure 5 As shown, the manufacturing method of the printed wiring board 100 includes a preparation step S1, a conductive layer formation step S2, a resist pattern formation step S3, an electrolytic plating step S4, a resist pattern removal step S5, an etching step S6, a substrate bonding step S7, a through-hole formation step S8, a conductive layer formation step S9, a resist pattern formation step S10, an electrolytic plating step S11, a resist pattern removal step S12, and an etching step S13.

[0063] In preparation step S1, a base film 10 is prepared. In the base film 10 prepared in preparation step S1, seed layers 22 are disposed on the main surface 10a and the main surface 10b. Before the conductive layer formation step S2, through holes 10c are formed in the seed layers 22 disposed on the main surface 10a and the main surface 10b.

[0064] Figure 6 This is a cross-sectional view illustrating the conductive layer formation process S2. For example... Figure 6 As shown, in the conductive layer formation step S2, a conductive layer 23 is formed on the seed layer 22. The conductive layer 23 is formed, for example, by electroless plating or sputtering. Although not shown, the conductive layer 23 is also formed on the inner wall surface of the through hole 10c.

[0065] Figure 7 This is a cross-sectional view illustrating the resist pattern formation process S3. For example... Figure 7 As shown, in the resist pattern forming process S3, a resist pattern 25 is formed on the conductive layer 23. The resist pattern 25 has an opening 25a. The conductive layer 23 is exposed through the opening 25a. The resist pattern 25 is formed, for example, by adhering a dry film resist to the conductive layer 23 and exposing and developing the adhering dry film resist.

[0066] Figure 8 This is a cross-sectional diagram illustrating the S4 electroplating process. For example... Figure 8 As shown, in the electroplating process S4, an electroplating layer 24 is formed on the conductive layer 23 exposed from the opening 25a by electroplating. Figure 9 This is a cross-sectional view illustrating the resist pattern removal process S5. For example... Figure 9 As shown, in the resist pattern removal process S5, the resist pattern 25 is removed from the conductive layer 23.

[0067] Figure 10 This is a cross-sectional view used to illustrate etching process S6. For example... Figure 10 As shown, in the etching process S6, the conductive layer 23 and the seed layer 22 located under the resist pattern 25 are removed by etching.

[0068] Figure 11 This is a cross-sectional view illustrating the substrate bonding process S7. For example... Figure 11 As shown, in the substrate bonding step S7, the substrate 70 is bonded to the base film 10 via the adhesive layer 30. In the substrate bonding step S7, firstly, the substrate 70 is prepared. The substrate 70 has a base film 40, a seed layer 51 disposed on the base film 40, and a copper layer 52 disposed on the seed layer 51. It should be noted that if the wiring 50 does not have a copper layer 52, the copper layer 52 is peeled off at this stage.

[0069] In the substrate bonding process S7, secondly, with the uncured adhesive layer 30 between the substrate 70 and the base film 10, pressure is applied to the substrate 70 toward the base film 10. At this time, heating is also performed. As a result, the adhesive layer 30 cures, and the substrate 70 (base film 40) is bonded to the base film 10. In the same manner, the base film 60 is bonded to the base film 10 via the adhesive layer 31 in the substrate bonding process S7.

[0070] Figure 12 This is a cross-sectional view illustrating process S8, which involves forming a through hole. For example... Figure 12 As shown, in the through-hole forming process S8, a through-hole 40a is formed in the adhesive layer 30, the base film 40, the seed layer 51, and the copper layer 52. The through-hole 40a is formed by irradiation with a laser. As a result, the top surface 20b located at the first end of the wiring 20 is exposed through the through-hole 40a.

[0071] Figure 13 This is a cross-sectional view illustrating the conductive layer formation process S9. For example... Figure 13 As shown, in the conductive layer formation process S9, a conductive layer 53 is formed on the copper layer 52. The conductive layer 53 is formed, for example, by electroless plating or sputtering. The conductive layer 53 is also formed on the inner wall surface of the through hole 40a and on the top surface 20b exposed from the through hole 40a.

[0072] Figure 14 This is a cross-sectional view illustrating the resist pattern formation process S10. For example... Figure 14 As shown, in the resist pattern forming process S10, a resist pattern 55 is formed on the conductive layer 53. The resist pattern 55 has an opening 55a. The conductive layer 53 is exposed through the opening 55a. The resist pattern 55 is formed, for example, by adhering a dry film resist to the conductive layer 53 and exposing and developing the adhering dry film resist.

[0073] Figure 15 This is a cross-sectional diagram illustrating the electroplating process S11. For example... Figure 15 As shown, in the electroplating process S11, an electroplating layer 54 is formed on the conductive layer 53 exposed from the opening 55a by electroplating.

[0074] Figure 16 This is a cross-sectional view illustrating the resist pattern removal process S12. For example... Figure 16 As shown, in the resist pattern removal process S12, the resist pattern 55 is removed from the conductive layer 53. In the etching process S13, the conductive layer 53, copper layer 52, and seed layer 51 located below the resist pattern 55 are removed by etching. Through the above processes, a resist pattern 55 is formed. Figures 1 to 4 The printed wiring board 100 with the structure shown is shown.

[0075] <Variation Example 1>

[0076] Figure 17 This is a cross-sectional view of a modified example 1 of the printed wiring board 100. Figures 1 to 4 The image shows an example of wiring 21 configured on the main surface 10b, but as... Figure 17 As shown, wiring 21 can also be disposed on the main surface (main surface 60a) of the base film 60 opposite to the main surface 10b. In this case, two single-sided panels (a single-sided panel with wiring 20 disposed on the main surface 10a and a single-sided panel with wiring 21 disposed on the main surface 60a) are continuously stacked in the thickness direction.

[0077] <Variation Example 2>

[0078] Figures 1 to 4 The example shown has three wiring layers, but the printed wiring board 100 can have two or more wiring layers, or even five or more. The printed wiring board 100 can be constructed from a combination of double-sided and single-sided boards, or from a combination of multiple single-sided boards. It should be noted that a double-sided board refers to a case where wiring is arranged on both main surfaces of a base film. Figures 1 to 4 In the example shown, the base film 10, wiring 20 and wiring 21 form a double-sided panel.

[0079] <Effect of Printed Wiring Board 100>

[0080] The effect of the printed wiring board 100 will be explained below by comparing it with the printed wiring board involved in the comparative example. The printed wiring board involved in the comparative example is referred to as printed wiring board 100A.

[0081] Figure 18 This is a cross-sectional view of the printed wiring board 100A. Figure 19 This is an enlarged cross-sectional view of the printed wiring board 100A near the inner wall surface of the through hole 40a. (See image below.) Figure 18 and Figure 19 As shown, the printed wiring board 100A has a base film 10, wiring 20 and wiring 21, adhesive layer 30 and adhesive layer 31, base film 40, wiring 50 and base film 60. In this respect, the structure of the printed wiring board 100A is the same as that of the printed wiring board 100.

[0082] In the printed wiring board 100A, the zinc concentration in the constituent material of the seed layer 51 is less than 0.42 μg / cm³. 2 In the printed wiring board 100A, the surface roughness of the main surface 51a exceeds 1.5 μm. In the printed wiring board 100A, a protrusion 40aa exists on the inner wall surface of the through hole 40a. The protrusion 40aa is formed by a seed layer 51. Regarding these points, the configuration of the printed wiring board 100A differs from that of the printed wiring board 100.

[0083] In the through-hole forming process S8, as described above, the through-hole 40a is formed by irradiating with a laser. To minimize damage to the wiring 20 (top surface 20b), the laser intensity needs to be set relatively low. As a result, the processing of the poorly machinable nickel-chromium alloy seed layer 51 becomes insufficient, sometimes resulting in a protrusion 40aa forming on the inner wall surface of the through-hole 40a. If the conductive layer forming process S9 and the electroplating process S11 are performed with the protrusion 40aa formed on the inner wall surface of the through-hole 40aa, a void will form near the protrusion 40aa. This void can reduce the reliability of the connection between the wiring 20 and the wiring 50.

[0084] On the other hand, by making the surface roughness of the main surface 51a less than 1.5 μm, the processability of the seed layer 51 is improved. Furthermore, in the printed wiring board 100, the zinc concentration in the constituent material of the seed layer 51 is made to be 0.42 μg / cm³. 2 As a result, the melting point of the constituent material of the seed layer 51 is reduced, and the processability of the seed layer 51 is also improved. Consequently, in the printed wiring board 100, it is less likely to form a protrusion 40aa on the inner wall surface of the through hole 40a.

[0085] Figure 20 This is an enlarged cross-sectional view of the printed wiring board 100 near the inner wall surface of the through hole 40a. (See image below.) Figure 20 As shown, in the printed wiring board 100, the processability of the seed layer 51 is improved, resulting in a smaller protrusion height (height H) of the protrusion 40aa even when a protrusion 40aa is formed on the inner wall surface of the through hole 40a. Height H is the difference in height between the inner wall surface of the through hole 40a located at the base film 40 and the inner wall surface of the through hole 40a located at the seed layer 51. In the printed wiring board 100, height H can be 2.0 μm or less, or height H can be 1.5 μm or less. Furthermore, in the printed wiring board 100, height H can be 0 μm, height H can be 0.2 μm or more, or height H can be 0.3 μm or more. It should be noted that height H is measured using a cross-sectional image obtained using SEM.

[0086] In this way, in the printed wiring board 100, the protrusion 40aa will not be formed on the inner wall surface of the through hole 40a or the height H will be reduced. As a result, it is not easy to form a gap near the protrusion 40aa, and the connection reliability between the wiring 20 and the wiring 50 is improved.

[0087] In the printed wiring board 100, the smaller the thickness T, the smaller the distance between the coil portion 20a and the coil portion 50a, and the stronger the magnetic flux generated by the printed wiring board 100, thus improving the performance of the printed wiring board 100 as a coil device. On the other hand, the larger the thickness T, the more necessary it is to reduce the intensity of the laser when forming the through hole 40a, thus making it easier to form the protrusion 40aa. Therefore, when the thickness T is 1 μm or more and 50 μm or less, it is possible to improve the performance as a coil device while also improving the connection reliability between the wiring 20 and the wiring 50.

[0088] <Evaluation of Connection Reliability>

[0089] Samples 1 to 8 were prepared to assess the connection reliability. As shown in Table 1, the zinc concentration in the constituent material of the seed layer 51 on the inner wall surface of the through hole 40a varied in samples 1 to 4. The surface roughness of the main surface 51a was fixed at 1.5 μm in samples 1 to 4. The surface roughness of the main surface 51a varied in samples 5 to 8. The zinc concentration in the constituent material of the seed layer 51 on the inner wall surface of the through hole 40a was fixed at 5 atomic percent in samples 5 to 8. As a result, the height H varied in samples 1 to 8.

[0090]

[0091] The zinc concentration in the constituent material of the seed layer 51 on the inner wall surface of the through hole 40a is 5 atomic% or more (0.42 μg / cm³). 2 (The above) is taken as condition A, and the surface roughness of the main surface 51a is taken as condition B. In samples 3, 4, and 6 to 8, both conditions A and B are satisfied. On the other hand, in samples 1, 2, and 5, neither condition A nor condition B is satisfied. In samples 3, 4, and 6 to 8, the height H is 2.0 μm or less. On the other hand, in samples 1, 2, and 5, the height H exceeds 2.0 μm. This comparison shows that by satisfying conditions A and B, the processability of the seed layer 51 is improved, and the height H is reduced.

[0092] The reliability of the connection between wiring 20 and wiring 50 was evaluated by subjecting samples 1 to 8 to thermal cycling tests and observing for cracks after the tests. The thermal cycling tests were conducted according to the method specified in IEC 60068-2-14-Na. During the thermal cycling, the high-temperature setting was 85°C, and the low-temperature setting was -40°C. The thermal cycles were repeated 100 times. The results of the thermal cycling tests are shown in Table 1. In Table 1, a result where the resistivity change after the thermal cycling test is within ±10% of the resistivity before the test is rated as "A", and a result where the resistivity change after the thermal cycling test is not within ±10% of the resistivity before the test is rated as "B".

[0093] The thermal cycling test results of samples 3, 4, and 6 through 8 are superior to those of samples 1, 2, and 5. This comparison shows that by satisfying conditions A and B, the height H decreases, making it less likely for gaps to form near the protrusion 40aa, thus improving the reliability of the connection between wiring 20 and wiring 50.

[0094] It should be understood that the embodiments disclosed herein are illustrative in all respects and not restrictive. The scope of the invention is set forth not by the above embodiments but by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0095] Explanation of reference numerals in the attached figures

[0096] 10: Base film; 10a: Main surface; 10b: Main surface; 10c: Through hole; 20: Wiring; 20a: Coil portion; 20b: Top surface; 21: Wiring; 21a: Coil portion; 22: Seed layer; 23: Conductive layer; 24: Electrolytic plating layer; 25: Resist pattern; 25a: Opening; 30: Adhesive layer; 31: Adhesive layer; 40: Base film; 40a: Through hole; 40aa: Protrusion; 50: Wiring; 50a: Coil portion; 51: Seed layer; 51a: Main surface; 51b: Main surface; 52: Copper layer; 53: Conductive layer; 54: Electrolytic plating layer; 55: Resist Pattern; 55a: Opening; 60: Base film; 60a: Main surface; 70: Substrate; 100, 100A: Printed wiring board; H: Height; S1: Preparation process; S2: Conductive layer formation process; S3: Resist pattern formation process; S4: Electroplating process; S5: Resist pattern removal process; S6: Etching process; S7: Substrate bonding process; S8: Through-hole formation process; S9: Conductive layer formation process; S10: Resist pattern formation process; S11: Electroplating process; S12: Resist pattern removal process; S13: Etching process; T, T1: Thickness.

Claims

1. A printed wiring board, comprising: First base film; First wiring; Adhesive layer; Second base membrane; as well as Seed layer, The first wiring is disposed on the first base film. The adhesive layer is disposed on the first base film in a manner that covers the first wiring. The second base film is disposed on the adhesive layer. The seed layer is disposed on the second base film. Through-holes are formed in the adhesive layer, the second base film, and the seed layer to expose a portion of the first wiring. The seed layer is made of a zinc-containing nickel-chromium alloy. In the seed layer located on the inner wall surface of the through hole, the zinc concentration in the constituent material of the seed layer is 5 atomic% or more. The seed layer has a main surface opposite to the second base film. The surface roughness of the main surface is less than 1.5 μm.

2. The printed wiring board according to claim 1, wherein, The inner wall surface of the through hole has a protrusion formed by the seed layer. The height of the protrusion is less than 2.0 μm.

3. The printed wiring board according to claim 1 or 2, wherein, The zinc concentration in the constituent materials of the seed layer is 0.42 μg / cm³. 2 above.

4. The printed wiring board according to any one of claims 1 to 3, wherein, The printed wiring board further includes a second wiring, the second wiring having the seed layer, a conductive layer disposed on the seed layer, and an electrolytic plating layer disposed on the conductive layer.

5. The printed wiring board according to claim 4, wherein, The first wiring and the second wiring each have a first coil portion and a second coil portion that are wound into a vortex shape when viewed from above. The first wiring has a top surface. The thickness of the adhesive layer located between the top surface and the second base film is more than 1 μm and less than 50 μm. The thickness of the second base film is greater than 1 μm and less than 35 μm.

Images