A method and system for implementing loopback testing based on algorithm switching

Abstract

The application provides a method and system for realizing loopback test based on algorithm switching. The method does not require external equipment, and one key can complete the whole process of transmission, collection and analysis. The method can realize integrated self-loopback, reduce operation difficulty, greatly reduce test time, and improve test efficiency. The method uses FPGA dynamic reconfiguration, supports multiple test scenes through algorithm switching, improves test controllability and integration, and reduces hardware cost.

Description

Technical Field

[0001] This application relates to the field of test and measurement technology, and in particular to a method and system for implementing loopback testing based on algorithm switching. Background Technology

[0002] Loopback testing is a technique that verifies the internal functional integrity and communication reliability of a system or device by directly feeding back its output signal to the input.

[0003] Loopback testing is widely used in many fields (such as network communication, hardware debugging, software testing, etc.). Its core function is to quickly locate faults, verify system stability, and reduce dependence on the external environment.

[0004] However, traditional loopback testing has many drawbacks and limitations: it is cumbersome to operate, requiring manual connection of external cables, reflectors, or simulated loads, resulting in high operational complexity; it is inefficient, as the test data generated by the transmitting end needs to be fed back to the receiving end through an external path, and the test cycle is long, requiring waiting for the external equipment to respond; it has poor fault location accuracy, as external links (such as cable loss and electromagnetic interference) may mask the real fault, and external cables introduce wiring errors and noise, making it difficult to focus on the problem of the equipment itself; and it has high testing costs, requiring the purchase of additional testing equipment (such as signal generators and spectrum analyzers), and manual intervention to plug and unplug cables or switch modes. Summary of the Invention

[0005] This application provides a method and system for loopback testing based on algorithm switching, in order to solve the problems of cumbersome operation, low efficiency, poor fault location accuracy, and high testing cost in the traditional loopback testing technology.

[0006] Firstly, this application provides a method for implementing loopback testing based on algorithm switching, including: The host computer writes preset waveform data to the memory chip through the high-speed serial computer expansion bus standard PCIe interface, and sends a start signal to the programmable array logic FPGA module. The waveform generation control module reads the preset waveform data from the memory chip and sends it to the digital-to-analog conversion module, so that the digital-to-analog conversion module outputs a preset analog signal based on the preset waveform data; The analog-to-digital conversion module samples the output preset analog signal to obtain sampled data. The FPGA module receives and parses the sampled data through the analog-to-digital sampling unit and sends it to the analysis module. At the same time, the sampled data is sent to the memory chip for storage. The analysis module extracts features from the sampled data to obtain feature information, and then transmits the feature information back to the host computer through the PCIe interface. The host computer compares the feature information with the target feature information corresponding to the preset waveform data to obtain the comparison result. If the feature information is inconsistent with the target feature information, the internal algorithm of the FPGA module is reconfigured to complete the algorithm switch, and the steps of writing preset waveform data to the memory chip through the high-speed serial computer expansion bus standard PCIe interface and sending a start signal to the programmable array logic FPGA module are reset.

[0007] In one possible implementation, before the host computer writes preset waveform data to the memory chip via the high-speed serial computer expansion bus standard PCIe interface, the method further includes: The host computer sends configuration information to the FPGA through the PCIe interface, so that the FPGA can use the configuration information to complete the initialization configuration.

[0008] In one possible implementation, the host computer writes preset waveform data to the memory chip via a high-speed serial computer expansion bus standard PCIe interface and sends a start signal to the programmable array logic FPGA module, including: The host computer determines the preset waveform data according to the set frequency and the set amplitude, and calls the high-speed serial computer expansion bus standard PCIe interface to write the preset waveform data to the memory chip. Additionally, the host computer sends a start signal to the waveform generation control module of the programmable array logic FPGA module through the PCIe interface.

[0009] In one possible implementation, the waveform generation control module reads the preset waveform data from the memory chip and sends it to the digital-to-analog converter module, so that the digital-to-analog converter module outputs a preset analog signal based on the preset waveform data, including: When the waveform generation control module receives the start signal, it reads the preset waveform data from the memory chip; The waveform generation control module sends the read preset waveform data to the digital-to-analog conversion module; The digital-to-analog conversion module performs digital-to-analog conversion processing based on the preset waveform data to obtain a preset analog signal.

[0010] In one possible implementation, the analog-to-digital conversion module samples the output preset analog signal to obtain sampled data. The FPGA module receives and parses the sampled data through the analog-to-digital sampling unit and sends it to the analysis module. Simultaneously, the sampled data is sent to the memory chip for storage, including: The analog-to-digital conversion module receives the preset analog signal output by the digital-to-analog conversion module and performs sampling processing to obtain sampled data, wherein the sampling processing includes analog-to-digital conversion processing; The FPGA module's analog-to-digital sampling unit receives the sampled data output by the analog-to-digital conversion module; The analog-to-digital sampling unit receives and parses the sampled data. The sampled data is sent to the analysis module for processing via the analog-to-digital sampling unit. And send the sampled data to the memory chip for storage.

[0011] In one possible implementation, the analysis module performs feature extraction on the sampled data to obtain feature information, and transmits the feature information back to the host computer via the PCIe interface, including: The analysis module extracts features from the sampled data to obtain feature information, wherein the feature information includes at least: amplitude, frequency, duty cycle, and rise / fall time; The feature information is transmitted back to the host computer and stored via the PCIe interface.

[0012] In one possible implementation, the host computer compares the feature information with the target feature information corresponding to the preset waveform data to obtain a comparison result, including: The host computer receives the feature information; A preset wave is determined based on preset waveform data, and target feature information is extracted from the preset wave. The feature information is compared with the target feature information to obtain the comparison result.

[0013] In one possible implementation, the step of reconfiguring the internal algorithm of the FPGA module to complete the algorithm switch when the feature information is inconsistent with the target feature information includes: If the feature information is inconsistent with the target feature information, the feature information that is inconsistent will be indicated; The internal algorithm reconfiguration module is activated to reconfigure the internal algorithms of the FPGA module in order to complete the algorithm switching.

[0014] In one possible implementation, the method further includes: If the feature information is completely consistent with the target feature information, the flag of the comparison result is set to a preset value, and the loop closure test is displayed as successful.

[0015] Secondly, this application provides a loopback testing system, comprising: The host computer is used to write preset waveform data to the memory chip through the high-speed serial computer expansion bus standard PCIe interface, and to send a start signal to the programmable array logic FPGA module. A waveform generation control module is used to read the preset waveform data from the memory chip and send it to the digital-to-analog conversion module, so that the digital-to-analog conversion module outputs a preset analog signal based on the preset waveform data. The FPGA module is used to receive and parse the sampled data through the analog-to-digital sampling unit and send it to the analysis module, and at the same time send the sampled data to the memory chip for storage; The analysis module is used to extract features from the sampled data, obtain feature information, and transmit the feature information back to the host computer through the PCIe interface; The host computer is also used to compare the feature information with the target feature information corresponding to the preset waveform data to obtain a comparison result; The internal algorithm reconfiguration module is used to reconfigure the internal algorithm of the FPGA module to complete the algorithm switching when the feature information is inconsistent with the target feature information, and to reset the execution steps of the host computer writing preset waveform data to the memory chip through the high-speed serial computer expansion bus standard PCIe interface and sending a start signal to the programmable array logic FPGA module.

[0016] Compared with the prior art, the technical solution provided in this application has the following advantages: The method provided in this application involves a host computer writing preset waveform data to a memory chip via a high-speed serial computer expansion bus standard PCIe interface, and sending a start signal to a programmable array logic FPGA module; a waveform generation control module reads the preset waveform data from the memory chip and sends it to a digital-to-analog converter module, so that the digital-to-analog converter module outputs a preset analog signal based on the preset waveform data; the analog-to-digital converter module samples the output preset analog signal to obtain sampled data; the FPGA module receives and parses the sampled data through an analog-to-digital sampling unit and sends it to an analysis module, while simultaneously... The sampled data is sent to the memory chip for storage; the analysis module extracts features from the sampled data to obtain feature information, and transmits the feature information back to the host computer via the PCIe interface; the host computer compares the feature information with the target feature information corresponding to the preset waveform data to obtain a comparison result; if the feature information is inconsistent with the target feature information, the internal algorithm of the FPGA module is reconfigured to complete the algorithm switch, and the steps of the host computer writing the preset waveform data to the memory chip via the high-speed serial computer expansion bus standard PCIe interface and sending a start signal to the programmable array logic FPGA module are reset. This achieves a one-click completion of the entire process of transmission, acquisition, and analysis without external devices, enabling integrated transmission and reception with self-loopback, reducing operational difficulty, significantly reducing test time, and improving test efficiency; utilizing FPGA dynamic reconfiguration and algorithm switching to support multiple test scenarios improves test controllability and integration, and reduces hardware costs. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0020] Figure 1A flowchart illustrating an embodiment of a method for implementing loopback testing based on algorithm switching, provided in this application. Figure 2 A flowchart illustrating another embodiment of a method for implementing loopback testing based on algorithm switching, provided in this application. Figure 3 This is a block diagram of an embodiment of a loop closure test system provided in this application. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] The following disclosure provides numerous different embodiments or examples for implementing various structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.

[0023] To address the technical problems of cumbersome, inefficient, and inaccurate fault location, as well as high testing costs, traditional loopback testing methods in existing technologies, this application provides a method for implementing loopback testing based on algorithm switching. This method can improve testing speed, reduce testing costs, and enhance testing controllability through hardware reconfiguration and software algorithm collaboration.

[0024] Figure 1 This is a flowchart illustrating an embodiment of a method for implementing loopback testing based on algorithm switching, provided in this application. Figure 1 As shown, the method includes the following steps: S101: The host computer writes preset waveform data to the memory chip through the high-speed serial computer expansion bus standard PCIe interface, and sends a start signal to the programmable array logic FPGA module.

[0025] This application is mainly used in loopback testing. In multiple fields such as network communication, hardware debugging, and software testing, loopback testing can quickly locate faults, verify system stability, and reduce dependence on the external environment.

[0026] In this embodiment, an electronic device performs a loopback test based on algorithm switching. This electronic device can be a benchtop oscilloscope, and it includes at least: an analog-to-digital converter, a digital-to-analog converter, an FPGA module, memory chips, and a controller. When the electronic device is powered on, the analog circuitry begins operation, completes initialization configuration, and the host computer identifies and controls the device via the PCIe interface.

[0027] In this embodiment, the host computer generates preset waveform data with a preset frequency and preset amplitude according to requirements, and writes the generated preset waveform data into the memory chip through the high-speed serial computer expansion bus standard PCIe interface. The host computer can be a computer or device responsible for managing and controlling the programmable array logic FPGA module. After writing the generated preset waveform data into the memory chip, a start signal is sent to the programmable array logic FPGA module.

[0028] S102, The waveform generation control module reads the preset waveform data from the memory chip and sends it to the digital-to-analog conversion module, so that the digital-to-analog conversion module outputs a preset analog signal based on the preset waveform data.

[0029] In this embodiment of the application, after the FPGA module receives the start signal, the waveform generation control module in the FPGA module reads the preset waveform data from the memory chip and sends the read preset waveform data to the digital-to-analog conversion module. The digital-to-analog conversion module converts the digital quantity into the corresponding analog quantity according to the weight of the acquired preset waveform data, and then processes the above-mentioned analog quantity to obtain a preset analog signal, and outputs the preset analog signal.

[0030] In this embodiment, the waveform generation control module acquires preset waveform data from the memory chip and controls the operation of the digital-to-analog converter module and the transmission of the preset waveform data. The digital-to-analog converter module can be a device that converts digital signals into analog signals, and is responsible for implementing the digital-to-analog conversion function.

[0031] S103, the analog-to-digital conversion module samples the output preset analog signal to obtain sampled data. The FPGA module receives and parses the sampled data through the analog-to-digital sampling unit and sends it to the analysis module. At the same time, the sampled data is sent to the memory chip for storage.

[0032] In this embodiment, the analog-to-digital conversion module receives the preset analog signal output by the digital-to-analog conversion module, performs sampling processing to obtain sampled data, and sends the processed sampled data to the analog-to-digital sampling unit. The analog-to-digital sampling unit parses the received sampled data. Further, after obtaining the sampled data, the analog-to-digital sampling unit also sends the sampled data to the analysis module for analysis and processing, and simultaneously sends the sampled data to the memory chip for storage.

[0033] In this embodiment, the analog-to-digital sampling unit controls the operation of the analog-to-digital conversion module and receives and processes the sampled data. The analog-to-digital conversion module can be a device that converts analog signals into digital signals, responsible for implementing the analog-to-digital conversion function.

[0034] S104. The analysis module extracts features from the sampled data to obtain feature information, and then transmits the feature information back to the host computer through the PCIe interface.

[0035] In this embodiment of the application, after the sampled data is sent to the analysis module, the analysis module performs feature extraction processing on the sampled data. The analysis module performs multi-dimensional analysis and processing on the sampled data, extracts key parameters or indicators that can characterize the characteristics of the sampled data, obtains feature information, and transmits the feature information back to the host computer for storage through the PCIe interface.

[0036] In this embodiment, the analysis module integrates multiple signal analysis algorithms, which can extract feature information from the loopback signal sampling data and transmit it back to the host computer for subsequent analysis and processing.

[0037] S105. The host computer compares the feature information with the target feature information corresponding to the preset waveform data to obtain the comparison result.

[0038] In this embodiment, after receiving the feature information, the host computer obtains a preset wave based on preset waveform data, and extracts features from the preset wave to obtain target feature information; the target feature information is then compared with the aforementioned feature information to obtain a comparison result. This comparison process includes the analysis of each feature information and the final comparison result is displayed.

[0039] S106. If the feature information is inconsistent with the target feature information, the internal algorithm of the FPGA module is reconfigured to complete the algorithm switch, and the steps of writing preset waveform data to the memory chip through the high-speed serial computer expansion bus standard PCIe interface and sending a start signal to the programmable array logic FPGA module are reset.

[0040] In this embodiment, when the feature information is inconsistent with the target feature information, the inconsistent feature information will be displayed and a prompt will be given. Simultaneously, the internal algorithm reconfiguration module of the FPGA module will be activated to reconfigure the internal algorithm of the FPGA module to complete the algorithm switch, and reset the steps of the host computer writing preset waveform data to the memory chip through the high-speed serial computer expansion bus standard PCIe interface and sending a start signal to the programmable array logic FPGA module. The internal algorithm reconfiguration module enables dynamic reconfiguration and rapid switching of the internal algorithm.

[0041] In an optional embodiment of this application, when the feature information is completely consistent with the target feature information, the loop closure test is displayed as successful and the process ends.

[0042] The technical solution provided in this application involves a host computer writing preset waveform data to a memory chip via a high-speed serial computer expansion bus standard PCIe interface and sending a start signal to a programmable array logic FPGA module. A waveform generation control module reads the preset waveform data from the memory chip and sends it to a digital-to-analog converter (DAC) module, causing the DAC module to output a preset analog signal based on the preset waveform data. The DAC module samples the output preset analog signal to obtain sampled data. The FPGA module receives and parses the sampled data through an analog-to-digital sampling unit and sends it to an analysis module. Simultaneously, the sampled data is sent to the memory chip. The sampled data is stored in memory chips. The analysis module extracts features from the sampled data to obtain feature information, and transmits the feature information back to the host computer via the PCIe interface. The host computer compares the feature information with the target feature information corresponding to the preset waveform data to obtain a comparison result. If the feature information is inconsistent with the target feature information, the internal algorithm of the FPGA module is reconfigured to complete the algorithm switch, and the steps of the host computer writing the preset waveform data to the memory chips via the high-speed serial computer expansion bus standard PCIe interface and sending a start signal to the programmable array logic FPGA module are reset. This achieves a one-click completion of the entire process of transmission, acquisition and analysis without external devices, achieving integrated transmission and reception with self-loopback, reducing operational difficulty, greatly reducing test time, and improving test efficiency. Utilizing FPGA dynamic reconfiguration and algorithm switching to support multiple test scenarios improves test controllability and integration, and reduces hardware costs.

[0043] Figure 2 A flowchart illustrating another embodiment of a method for implementing loopback testing based on algorithm switching, provided in this application. Figure 2 The process shown is in Figure 1 Based on the illustrated process, the following steps are included: S201. The host computer sends configuration information to the FPGA through the PCIe interface, so that the FPGA can use the configuration information to complete the initialization configuration.

[0044] This application is mainly used in loopback testing. In multiple fields such as network communication, hardware debugging, and software testing, loopback testing can quickly locate faults, verify system stability, and reduce dependence on the external environment.

[0045] In this embodiment, the system completes the loopback testing process based on algorithm switching through a host computer and an electronic device. The electronic device can be a benchtop oscilloscope, and the benchtop oscilloscope includes at least: an analog-to-digital converter, a digital-to-analog converter, an FPGA module, and memory chips. The FPGA module includes a waveform generation control module, an analog-to-digital sampling unit, a memory chip storage control module, an analysis module, and an internal algorithm reconfiguration module.

[0046] In this embodiment of the application, when the electronic device is powered on, the analog circuit starts to work, and the host computer sends configuration information to the FPGA through the PCIe interface so that the FPGA can use the configuration information to complete the initialization configuration.

[0047] In one example, a benchtop oscilloscope is used. This benchtop oscilloscope includes an ADC chip, a DAC chip, an FPGA chip, and DDR4 memory chips. The FPGA chip internally includes a waveform generation control module, an ADC acquisition control module, a DDR4 memory control module, an analysis module, and an internal algorithm reconfiguration module. When the oscilloscope is powered on, the analog circuitry starts working, the ADC chip begins its analog-to-digital conversion, the DAC chip begins its digital-to-analog conversion, the FPGA completes its power-on process, and the DDR4 completes its power-on initialization. The host computer identifies the benchtop oscilloscope through the PCIe interface and gains control of the FPGA. Simultaneously, it sends configuration information to the FPGA and controls it to complete the initialization parameter configuration.

[0048] S202. The host computer determines the preset waveform data according to the set frequency and the set amplitude, and calls the high-speed serial computer expansion bus standard PCIe interface to write the preset waveform data to the memory chip.

[0049] In this embodiment, the host computer generates preset waveform data with preset frequency and preset amplitude according to requirements, and writes the generated preset waveform data into the memory chip through the high-speed serial computer expansion bus standard PCIe interface. The host computer can be a computer or device responsible for managing and controlling the programmable array logic FPGA module.

[0050] Continuing from the previous example, the host computer generates square wave data with a frequency of 1MHz and an amplitude of 4V according to the requirements, and writes the square wave data to the DDR4 memory chip through the PCIe interface. The DDR4 memory chip stores the written square wave data.

[0051] S203. The host computer sends a start signal to the waveform generation control module of the programmable array logic FPGA module through the PCIe interface.

[0052] In this embodiment of the application, after the generated preset waveform data is written into the memory chip, the host computer sends a start signal to the programmable array logic FPGA module through the PCIe interface to trigger the FPGA module to start and ensure that it can correctly load the configuration data and enter the running state.

[0053] Continuing from the previous example, after the host computer writes the above waveform data into the DDR4 memory chip, it sends a start signal awg_start to the waveform generation control module of the FPGA chip to trigger the waveform generation control module of the FPGA chip to start and prepare for subsequent processing.

[0054] S204. When the waveform generation control module receives the start signal, it reads the preset waveform data from the memory chip.

[0055] In this embodiment of the application, after the waveform generation control module receives the start signal sent by the host computer, the waveform generation control module enters the working state and reads the preset waveform data stored in the memory chip.

[0056] Continuing from the previous example, the waveform generation control module enters the working state when it receives the start signal awg_start, and reads the square wave waveform data stored in the DDR4 memory chip.

[0057] S205. The waveform generation control module sends the read preset waveform data to the digital-to-analog conversion module.

[0058] S206 The digital-to-analog conversion module performs digital-to-analog conversion processing based on preset waveform data to obtain a preset analog signal.

[0059] The following is a unified discussion of S205-S206.

[0060] In this embodiment, after the waveform generation control module reads the preset waveform data from the memory chip, it sends the read preset waveform data to the digital-to-analog conversion module. The digital-to-analog conversion module performs digital-to-analog conversion processing based on the acquired preset waveform data. Specifically, it can convert the digital quantity into the corresponding analog quantity according to the weight, and then process the analog quantity to obtain the preset analog signal, and output the preset analog signal.

[0061] Continuing the previous example, after the waveform generation control module obtains the square wave data stored in the DDR4 memory chip, it sends the square wave data to the DAC chip. The DAC chip receives the square wave data and performs digital-to-analog conversion on it to obtain a square wave analog signal. Then, the waveform generation control module controls the DAC chip to output the square wave analog signal.

[0062] S207. The analog-to-digital conversion module receives the preset analog signal output by the digital-to-analog conversion module and performs sampling processing to obtain sampled data, wherein the sampling processing includes analog-to-digital conversion processing.

[0063] S208 uses the analog-to-digital sampling unit of the FPGA module to receive the sampled data output by the analog-to-digital conversion module.

[0064] S209, The analog-to-digital sampling unit receives and parses the sampled data.

[0065] The following is a unified discussion of S207-S209.

[0066] In this embodiment, after the digital-to-analog converter (DAC) outputs a preset analog signal, the preset analog signal is sent to the analog-to-digital converter (ADC). The ADC samples the preset analog signal to obtain sampled data. The sampling process includes analog-to-digital conversion (ADC): converting the obtained preset analog signal into a digital signal. The FPGA module's analog-to-digital sampling unit receives the sampled data output by the ADC. After receiving the sampled data, the analog-to-digital sampling unit parses and processes the sampled data.

[0067] Continuing the previous example, after the DAC chip outputs the aforementioned square wave analog signal, this signal is sent to the ADC chip. The ADC chip samples the received square wave analog signal and performs analog-to-digital conversion (ADC) to convert it into a digital signal (i.e., a loopback signal), thus obtaining the sampled data. The host computer uses the ADC acquisition control module of the FPGA chip to switch the analog input signal of ADC channel 1 to receive and analyze the sampled data output by the ADC chip.

[0068] S210. The sampled data is sent to the analysis module for processing through the analog-to-digital sampling unit.

[0069] S211. Send the sampled data to the memory chip for storage.

[0070] The following is a unified discussion of S207-S208.

[0071] In this embodiment, after obtaining the sampling data, the sampling data is sent to the analysis module for reception and parsing through the analog-to-digital sampling unit, while the FPGA module sends the sampling data to the memory chip for storage.

[0072] Continuing from the previous example, after obtaining the sampled data, the ADC acquisition and control module receives and parses the sampled data, sends the sampled data to the analysis module in the FPGA chip for algorithm analysis, and simultaneously sends the data to the DDR4 storage control module for data storage.

[0073] S212. The analysis module extracts features from the sampled data to obtain feature information.

[0074] S213. The feature information is transmitted back to the host computer and stored via the PCIe interface.

[0075] The following is a unified discussion of S212-S213.

[0076] In this embodiment, the system also sends the sampled data to the analysis module for feature extraction. The analysis module uses integrated signal analysis algorithms to perform multi-dimensional analysis and processing on the sampled data, extracting key parameters or indicators that characterize the features of the sampled data, obtaining feature information, and then transmitting this feature information back to the host computer for storage via the PCIe interface for subsequent analysis and processing. The feature information includes at least: amplitude, frequency, duty cycle, rise / fall time, and overshoot / undershoot.

[0077] Continuing the previous example, the analysis module receives the aforementioned square wave loop-loop signal with a frequency of 1MHz and an amplitude of 4V. Using pre-integrated signal analysis algorithms, it extracts feature information from this signal. This feature information can include amplitude, frequency, duty cycle, rise / fall time, and overshoot / undershoot. The extracted feature information results are obtained as data_amp_read, data_fre_read, data_dcr_read, data_rt_read, data_ft_read, data_os_read, and data_us_read. These results are then transmitted back to the host computer via the PCIe interface for storage.

[0078] S214. The host computer receives the feature information.

[0079] S215. Determine the preset wave based on the preset waveform data, and extract the target feature information from the preset wave.

[0080] S216. Compare the feature information with the target feature information to obtain the comparison result.

[0081] The following is a unified discussion of S214-S216.

[0082] In this embodiment, the host computer receives and stores the feature information sent by the analysis module. A preset wave is obtained based on the received preset waveform data, and target feature information is obtained by acquiring each of the aforementioned feature information of the preset wave. The target feature information is then compared with the aforementioned feature information to obtain a comparison result. This comparison process includes the analysis of each feature information, and the final comparison result is displayed.

[0083] In an optional embodiment of this application, after the host computer receives and stores the feature information sent by the analysis module, it can obtain the target feature extraction information of the preset wave that has been stored in the host computer storage module, and then proceed to the next step of processing.

[0084] Continuing the previous example, the host computer receives and stores the feature information extraction results of the aforementioned square wave loop signal. Simultaneously, it determines the square wave based on the waveform data and acquires its feature information (amplitude, frequency, duty cycle, rise / fall time, overshoot / undershoot) to obtain the target feature information. The obtained target feature information is then compared one by one with the aforementioned feature information to obtain the comparison results, which are then displayed.

[0085] S217. If the feature information is inconsistent with the target feature information, indicate the difference in feature information; start the internal algorithm reconfiguration module to reconfigure the internal algorithm of the FPGA module to complete the algorithm switch.

[0086] In this embodiment, the target feature information is compared with the feature information. After obtaining the comparison result, if the feature information is inconsistent with the target feature information, the inconsistent feature information will be displayed and a prompt will be given. At the same time, the internal algorithm reconfiguration module of the FPGA module is activated to reconfigure the internal algorithm of the FPGA module to complete the algorithm switching. The internal algorithm reconfiguration module shortens the algorithm switching time and improves the testing speed. Further, the system resets the execution steps of the host computer writing preset waveform data to the memory chip through the high-speed serial computer expansion bus standard PCIe interface and sending a start signal to the programmable array logic FPGA module. Among them, the internal algorithm reconfiguration module realizes the dynamic reconfiguration and fast switching of the internal algorithm.

[0087] S218. If the feature information is completely consistent with the target feature information, set the flag of the comparison result to the preset value and display that the loop closure test is successful.

[0088] In this embodiment of the application, when the comparison result is obtained and the result shows that the feature information is completely consistent with the target feature information, the flag of the comparison result is set to a preset value, the loop closure test is displayed as successful, and the process ends.

[0089] Continuing from the previous example, when the comparison result shows that the feature information data_read is completely consistent with the target feature information data_original, the comparison result flag_compare is set to 1 to indicate that the loop closure test was successful and the process ends.

[0090] Figure 2 The illustrated process provides a method for loopback testing based on algorithm switching. This method enables one-click completion of the entire transmission, acquisition, and analysis process without the need for external devices, achieving integrated transmission and reception with self-loopback. This reduces operational complexity, significantly shortens testing time, and improves testing efficiency. Furthermore, by utilizing FPGA dynamic reconfiguration and algorithm switching to support multiple testing scenarios, it enhances test controllability and integration while reducing hardware costs.

[0091] Figure 3 This is a block diagram illustrating an embodiment of a loop closure test system provided in this application. Figure 3 As shown, the system includes: The host computer 301 is used to write preset waveform data to the memory chip through the high-speed serial computer expansion bus standard PCIe interface, and to send a start signal to the programmable array logic FPGA module. The waveform generation control module 302 is used to read the preset waveform data from the memory chip and send it to the digital-to-analog conversion module, so that the digital-to-analog conversion module outputs a preset analog signal based on the preset waveform data. The FPGA module 303 is used to receive and parse the sampled data through the analog-to-digital sampling unit and send it to the analysis module, and at the same time send the sampled data to the memory chip for storage; Analysis module 304 is used to extract features from the sampled data, obtain feature information, and transmit the feature information back to the host computer through the PCIe interface; The host computer 301 is also used to compare the feature information with the target feature information corresponding to the preset waveform data to obtain a comparison result; The internal algorithm reconfiguration module 305 is used to reconfigure the internal algorithm of the FPGA module to complete the algorithm switching when the feature information is inconsistent with the target feature information, and to reset the execution steps of the host computer writing preset waveform data to the memory chip through the high-speed serial computer expansion bus standard PCIe interface and sending a start signal to the programmable array logic FPGA module.

[0092] In one possible implementation, the host computer 301 is specifically used to send configuration information to the FPGA through the PCIe interface, so that the FPGA can use the configuration information to complete the initialization configuration.

[0093] In one possible implementation, the host computer 301 is specifically used to determine preset waveform data according to a set frequency and a set amplitude, and call the high-speed serial computer expansion bus standard PCIe interface to write the preset waveform data to the memory chip; and the host computer sends a start signal to the waveform generation control module of the programmable array logic FPGA module through the PCIe interface.

[0094] In one possible implementation, the waveform generation control module 302 is specifically used to read the preset waveform data from the memory chip when the waveform generation control module receives a start signal; the waveform generation control module then sends the read preset waveform data to the digital-to-analog converter module.

[0095] In one possible implementation, the digital-to-analog conversion module 306 is specifically used to perform digital-to-analog conversion processing based on the preset waveform data to obtain a preset analog signal.

[0096] In one possible implementation, the analog-to-digital conversion module 307 is specifically used to receive the preset analog signal output by the digital-to-analog conversion module and perform sampling processing to obtain sampled data, wherein the sampling processing includes analog-to-digital conversion processing.

[0097] In one possible implementation, the analog-to-digital sampling unit 308 is specifically used to receive the sampling data output by the analog-to-digital conversion module; the analog-to-digital sampling unit receives and parses the sampling data; the analog-to-digital sampling unit sends the sampling data to the analysis module for processing; and the analog-to-digital sampling unit sends the sampling data to the memory chip for storage.

[0098] In one possible implementation, the analysis module 304 is specifically used to extract features from the sampled data to obtain feature information, wherein the feature information includes at least: amplitude, frequency, duty cycle, rise / fall time, overshoot / undershoot; and to transmit the feature information back to the host computer and store it through the PCIe interface.

[0099] In one possible implementation, the host computer 301 is specifically used to receive the feature information; determine a preset wave based on preset waveform data; extract target feature information from the preset wave; and compare the feature information with the target feature information to obtain a comparison result.

[0100] In one possible implementation, the host computer 301 is specifically used to prompt the feature information that is inconsistent with the target feature information when the feature information is inconsistent with the target feature information; and to start the internal algorithm reconfiguration module to reconfigure the internal algorithm of the FPGA module to complete the algorithm switching.

[0101] In one possible implementation, the host computer 301 is specifically used to set the flag of the comparison result to a preset value and display that the loop closure test is successful when the feature information is completely consistent with the target feature information.

[0102] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0103] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented using software plus a general-purpose hardware platform, or of course, using hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0104] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also include the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.

[0105] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for implementing loopback testing based on algorithm switching, characterized in that, The method includes: The host computer writes preset waveform data to the memory chip through the high-speed serial computer expansion bus standard PCIe interface, and sends a start signal to the programmable array logic FPGA module. The waveform generation control module reads the preset waveform data from the memory chip and sends it to the digital-to-analog conversion module, so that the digital-to-analog conversion module outputs a preset analog signal based on the preset waveform data; The analog-to-digital conversion module samples the output preset analog signal to obtain sampled data. The FPGA module receives and parses the sampled data through the analog-to-digital sampling unit and sends it to the analysis module. At the same time, the sampled data is sent to the memory chip for storage. The analysis module extracts features from the sampled data to obtain feature information, and then transmits the feature information back to the host computer through the PCIe interface. The host computer compares the feature information with the target feature information corresponding to the preset waveform data to obtain the comparison result. If the feature information is inconsistent with the target feature information, the internal algorithm of the FPGA module is reconfigured to complete the algorithm switch, and the steps of writing preset waveform data to the memory chip through the high-speed serial computer expansion bus standard PCIe interface and sending a start signal to the programmable array logic FPGA module are reset.

2. The method according to claim 1, characterized in that, Before the host computer writes preset waveform data to the memory chip via the high-speed serial computer expansion bus standard PCIe interface, the following is also included: The host computer sends configuration information to the FPGA through the PCIe interface, so that the FPGA can use the configuration information to complete the initialization configuration.

3. The method according to claim 1, characterized in that, The host computer writes preset waveform data to the memory chip via the high-speed serial computer expansion bus standard PCIe interface, and sends a start signal to the programmable array logic FPGA module, including: The host computer determines the preset waveform data according to the set frequency and the set amplitude, and calls the high-speed serial computer expansion bus standard PCIe interface to write the preset waveform data to the memory chip. Additionally, the host computer sends a start signal to the waveform generation control module of the programmable array logic FPGA module through the PCIe interface.

4. The method according to claim 3, characterized in that, The waveform generation control module reads the preset waveform data from the memory chip and sends it to the digital-to-analog conversion module, so that the digital-to-analog conversion module outputs a preset analog signal based on the preset waveform data, including: When the waveform generation control module receives the start signal, it reads the preset waveform data from the memory chip; The waveform generation control module sends the read preset waveform data to the digital-to-analog conversion module; The digital-to-analog conversion module performs digital-to-analog conversion processing based on the preset waveform data to obtain a preset analog signal.

5. The method according to claim 4, characterized in that, The analog-to-digital conversion module samples the output preset analog signal to obtain sampled data. The FPGA module receives and parses the sampled data through the analog-to-digital sampling unit and sends it to the analysis module. Simultaneously, the sampled data is sent to the memory chip for storage, including: The analog-to-digital conversion module receives the preset analog signal output by the digital-to-analog conversion module and performs sampling processing to obtain sampled data, wherein the sampling processing includes analog-to-digital conversion processing; The FPGA module's analog-to-digital sampling unit receives the sampled data output by the analog-to-digital conversion module; The analog-to-digital sampling unit receives and parses the sampled data. The sampled data is sent to the analysis module for processing via the analog-to-digital sampling unit. In addition, the sampled data is sent to the memory chip for storage.

6. The method according to claim 5, characterized in that, The analysis module extracts features from the sampled data to obtain feature information, and then transmits the feature information back to the host computer via the PCIe interface, including: The analysis module extracts features from the sampled data to obtain feature information, wherein the feature information includes at least: amplitude, frequency, duty cycle, and rise / fall time; The feature information is transmitted back to the host computer and stored via the PCIe interface.

7. The method according to claim 1, characterized in that, The host computer compares the feature information with the target feature information corresponding to the preset waveform data to obtain a comparison result, including: The host computer receives the feature information; A preset wave is determined based on preset waveform data, and target feature information is extracted from the preset wave; The feature information is compared with the target feature information to obtain the comparison result.

8. The method according to claim 1, characterized in that, In the case where the feature information and the target feature information are inconsistent, the internal algorithm of the FPGA module is reconfigured to complete the algorithm switch, including: If the feature information is inconsistent with the target feature information, the feature information that is inconsistent will be indicated; The internal algorithm reconfiguration module is activated to reconfigure the internal algorithms of the FPGA module in order to complete the algorithm switching.

9. The method according to claim 8, characterized in that, The method further includes: If the feature information is completely consistent with the target feature information, the flag of the comparison result is set to a preset value, and the loop closure test is displayed as successful.

10. A loopback testing system, characterized in that, The system includes: The host computer is used to write preset waveform data to the memory chip through the high-speed serial computer expansion bus standard PCIe interface, and to send a start signal to the programmable array logic FPGA module. A waveform generation control module is used to read the preset waveform data from the memory chip and send it to the digital-to-analog conversion module, so that the digital-to-analog conversion module outputs a preset analog signal based on the preset waveform data. The FPGA module is used to receive and parse the sampled data through the analog-to-digital sampling unit and send it to the analysis module, and at the same time send the sampled data to the memory chip for storage; The analysis module is used to extract features from the sampled data, obtain feature information, and transmit the feature information back to the host computer through the PCIe interface; The host computer is also used to compare the feature information with the target feature information corresponding to the preset waveform data to obtain a comparison result; The internal algorithm reconfiguration module is used to reconfigure the internal algorithm of the FPGA module to complete the algorithm switching when the feature information is inconsistent with the target feature information, and to reset the execution steps of the host computer writing preset waveform data to the memory chip through the high-speed serial computer expansion bus standard PCIe interface and sending a start signal to the programmable array logic FPGA module.

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