A fault detection circuit and fault identification system for a motor driver

Abstract

The present application relates to the technical field of motor drive, in particular to a kind of fault detection circuit and fault identification system of motor driver, receive the analog signal of front-stage circuit transmission, this fault detection circuit includes: logic unit, latching unit, action and detection unit, driving chip;Also disclose a kind of fault detection of motor driver's fault identification system, including MCU and multiple load as before the fault detection circuit of motor driver, each fault detection circuit is connected to MCU after receiving the analog of front-stage circuit, and the fault type is identified according to the feedback signal kind of each fault detection circuit output, in fault detection circuit, when fault occurs, the first level signal of logic unit is converted into second level signal, to control the output of latching unit is latched to the logic unit, to avoid the damage of each element in circuit by fault.

Description

Technical Field

[0001] This invention relates to the field of motor drive technology, and in particular to a fault detection circuit and fault identification system for a motor driver. Background Technology

[0002] Motor drivers typically consist of a control unit, a drive unit, and a signal feedback system, mainly including a microprocessor, power MOSFETs, and position sensors. However, current motor drivers often lack fault detection circuits to handle damage to hardware caused by circuit faults, such as abnormal voltage or current, which can even lead to permanent damage to some components. Furthermore, accurate fault identification is difficult, negatively impacting motor driver repair. Summary of the Invention

[0003] The purpose of this invention is to provide a fault detection circuit for a motor driver to solve the problem of circuit faults causing damage to hardware in the circuit in the prior art, and to provide a fault identification system for a motor driver to accurately identify the type of fault.

[0004] To achieve the above objectives, the present invention provides a fault detection circuit for a motor driver, coupled between a pre-amplifier circuit and an MCU, receiving analog signals transmitted from the pre-amplifier circuit. The fault detection circuit comprises: The logic unit is configured to output a first-level signal when operating normally, and to output a second-level signal when the analog signal exceeds a single-limit threshold. A latching unit is connected to the logic unit and receives the output of the logic unit. When a first level signal is received, the output remains unchanged. When a second level signal is received, the output of the logic unit is latched as the second level signal. The action and detection unit is connected to the driver chip, the logic unit, the latch unit, and the MCU respectively. When the action and detection unit receives a second level signal from the logic unit or the MCU, the driver chip stops enabling. The driver chip is connected to the action and detection unit and receives the output of the action and detection unit.

[0005] The fault detection circuit for the motor driver proposed in this invention operates as follows: during normal operation, the logic unit outputs a first-level signal, the latch unit remains inactive, and the enable signal of the driver chip is controlled by the MCU. When a fault occurs, the latch unit activates, pulling the enable signal of the driver chip low, thus disengaging the driver chip from MCU control and awaiting fault diagnosis and reset. Throughout the entire operation, the MCU detects the returned enable signal, implementing a detection and protection function for the motor driver. The first-level signal ranges from 2V to VCC, and the second-level signal ranges from 0V to 0.8V, where VCC is the power supply voltage.

[0006] The logic unit includes a first comparator U1, a first AND gate U3, a first resistor R2, a second resistor R5, and a pull-up resistor R3. The non-inverting input of the first comparator U1 is connected to one end of the first resistor R2 and one end of the second resistor R5. The other end of the first resistor R2 is connected to the power supply, and the other end of the second resistor R5 is grounded. The inverting input of the first comparator U1 is used to receive analog signals from the preceding circuit. The output of the first comparator U1 is connected to the first input of the first AND gate U3. One end of the pull-up resistor R3 is connected to the power supply, and the other end is connected to the second input of the first AND gate U3. The first AND gate U3 is configured to output a second-level signal when any input is a second-level signal, and to output a first-level signal when all inputs are first-level signals.

[0007] In this embodiment, only a first comparator U1 is provided. The output of the first comparator U1 is a second-level signal, and the output of the first AND gate U3 is the output of the logic unit, which is the second-level signal. During normal operation, the logic unit outputs a first-level signal, and the pull-up resistor R3 is used for current limiting.

[0008] The logic unit includes a first comparator U1, a second comparator U2, a first AND gate U3, a first resistor R2, a second resistor R5, and a resistor R9. The non-inverting input of the first comparator U1 is connected to one end of the first resistor R2 and one end of the second resistor R5, and the other end of the first resistor R2 is connected to a power supply. The inverting input of the second comparator U2 is connected to one end of the resistor R9 and the other end of the second resistor R5, and the other end of the resistor R9 is grounded. Both the inverting input of the first comparator U1 and the non-inverting input of the second comparator U2 are used to receive analog signals from the preceding circuit. The first AND gate U3 is configured to output a second-level signal when any input is a second-level signal, and to output a first-level signal when all inputs are first-level signals.

[0009] In this embodiment, the first AND gate U3 is a dual-channel AND gate, which can be replaced with a single-channel or multi-channel AND gate as needed. When the motor driver fails, if either the first comparator U1 or the second comparator U2 outputs a second-level signal, the logic unit outputs a second-level signal; during normal operation, the logic unit outputs a first-level signal. The analog quantity can be a voltage, current, temperature, or other signal. In the event of a fault, the logic unit outputs an enable signal that is pulled low to stop the actuator, thus providing a rapid response to the hardware fault. The resistor R9 is used for voltage division.

[0010] The latch unit includes a third resistor R1, a first PNP transistor Q1, a second NPN transistor Q2, and a fourth resistor R4. The output terminal of the logic unit is connected to the base of the first PNP transistor Q1 through the third resistor R1. The emitter of the first PNP transistor Q1 is connected to the operating voltage, and its collector is connected to the base of the second NPN transistor Q2 through the fourth resistor R4. The emitter of the second NPN transistor Q2 is grounded, and its collector serves as the output terminal of the enable signal.

[0011] In this invention, when the logic unit outputs a first-level signal, the first PNP transistor Q1 and the second NPN transistor Q2 are not activated, and the logic unit output remains at the first-level signal. When the logic unit outputs a second-level signal, the first PNP transistor Q1 and the second NPN transistor Q2 are activated, and the actuator stops. After the second NPN transistor Q2 is activated, its base level is pulled low. At this time, regardless of whether the logic unit outputs a first-level signal or a second-level signal, the enable signal will be latched as the second-level signal, achieving a one-time latching function. The third resistor R1 and the fourth resistor R4 have a current-limiting function to prevent circuit losses after the circuit latching operation.

[0012] The action and monitoring unit includes a second AND gate U5, a third PNP transistor Q3, a NOT gate U4, and a fifth resistor R10. The first input of the second AND gate U5 is connected to the output of the logic unit, and the second input of the second AND gate U5 is connected to the collector of the third PNP transistor Q3. The base of the third PNP transistor Q3 is connected to the MCU through the fifth resistor R10, and the emitter of the third PNP transistor Q3 is grounded. The output of the second AND gate U5 outputs an enable signal EN, which is connected to the input of the NOT gate U4. The output of the NOT gate U4 is connected to the MCU and is used to output a feedback signal FB.

[0013] The inputs of the second AND gate U5 are the output of the logic unit and the collector of the third PNP transistor Q3, respectively. When the actuator is enabled, stopped, or software protection occurs, the MCU controls the base of the third PNP transistor Q3 to turn on and off. When the base level is a first level signal, the third PNP transistor Q3 is off, and the pin input of the second AND gate U5 is a second level signal; when the base level is a second level signal, the third PNP transistor Q3 is on, and the pin input of the second AND gate U5 is a first level signal. If all inputs to the second AND gate U5 are first level signals, the enable signal is a first level signal; if any input is a second level signal, the output of the second AND gate U5 is a second level signal, and the driver chip stops enabling. The enable signal is toggled through the NOT gate U4, and the MCU detects the feedback signal to realize fault action and detection functions.

[0014] The driving chip is a MOS transistor driver. When the input enable signal is a first level signal, the MOS transistor is controlled to turn on and off. When the input enable signal is a second level signal, it controls the MOS transistor to be in the off state.

[0015] The driving chip is a MOS transistor driver enabled by a first-level signal. When the input signal is a first-level signal, the driving signal is valid, and the MOS transistor is controlled to turn on and off. When the driving signal is a second-level signal, the MOS transistor is controlled to be in the off state.

[0016] The present invention also provides a fault identification system for a motor driver, including an MCU and multiple fault detection circuits carrying the motor driver as described above. Each fault detection circuit receives analog signals from the preceding circuit and is connected to the MCU. The MCU identifies the fault type based on the type of feedback signal output by each fault detection circuit.

[0017] The analog quantity is one of voltage, current, or temperature.

[0018] The feedback signals include FB_Vol corresponding to the voltage value, FB_Cur corresponding to the current value, and FB_Temp corresponding to the temperature.

[0019] Multiple fault detection circuits are connected to the MCU. Each fault detection circuit is configured to receive different analog quantities and to configure different feedback signals for different analog quantities. The voltage value corresponds to FB_Vol, the current value corresponds to FB_Cur, and the temperature corresponds to FB_Temp. When any fault occurs, the fault type can be quickly identified through the feedback signal received by the MCU.

[0020] This invention provides a fault detection circuit and a fault identification system for a motor driver. Addressing the issues in existing technologies where circuit faults easily damage the circuit, and where fault detection circuits cannot handle hardware damage or identify fault types, this invention first proposes a fault detection circuit. When a fault occurs, the logic unit outputs a first-level signal that changes to a second-level signal, controlling a latching unit to latch the logic unit's output, thus preventing damage to components in the circuit. Secondly, the invention proposes a fault identification system that integrates multiple fault detection circuits and sets corresponding feedback signals for the analog quantities input to each fault detection circuit. When a fault occurs, the type of fault can be determined through the feedback signals. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This invention relates to a fault detection circuit for a motor driver.

[0023] Figure 2 This is a schematic diagram of the working timing of a fault detection circuit for a motor driver according to the present invention.

[0024] Figure 3 This is a schematic diagram of the application circuit of the fault detection circuit of the motor driver of the present invention for three-phase current faults.

[0025] Figure 4 This is a schematic diagram of the application circuit for bus voltage fault detection in a motor driver according to the present invention.

[0026] Figure 5 This is a schematic diagram of the application circuit for over-temperature fault detection in a motor driver according to the present invention.

[0027] Figure 6 This is a schematic diagram of a circuit for detecting a drive level undervoltage fault in another embodiment of a motor driver according to the present invention.

[0028] Figure 7 This is a schematic diagram of a fault identification system for a motor driver according to the present invention. Detailed Implementation

[0029] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0030] Please see Figures 1 to 6 This invention provides a fault detection circuit for a motor driver, coupled between a pre-amplifier circuit and an MCU, receiving analog signals transmitted from the pre-amplifier circuit. The fault detection circuit comprises: The logic unit is configured to output a first-level signal when operating normally, and to output a second-level signal when the analog signal exceeds a single-limit threshold. A latching unit is connected to the logic unit and receives the output of the logic unit. When a first level signal is received, the output remains unchanged. When a second level signal is received, the output of the logic unit is latched as the second level signal. The action and detection unit is connected to the driver chip, the logic unit, the latch unit, and the MCU respectively. When the action and detection unit receives a second level signal from the logic unit or the MCU, the driver chip stops enabling. The driver chip is connected to the action and detection unit and receives the output of the action and detection unit. Please see Figure 2 When a fault occurs in this application, the logic unit outputs a second-level signal. At this time, the latch unit activates to maintain the logic unit's output at the second-level signal, thus the enable signal EN becomes a second-level signal, and the actuator stops. After stopping, regardless of whether the MCU's instruction is a first-level signal or a second-level signal, the enable signal EN will remain at the second-level signal. Simultaneously, the MCU detects the signal FB to perform a detection function.

[0031] The logic unit includes a first comparator U1, a first AND gate U3, a first resistor R2, a second resistor R5, and a pull-up resistor R3. The non-inverting input of the first comparator U1 is connected to one end of the first resistor R2 and one end of the second resistor R5. The other end of the first resistor R2 is connected to the power supply, and the other end of the second resistor R5 is grounded. The inverting input of the first comparator U1 is used to receive analog signals from the preceding circuit. The output of the first comparator U1 is connected to the first input of the first AND gate U3. One end of the pull-up resistor R3 is connected to the power supply, and the other end is connected to the second input of the first AND gate U3. The first AND gate U3 is configured to output a second-level signal when any input is a second-level signal, and to output a first-level signal when all inputs are first-level signals.

[0032] Please see Figure 5 and Figure 6 In one embodiment of the present invention, the fault detection circuit determines the fault based on the upper or lower limit of the analog quantity. When determining the single limit threshold, the input of the first AND gate U3 in the logic unit is pulled high, thus using a pull-up resistor R3.

[0033] The logic unit includes a first comparator U1, a second comparator U2, a first AND gate U3, a first resistor R2, a second resistor R5, and a resistor R9. The non-inverting input of the first comparator U1 is connected to one end of the first resistor R2 and one end of the second resistor R5, and the other end of the first resistor R2 is connected to a power supply. The inverting input of the second comparator U2 is connected to one end of the resistor R9 and the other end of the second resistor R5, and the other end of the resistor R9 is grounded. Both the inverting input of the first comparator U1 and the non-inverting input of the second comparator U2 are used to receive analog signals from the preceding circuit. The first AND gate U3 is configured to output a second-level signal when any input is a second-level signal, and to output a first-level signal when all inputs are first-level signals.

[0034] Please see Figure 1 , Figure 3 and Figure 4 In another embodiment of the present invention, the fault detection circuit performs fault action for analog quantities, including voltage, current, temperature, etc. The fault detection circuit can simultaneously protect against faults at the upper and lower limits of the analog quantities. During the simultaneous protection against faults at the upper and lower limits of the analog quantities, before the actuator operates, the MCU controls the base level of the third PNP transistor Q3 to a first level signal. At this time, the third PNP transistor Q3 is turned off, and the pin input of the second AND gate U5 is a second level signal. At this time, the analog quantity has not exceeded the protection threshold, the logic unit output is a first level signal, and therefore the enable signal EN is a second level signal; the actuator stops and waits for the run command. When the actuator runs, the MCU controls the base level of the third transistor Q3 to a second level signal. At this time, the PNP transistor Q is turned on, the input level of the driver chip is a first level signal, the enable signal EN is a first level signal, and the motor driver operates normally. When a fault occurs, the logic unit outputs a second level signal. At this time, the latch unit operates to keep the output of the logic unit at a second level signal, therefore the enable signal EN is a second level signal, and the actuator stops. After shutdown, regardless of whether the MCU instruction is a first-level signal or a second-level signal, the enable signal EN will remain at the second-level signal.

[0035] The latch unit includes a third resistor R1, a first PNP transistor Q1, a second NPN transistor Q2, and a fourth resistor R4. The output terminal of the logic unit is connected to the base of the first PNP transistor Q1 through the third resistor R1. The emitter of the first PNP transistor Q1 is connected to the operating voltage, and its collector is connected to the base of the second NPN transistor Q2 through the fourth resistor R4. The emitter of the second NPN transistor Q2 is grounded, and its collector serves as the output terminal of the enable signal.

[0036] In this embodiment, when the logic unit outputs a first-level signal, the first PNP transistor Q1 and the second NPN transistor Q2 are not activated, and the logic unit output remains at the first-level signal. When the logic unit outputs a second-level signal, the first PNP transistor Q1 and the second NPN transistor Q2 are activated, and the actuator stops. After the second NPN transistor Q2 is activated, its base level is pulled low. At this time, regardless of whether the logic unit outputs a first-level signal or a second-level signal, the enable signal will be latched as the second-level signal, achieving a one-time latching function. The third resistor R1 and the fourth resistor R4 serve a current-limiting function to prevent circuit losses after the circuit latching operation.

[0037] The action and monitoring unit includes a second AND gate U5, a third PNP transistor Q3, a NOT gate U4, and a fifth resistor R10. The first input of the second AND gate U5 is connected to the output of the logic unit, and the second input of the second AND gate U5 is connected to the collector of the third PNP transistor Q3. The base of the third PNP transistor Q3 is connected to the MCU through the fifth resistor R10, and the emitter of the third PNP transistor Q3 is grounded. The output of the second AND gate U5 outputs an enable signal EN, which is connected to the input of the NOT gate U4. The output of the NOT gate U4 is connected to the MCU and is used to output a feedback signal FB.

[0038] The driving chip is a MOS transistor driver. When the input enable signal is a first level signal, the MOS transistor is controlled to turn on and off. When the input enable signal is a second level signal, it controls the MOS transistor to be in the off state.

[0039] The MCU detects the feedback signal, thereby realizing fault action and detection functions. The driving chip is a MOS transistor driver enabled by a first level signal. When the input signal is a first level signal, the driving signal is valid, and the MOS transistor is controlled to turn on and off. When the driving signal is a second level signal, the MOS transistor is controlled to be in the off state.

[0040] The present invention also provides a fault identification system for a motor driver, including an MCU and multiple fault detection circuits carrying the motor driver as described above. Each fault detection circuit receives analog signals from the preceding circuit and is connected to the MCU. The MCU identifies the fault type based on the type of feedback signal output by each fault detection circuit.

[0041] In the constructed fault identification system, corresponding detection analog quantities are established with different feedback signals, and then the MCU detects the types of feedback signals to realize the identification of fault types.

[0042] The analog quantity is one of voltage, current, or temperature.

[0043] The feedback signals include FB_Vol corresponding to the voltage value, FB_Cur corresponding to the current value, and FB_Temp corresponding to the temperature.

[0044] Please see Figure 7 In the diagram, H represents the first level signal and L represents the second level signal. Before operation, the MCU controls the base level of the third PNP transistor Q3 to be the first level signal. At this time, the third PNP transistor Q3 is turned off, and the input of pin 2 of the second AND gate U5 is the second level signal. At this time, the analog quantity does not exceed the protection threshold, and the logic unit output is the first level signal. Therefore, the enable signal EN is the second level signal. The actuator stops and waits for the operation command.

[0045] When the actuator is running, the MCU controls the base level of the third PNP transistor Q3 to the second level signal. At this time, the third PNP transistor Q3 is turned on, the input level of the driver chip is the first level signal, the enable signal EN is the first level signal, and the motor driver runs normally.

[0046] When a fault occurs, the logic unit outputs a second-level signal. At this time, the latch unit activates, maintaining the logic unit's output at the second-level signal. Therefore, the enable signal EN is also at the second-level signal, and the actuator stops. After stopping, regardless of whether the MCU's instruction is a second-level or first-level signal, the enable signal EN will remain at the second-level signal. Simultaneously, the MCU detects the feedback signal FB, performing a detection function. The fault detection circuit, as a single circuit unit, handles the fault. The fault identification system determines the specific fault type in the motor driver based on the feedback signal FB, thus achieving the fault detection function.

[0047] The specific implementation method is as follows: Figure 7This is a fault identification system composed of three fault detection circuits, with analog values ​​representing the upper limit of current, lower limit of current, lower limit of voltage, and upper limit of temperature. The outputs of the three detection and action circuit units are all connected to the MCU, namely FB_Cur, FB_Vol, and FB_Temp. When the motor is running, the MCU simultaneously monitors the levels of FB_Cur, FB_Vol, and FB_Temp. When no fault occurs, all three levels are at the second-level signal. If the feedback signal FB_Cur is detected to be at the first-level signal, it indicates an overcurrent fault; if the feedback signal FB_Vol is detected to be at the first-level signal, it indicates an overvoltage fault. This allows for precise identification of the fault type.

[0048] The above description discloses only one preferred embodiment of the present invention, and should not be construed as limiting the scope of the present invention. Those skilled in the art will understand that all or part of the processes of the above embodiments can be implemented, and equivalent changes made in accordance with the claims of the present invention are still within the scope of the invention.

Claims

1. A fault detection circuit for a motor driver, coupled between a pre-amplifier circuit and an MCU, receiving analog signals transmitted from the pre-amplifier circuit, characterized in that, The fault detection circuit includes: The logic unit is configured to output a first-level signal when operating normally, and to output a second-level signal when the analog signal exceeds a single-limit threshold. A latching unit is connected to the logic unit and receives the output of the logic unit. When a first level signal is received, the output remains unchanged. When a second level signal is received, the output of the logic unit is latched as the second level signal. The action and detection unit is connected to the driver chip, the logic unit, the latch unit, and the MCU respectively. When the action and detection unit receives a second level signal from the logic unit or the MCU, the driver chip stops enabling. The driver chip is connected to the action and detection unit and receives the output of the action and detection unit.

2. The fault detection circuit for the motor driver as described in claim 1, characterized in that, The logic unit includes a first comparator U1, a first AND gate U3, a first resistor R2, a second resistor R5, and a pull-up resistor R3. The non-inverting input of the first comparator U1 is connected to one end of the first resistor R2 and one end of the second resistor R5. The other end of the first resistor R2 is connected to the power supply, and the other end of the second resistor R5 is grounded. The inverting input of the first comparator U1 is used to receive analog signals from the preceding circuit. The output of the first comparator U1 is connected to the first input of the first AND gate U3. One end of the pull-up resistor R3 is connected to the power supply, and the other end is connected to the second input of the first AND gate U3. The first AND gate U3 is configured to output a second-level signal when any input is a second-level signal, and to output a first-level signal when all inputs are first-level signals.

3. The fault detection circuit for the motor driver as described in claim 1, characterized in that, The logic unit includes a first comparator U1, a second comparator U2, a first AND gate U3, a first resistor R2, a second resistor R5, and a resistor R9. The non-inverting input of the first comparator U1 is connected to one end of the first resistor R2 and one end of the second resistor R5, and the other end of the first resistor R2 is connected to a power supply. The inverting input of the second comparator U2 is connected to one end of the resistor R9 and the other end of the second resistor R5, and the other end of the resistor R9 is grounded. Both the inverting input of the first comparator U1 and the non-inverting input of the second comparator U2 are used to receive analog signals from the preceding circuit. The first AND gate U3 is configured to output a second-level signal when any input is a second-level signal, and to output a first-level signal when all inputs are first-level signals.

4. The fault detection circuit for the motor driver as described in any one of claims 1 to 3, characterized in that, The latch unit includes a third resistor R1, a first PNP transistor Q1, a second NPN transistor Q2, and a fourth resistor R4. The output terminal of the logic unit is connected to the base of the first PNP transistor Q1 through the third resistor R1. The emitter of the first PNP transistor Q1 is connected to the operating voltage, and its collector is connected to the base of the second NPN transistor Q2 through the fourth resistor R4. The emitter of the second NPN transistor Q2 is grounded, and its collector serves as the output terminal of the enable signal.

5. The fault detection circuit for the motor driver as described in any one of claims 1 to 3, characterized in that, The action and monitoring unit includes a second AND gate U5, a third PNP transistor Q3, a NOT gate U4, and a fifth resistor R10. The first input of the second AND gate U5 is connected to the output of the logic unit, and the second input of the second AND gate U5 is connected to the collector of the third PNP transistor Q3. The base of the third PNP transistor Q3 is connected to the MCU through the fifth resistor R10, and the emitter of the third PNP transistor Q3 is grounded. The output of the second AND gate U5 outputs an enable signal EN, which is connected to the input of the NOT gate U4. The output of the NOT gate U4 is connected to the MCU and is used to output a feedback signal FB.

6. The fault detection circuit for the motor driver as described in claim 5, characterized in that, The driving chip is a MOS transistor driver. When the input enable signal is a first level signal, the MOS transistor is controlled to turn on and off. When the input enable signal is a second level signal, it controls the MOS transistor to be in the off state.

7. A fault identification system for fault detection of a motor driver, characterized in that, The system includes an MCU and multiple fault detection circuits carrying motor drivers as described in any one of claims 1 to 6. Each fault detection circuit receives analog signals from the preceding circuit and is connected to the MCU. The MCU identifies the fault type based on the type of feedback signal output by each fault detection circuit.

8. The fault identification system for fault detection of a motor driver as described in claim 7, characterized in that, The analog quantity is one of voltage, current, or temperature.

9. The fault identification system for fault detection of a motor driver as described in claim 8, characterized in that, The feedback signals include FB_Vol corresponding to the voltage value, FB_Cur corresponding to the current value, and FB_Temp corresponding to the temperature.

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