Test device for chips

Abstract

The application provides a kind of chip testing device, comprising: base including seat body and installation platform being arranged on seat body, installation platform is used to place chip to be tested;Top cover is movably arranged with base;Test circuit board includes first conductive part, second conductive part and third conductive part, first conductive part, second conductive part and third conductive part are sequentially stacked and are electrically isolated with each other;Probe assembly includes output sub-probe, first input sub-probe and second input sub-probe, output sub-probe is electrically connected with second conductive part, first input sub-probe is electrically connected with first conductive part, second input sub-probe is electrically connected with third conductive part, wherein, second conductive part is used to connect one of positive and negative of power supply, first conductive part and third conductive part are used to connect the other of positive and negative of power supply.The technical scheme of the application can effectively solve the problem of inaccurate detection in related art.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a chip testing apparatus. Background Technology

[0002] In related technologies, dynamic testing of silicon carbide power semiconductor dies primarily relies on traditional probe station systems. These systems typically employ a single-probe contact method, coupled with external test circuitry for parameter acquisition. However, traditional probe station systems suffer from significant limitations when testing silicon carbide power semiconductor dies under high voltage, high frequency, and high current conditions due to the influence of parasitic inductance. In other words, the long probe connections and complex signal paths of traditional probe stations result in high parasitic inductance in the power circuit. During dynamic testing, especially under high current change rates, this parasitic inductance can cause significant voltage overshoot and waveform distortion, severely impacting the accuracy and reliability of measurement results. Besides silicon carbide power semiconductor dies, the testing of other chips also faces this problem. Summary of the Invention

[0003] The main objective of this invention is to provide a chip testing device to solve the problem of inaccurate testing in related technologies.

[0004] To achieve the above objectives, the present invention provides a chip testing apparatus, comprising: a base, including a seat body and a mounting stage disposed on the seat body, the mounting stage being used to place the chip to be tested; a top cover, movably disposed relative to the base; a test circuit board disposed on the top cover, the test circuit board including a first conductive portion, a second conductive portion, and a third conductive portion, the first conductive portion, the second conductive portion, and the third conductive portion being stacked sequentially and electrically isolated from each other; and a probe assembly disposed on the top cover, the probe assembly being used to electrically connect to the chip to be tested, the probe assembly including an output sub-probe, a first input sub-probe, and a second input sub-probe, the output sub-probe being electrically connected to the second conductive portion, the first input sub-probe being electrically connected to the first conductive portion, and the second input probe being electrically connected to the third conductive portion, wherein the second conductive portion is used to connect to one of the positive and negative terminals of a power supply, and the first and third conductive portions are used to connect to the other of the positive and negative terminals of the power supply.

[0005] Furthermore, the projections of the first conductive part and the third conductive part on the surface of the top cover facing the base completely overlap.

[0006] Furthermore, the first conductive part, the second conductive part, and the third conductive part all extend along the first direction, and the first conductive part and the second conductive part are staggered in the second direction, wherein the second direction is perpendicular to the first direction and parallel to the surface of the top cover facing the base.

[0007] Furthermore, the first conductive part and the second conductive part have a misalignment distance D1 in the second direction, and the second conductive part has a width dimension D2 in the second direction. The ratio of the misalignment distance D1 to the width dimension D2 satisfies: 0.66≤D1 / D2≤0.1.

[0008] Furthermore, the misalignment distance D1 satisfies: 1.6mm≤D1≤2.4mm; and / or, the width dimension D2 satisfies: 19.2mm≤D2≤28.8mm.

[0009] Furthermore, the test circuit board also includes a first insulating layer and a second insulating layer, the first insulating layer being disposed between the first conductive portion and the second conductive portion, and the second insulating layer being disposed between the second conductive portion and the third conductive portion.

[0010] Furthermore, the first insulating layer has a thickness dimension D3, which satisfies: 1.49mm≤D3≤2.23mm.

[0011] Furthermore, the mounting platform has a bearing area and an insulating area surrounding the outer periphery of the bearing area. The bearing area is used to bear the chip to be tested, and the insulating area is covered with an insulating part.

[0012] Furthermore, the testing device also includes a negative pressure source, and multiple through holes are provided in the bearing area. All through holes are connected to the negative pressure source to adsorb the chip to be tested in the bearing area.

[0013] Furthermore, the top cover is provided with a groove. When the top cover is docked with the base, the groove and the bearing area together form a sealed cavity. The chip to be tested is located in the sealed cavity. The base is provided with an inert gas input pipe that communicates with the sealed cavity, and the top cover is provided with a gas outlet that communicates with the sealed cavity.

[0014] Furthermore, a pressure reducing valve and / or flow meter are installed on the inert gas inlet pipe.

[0015] Furthermore, the output sub-probe includes a first rod, a second rod, and an elastic element. The first rod and the second rod are nested together. The end of the first rod away from the second rod is connected to the top cover. The second rod is movably disposed relative to the first rod. The end of the second rod away from the first rod is used for electrical connection with the chip under test. The elastic element is disposed in the first rod and abuts against the second rod.

[0016] According to the technical solution of this invention, the base includes a seat and a mounting platform disposed on the seat. The mounting platform is used to place the chip to be tested for testing. The top cover is movable relative to the base. A probe assembly is disposed on the top cover and is used to electrically connect with the chip to be tested. The top cover moves to electrically connect or disconnect the probe assembly from the chip to be tested, thereby forming or disconnecting the test circuit. The test circuit board includes a first conductive part, a second conductive part, and a third conductive part. When the power is turned on, current flows out through the second conductive part and flows in through the first and third conductive parts, so that the current direction of the second conductive part is opposite to the current direction of the first and third conductive parts. This device achieves mutual cancellation of local magnetic fields in the power circuit through the design that the current direction of the second conductive part is opposite to the current direction of the first and third conductive parts. This design reduces the parasitic inductance caused by long probe connection lines and complex signal paths in traditional probe station systems, reduces voltage overshoot and test waveform distortion during high current change rate dynamic testing, thereby improving the accuracy of measurement results. Especially under harsh testing conditions such as high voltage, high frequency, and high current, this testing device exhibits superior performance, meeting the precise dynamic testing requirements of silicon carbide power semiconductor dies. By incorporating a test circuit board composed of a first conductive part, a second conductive part, and a third conductive part on the top cover, along with a matching probe assembly, the device effectively solves the problem of high parasitic inductance in the dynamic testing of silicon carbide power semiconductor dies. Therefore, the technical solution of this application can effectively address the problem of inaccurate detection in related technologies. Attached Figure Description

[0017] The accompanying drawings, which form part of this application, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings:

[0018] Figure 1 A schematic diagram of a portion of the structure of a test circuit board according to an embodiment of the test apparatus of the present invention is shown;

[0019] Figure 2 It shows Figure 1 A three-dimensional structural diagram of the testing device;

[0020] Figure 3 It shows Figure 1 A schematic diagram of the split structure of the testing device;

[0021] Figure 4 It shows Figure 1 A three-dimensional structural diagram of the top cover and part of the test circuit board of the test device;

[0022] Figure 5 It shows Figure 1A three-dimensional structural diagram of part of the mounting platform of the testing device;

[0023] Figure 6 It shows Figure 1 A schematic diagram of the partial structure of the probe assembly of the testing device.

[0024] The above figures include the following reference numerals:

[0025] 10. Base; 11. Seat body; 12. Mounting platform; 121. Bearing area; 122. Insulation area; 123. Through hole;

[0026] 20. Top cover;

[0027] 30. Test circuit board; 31. First conductive part; 32. Second conductive part; 33. Third conductive part; 34. First insulating layer; 35. Second insulating layer;

[0028] 40. Probe assembly; 41. Output sub-probe; 411. First rod; 412. Second rod; 413. Elastic element;

[0029] 50. Inert gas inlet pipe. Detailed Implementation

[0030] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the present invention or its application or use. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0032] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention. It should also be understood that, for ease of description, the dimensions of the various parts shown in the drawings are not drawn to actual scale. Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following figures denote similar items; therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0033] like Figures 1 to 6 As shown, this application provides a chip testing device. An embodiment of the testing device includes: a base 10, a top cover 20, a test circuit board 30, and a probe assembly 40. The base 10 includes a seat 11 and a mounting platform 12 disposed on the seat 11, the mounting platform 12 being used to place the chip to be tested. The top cover 20 is movably disposed relative to the base 10. The test circuit board 30 is disposed on the top cover 20, and the test circuit board 30 includes a first conductive portion 31, a second conductive portion 32, and a third conductive portion 33, which are stacked sequentially. The probe assembly 40 is disposed on the top cover 20 and is electrically isolated from each other. The probe assembly 40 is used to electrically connect with the chip under test. The probe assembly 40 includes an output sub-probe 41, a first input sub-probe and a second input sub-probe. The output sub-probe 41 is electrically connected to the second conductive part 32, the first input sub-probe is electrically connected to the first conductive part 31, and the second input probe is electrically connected to the third conductive part 33. The second conductive part 32 is used to connect to one of the positive and negative terminals of the power supply, and the first conductive part 31 and the third conductive part 33 are used to connect to the other of the positive and negative terminals of the power supply.

[0034] Applying the technical solution of this embodiment, the base 10 includes a seat 11 and a mounting platform 12 disposed on the seat 11. The mounting platform 12 is used to place the chip to be tested for testing. The top cover 20 is movably disposed relative to the base 10. The probe assembly 40 is disposed on the top cover 20 and is used to electrically connect with the chip to be tested. The top cover 20 is moved to electrically connect or disconnect the probe assembly 40 from the chip to be tested, thereby forming or disconnecting the test circuit. The test circuit board 30 includes a first conductive part 31, a second conductive part 32, and a third conductive part 33. When the power is turned on, the current flows out through the second conductive part 32 and flows in through the first conductive part 31 and the third conductive part 33, so that the current direction of the second conductive part 32 is opposite to the current direction of the first conductive part 31 and the third conductive part 33. This device achieves mutual cancellation of local magnetic fields in the power circuit through the design that the current direction of the second conductive part 32 is opposite to the current direction of the first conductive part 31 and the third conductive part 33. This design reduces parasitic inductance caused by long probe connection lines and complex signal paths in traditional probe station systems, and reduces voltage overshoot and waveform distortion during dynamic testing with high current change rates, thereby improving the accuracy of measurement results. Especially under harsh testing conditions such as high voltage, high frequency, and high current, this testing device exhibits superior performance, meeting the precise dynamic testing requirements of silicon carbide power semiconductor dies. The testing device effectively solves the problem of high parasitic inductance in dynamic testing of silicon carbide power semiconductor dies by setting a test circuit board 30 composed of a first conductive part 31, a second conductive part 32, and a third conductive part 33 on the top cover 20, along with a matching probe assembly 40. Therefore, the technical solution of this embodiment can effectively solve the problem of inaccurate detection in related technologies.

[0035] It should be noted that, besides power semiconductor chips, the testing device of this embodiment can achieve more accurate test results, and other types of chips also achieve the same technical effect when using the testing device of this embodiment. The current flow path is: positive terminal of the power supply, second conductive part 32, output sub-probe 41, chip under test, first input sub-probe, first conductive part 31, negative terminal of the power supply; or, positive terminal of the power supply, second conductive part 32, output sub-probe 41, chip under test, second input sub-probe, third conductive part 33, negative terminal of the power supply. It should be noted that the superposition principle indicates that the magnetic fields generated by multiple currents can be calculated individually and then simply added together to obtain the total magnetic field. This means that the magnetic fields generated by the first conductive part 31, the second conductive part 32, and the third conductive part 33 can be calculated independently, and finally superimposed to obtain the magnetic field distribution inside the entire testing device. When current flows into the first conductive part 31 and the third conductive part 33 respectively, and flows out of the second conductive part 32, since the current directions are opposite, according to the right-hand rule, the first conductive part 31 and the third conductive part 33 generate magnetic fields in opposite directions in their respective vicinity, while the second conductive part 32 generates a magnetic field in another direction in its vicinity. Due to the careful geometric arrangement of these three conductive parts—the projections of the first conductive part 31 and the third conductive part 33 completely coincide, while the second conductive part 32 is offset from them by a certain distance in the planar direction (mentioned later)—the magnetic fields generated by the three current paths are tightly coupled in space. However, due to the clever arrangement of the current directions, the local magnetic fields cancel each other out. Specifically, this design reduces magnetic field fluctuations caused by current changes, reduces parasitic inductance in the circuit, and thus improves the quality of the test waveform under high current change rates, improving the accuracy of the measurement results. This is because parasitic inductance mainly originates from changes in the magnetic field in the current path. Especially when the current changes rapidly, the change in the magnetic field can cause voltage overshoot, affecting the test accuracy. By tightly coupling the current paths in three-dimensional space and ensuring the opposite direction of the currents, changes in the magnetic field can be effectively reduced, parasitic inductance can be lowered, and the accuracy of performance evaluation of power semiconductor chips under dynamic test conditions can be improved.

[0036] Furthermore, the current path of the second conductive part 32 is a forward current inflow path. A forward current inflow path refers to the current transmission path from the power source, through the input terminal of the test device or electronic device, and then through the components in the test object or circuit to complete its predetermined function. In dynamic test devices, the forward current path is typically the power signal injection path, driven by an external power supply. Through specific circuits of the test device (such as a drive circuit), the current is delivered to the electrodes of the silicon carbide power semiconductor die under test, stimulating its dynamic behavior (such as a switching process). The current paths of the first conductive part 31 and the third conductive part 33 are return current paths. A return current path is the path from the output terminal or test object back to the power supply device after the current has completed its predetermined task. In circuit analysis, ideally, the current should follow the "return loop" principle, meaning the paths through which the current flows should be as close as possible to reduce the influence of electromagnetic radiation and parasitic inductance. In dynamic test devices, the return current path is responsible for guiding the current in the power circuit back to the power source, forming a complete current closed loop.

[0037] Furthermore, the current paths of the first conductive part 31 and the third conductive part 33 form a dual return current path. In complex high-frequency circuits or high-power test devices, the dual return current path is mainly used to reduce parasitic inductance and improve the integrity of the test signal. Specifically:

[0038] Magnetic field cancellation: When a forward current path approaches a set of return current paths, they generate interacting magnetic fields. If the second set of return current paths is a perfect mirror image of the first set (discussed later), the magnetic fields on both sides of the forward current path can cancel each other out. This significantly reduces the area of ​​the current loop, thereby lowering parasitic inductance. Lower parasitic inductance means that voltage overshoot and signal distortion are significantly suppressed under high-speed switching or large current changes.

[0039] Signal Balance and Stability: In high-speed electrical testing, dual return paths help achieve current signal balance, thereby improving signal stability (multiple return paths formed by multiple probes connected in parallel have a similar effect). Especially when current and voltage changes very rapidly in the test circuit, unbalanced current paths can lead to electromagnetic interference (EMI) problems, affecting test accuracy and system stability. The dual return path design helps reduce these potential interference factors by ensuring the symmetry of the current loop.

[0040] Thermal Management and Heat Dissipation: Dual return paths also disperse current density, reducing heat buildup in a single current path, which is especially important for testing highly heat-sensitive silicon carbide power semiconductor dies. A well-distributed current path helps improve heat dissipation efficiency and protects the die from overheating.

[0041] Flexibility and Redundancy: Dual return paths offer greater flexibility in circuit design. In certain situations, if one path is disrupted or fails, the other can serve as a backup, ensuring normal circuit operation and continuous testing. This is highly beneficial for improving the reliability and robustness of the test setup.

[0042] like Figures 1 to 6 As shown, the projections of the first conductive part 31 and the third conductive part 33 on the surface of the top cover 20 facing the base 10 completely overlap.

[0043] In this embodiment, the projections of the first conductive part 31 and the third conductive part 33 on the surface of the top cover 20 facing the base 10 completely overlap. This design makes the current distribution between the first conductive part 31 and the third conductive part 33 more uniform, thereby effectively reducing electromagnetic interference caused by uneven current distribution. Since the current directions of the first conductive part 31 and the third conductive part 33 are opposite, the complete overlap of their projections helps to form a symmetrical magnetic field distribution in the vertical direction, further canceling out the magnetic fields generated by each, thereby significantly reducing the parasitic inductance of the entire test device and improving test accuracy and stability. In addition, this structural layout also helps to optimize the space utilization of the test circuit board 30, making the test device more compact and easier to integrate and operate. Of course, in other embodiments not shown in the figure, the projections of the first conductive part 31 and the third conductive part 33 can also be designed to partially overlap. By adjusting the degree of overlap, the electromagnetic shielding effect and the uniformity of current distribution can be balanced to adapt to different test requirements. In this way, the test device can have greater flexibility and applicability while ensuring test accuracy.

[0044] like Figures 1 to 6 As shown, the first conductive part 31, the second conductive part 32 and the third conductive part 33 all extend along the first direction. The first conductive part 31 and the second conductive part 32 are offset in the second direction. The second direction is perpendicular to the first direction and parallel to the surface of the top cover 20 facing the base 10.

[0045] In this embodiment, the first conductive part 31, the second conductive part 32, and the third conductive part 33 all extend along a first direction. The first conductive part 31 and the second conductive part 32 are staggered in a second direction, wherein the second direction is perpendicular to the first direction and parallel to the surface of the top cover 20 facing the base 10. This staggered design, combined with the opposite current direction, can further reduce the interaction of magnetic fields, thereby reducing the parasitic inductance of the test circuit. Through the staggered arrangement on the horizontal plane and the overlap in the vertical direction, a unique three-dimensional current layout is formed, which effectively optimizes the current path and improves the test accuracy. Of course, the specific staggered distance between the first conductive part 31 and the second conductive part 32, and the width of the second conductive part 32, need to be adjusted according to the actual test requirements and chip size to achieve the best inductance reduction effect. This structural design not only reduces electromagnetic interference during testing but also ensures that the test circuit board 30 achieves efficient and accurate current control within a limited space, meeting the stringent requirements of power semiconductor chips in dynamic testing and improving the stability and reliability of the overall test system.

[0046] Furthermore, it should be noted that in the design of the test circuit board 30, offsetting the forward current path of the second conductive part 32 from the return current paths of the first conductive part 31 and the third conductive part 33 by a certain distance in the second direction, while designing them to be parallel in the stacking direction, is an effective strategy for optimizing the current path layout, reducing electromagnetic interference (EMI), and lowering parasitic inductance. The benefits of this offsetting arrangement are mainly reflected in the following aspects:

[0047] Reducing magnetic field coupling: When current flows through a conductive part, it generates a magnetic field around it. When two current paths (especially the forward and return paths) are parallel and close together, the magnetic fields generated between them will couple strongly. By offsetting the current paths in the second direction, the direct coupling of the magnetic fields between the two current paths can be reduced, thereby reducing parasitic inductance. As the offset distance increases, the magnetic field coupling gradually decreases, but an excessively large offset distance can also increase the loop area, which may increase the total inductance. Therefore, selecting the offset distance is an optimization design process that requires finding a balance between reducing magnetic field coupling and controlling the loop area.

[0048] Suppressing crosstalk: In multilayer PCBs, if the current paths between adjacent layers are too close, crosstalk will occur due to electromagnetic induction, meaning that the signal from one circuit interferes with the signal from another circuit. By offsetting the current paths in the second direction, this crosstalk can be significantly reduced, especially for the transmission paths of high-speed digital signals or high-frequency analog signals, thus avoiding signal quality degradation.

[0049] Improving signal integrity: In high-speed circuits, signal integrity is a critical design consideration. Proper current path layout (including staggered designs) helps reduce signal reflections and cross-layer propagation delays, ensuring signal quality and stability during transmission. This is essential for the lossless transmission of clock signals, data signals, and other high-speed signals.

[0050] Enhanced Electromagnetic Compatibility (EMC): Staggered placement can reduce electromagnetic radiation generated by the circuit, improve the EMC of the PCB, and reduce interference with external devices. This design strategy is particularly critical in applications with stringent EMC requirements, such as wireless communication equipment and medical electronic equipment.

[0051] Thermal management: Current flowing through a conductor generates heat. Properly arranging the current path helps disperse heat sources and improves PCB thermal management. By staggering the current paths in the second direction, current paths can be prevented from concentrating in a single area, thereby reducing localized heat accumulation and improving circuit cooling efficiency.

[0052] like Figures 1 to 6 As shown, the first conductive part 31 and the second conductive part 32 have a misalignment distance D1 in the second direction, and the second conductive part 32 has a width dimension D2 in the second direction. The ratio of the misalignment distance D1 to the width dimension D2 satisfies: 0.66≤D1 / D2≤0.1.

[0053] In this embodiment, this design, by controlling the relative positions of the first conductive part 31 and the second conductive part 32 on the horizontal plane, can form a specific current path in three-dimensional space, thereby effectively reducing the parasitic inductance of the loop. In practical applications, by adjusting the ratio of D1 / D2, the current distribution can be optimized, electromagnetic interference reduced, and more accurate dynamic testing of power semiconductor chips achieved. As the offset distance increases, the magnetic field coupling gradually decreases, but an excessively large offset distance will also increase the loop area, which may increase the total inductance. Therefore, the selection of the offset distance is an optimization design process, requiring a balance between reducing magnetic field coupling and controlling the loop area. Meeting the above ratio requirement satisfies this balance. The ratio of the offset distance D1 to the width dimension D2 can be 0.066, 0.07, 0.075, 0.08, 0.083, 0.09, or 0.1.

[0054] like Figures 1 to 6As shown, the misalignment distance D1 satisfies: 1.6mm ≤ D1 ≤ 2.4mm; the width dimension D2 satisfies: 19.2mm ≤ D2 ≤ 28.8mm. In this embodiment, this design ensures optimized current path, enabling the second conductive part 32 to form optimal electromagnetic coupling with the first conductive part 31 and the third conductive part 33 in space, thereby minimizing the influence of parasitic inductance in the circuit. By controlling the ratio of D1 and D2, the current distribution can be further adjusted to achieve finer magnetic field cancellation and improve test accuracy. The misalignment distance D1 can be 1.6mm, 1.82mm, 1.86mm, 2.2mm, 2.33mm, 2.4mm, or XXX. The width dimension D2 can be 19.2mm, 21mm, 23.6mm, 24mm, 25.7mm, 26mm, or 28.8mm.

[0055] like Figures 1 to 6 As shown, the test circuit board 30 also includes a first insulating layer 34 and a second insulating layer 35. The first insulating layer 34 is disposed between the first conductive part 31 and the second conductive part 32, and the second insulating layer 35 is disposed between the second conductive part 32 and the third conductive part 33.

[0056] In this embodiment, the test circuit board 30 further includes a first insulating layer 34 and a second insulating layer 35. The first insulating layer 34 is disposed between the first conductive part 31 and the second conductive part 32, and the second insulating layer 35 is disposed between the second conductive part 32 and the third conductive part 33. This structure ensures electrical isolation between different conductive parts, allowing the first conductive part 31, the second conductive part 32, and the third conductive part 33 to work independently on the same test circuit board 30 without interfering with each other. The presence of the first insulating layer 34 and the second insulating layer 35 not only enhances the insulation performance of the test circuit board 30 but also helps maintain the compactness of the entire test device, reducing the additional volume caused by electrical isolation. By rationally setting the insulating layers between the conductive parts, the test device can realize complex test circuit layouts within a limited space, meeting the requirements of high-precision dynamic testing, while also improving the safety of the testing process. In other embodiments not shown in the figures, in order to further reduce parasitic inductance, the thickness of the first insulating layer 34 and the second insulating layer 35 can be appropriately adjusted to optimize the distance between the conductive parts and achieve optimal electromagnetic compatibility and test performance. In addition, the selection of insulating material is also crucial. Materials with high dielectric constant and low loss factor should be selected to reduce energy loss during signal transmission and improve the accuracy and stability of the test.

[0057] Insulating materials play a crucial role in PCB (Printed Circuit Board) design. They not only provide electrical isolation between conductors in different layers but also affect signal integrity, thermal management, structural strength, and the overall cost of the PCB. Depending on the application requirements, various types of insulating materials can be selected. Here are some common options: FR-4 Epoxy Glass: This is the most commonly used insulating material, composed of epoxy resin-impregnated glass fibers. FR-4 has good dielectric properties, structural strength, and thermal stability, making it suitable for most PCB designs, especially in multilayer boards. Polytetrafluoroethylene (PTFE): Commonly used in PCBs for high-performance radio frequency (RF) and microwave applications. PTFE has a low dielectric constant and loss factor, reducing signal delay and attenuation, while also exhibiting excellent thermal and chemical stability. Ceramic Materials: Such as Alumina, BeO, or SiC. These materials have very high dielectric strength and thermal conductivity, making them suitable for applications requiring extremely high insulation performance and good thermal management, such as PCBs in high-power electronic devices and high-temperature applications. Polymer-based Composites: These include mixtures of various polymers and fillers, such as epoxy resin filled with inorganic minerals (e.g., silica, ceramic particles) to enhance dielectric properties and thermal stability. Air Gap: In certain specialized designs, such as microwave antennas or high-frequency circuits, air can also serve as an insulating layer. This design typically leaves gaps in specific areas of the PCB; air, as a natural insulating material, helps reduce electromagnetic interference (EMI) and improve signal purity. Ceramic-filled Epoxy Resins: This material combines the processability of epoxy resins with the high dielectric strength of ceramic materials, making it suitable for applications requiring a balance of electrical and processing performance. Polyphenylene Sulfide (PPS): PPS possesses excellent dielectric properties and heat resistance, making it suitable for high-temperature and high-frequency electronic equipment.

[0058] like Figures 1 to 6As shown, the first insulating layer 34 has a thickness dimension D3, which satisfies the following condition: 1.49mm ≤ D3 ≤ 2.23mm. In this embodiment, this design ensures electrical isolation between different conductive parts. Simultaneously, by precisely controlling the thickness of the insulating layer, it is possible to reduce interlayer distance while maintaining insulation performance, thereby reducing the impact of parasitic capacitance. In practical applications, an optimized D3 value helps improve test accuracy, especially in high-frequency and high-voltage environments. Smaller parasitic capacitance can reduce signal interference, making test results more accurate and reliable. The thickness dimension D3 of the first insulating layer 34 can be 1.49mm, 1.6mm, 1.88mm, 2mm, 2.1mm, 2.2mm, or 2.23mm.

[0059] like Figures 1 to 6 As shown, the mounting platform 12 has a bearing area 121 and an insulating area 122 surrounding the outer periphery of the bearing area 121. The bearing area 121 is used to bear the chip to be tested, and the insulating area 122 is covered with an insulating portion.

[0060] In this embodiment, the mounting platform 12 is designed with a support area 121 and an insulating area 122. The support area 121 is specifically used to support the chip under test, while the insulating area 122 is arranged around the outer periphery of the support area 121 and covered with an insulating portion. This layout ensures electrical isolation and safety of the chip under test during the testing process, avoids interference between different test circuits, and improves the accuracy and reliability of the test. By providing an insulating portion between the support area 121 and the insulating area 122, current leakage is effectively prevented, ensuring the purity of the test circuit and the accuracy of the measurement results.

[0061] like Figures 1 to 6 As shown, the testing device also includes a negative pressure source, and multiple through holes 123 are provided in the bearing area 121. The multiple through holes 123 are all connected to the negative pressure source to adsorb the chip to be tested in the bearing area 121.

[0062] In this embodiment, the testing device also includes a negative pressure source. Multiple through holes 123 are provided within the bearing area 121, all of which are connected to the negative pressure source to adsorb the chip under test within the bearing area 121. This design utilizes a negative pressure adsorption mechanism to ensure that the chip under test is stably fixed in the bearing area 121 during testing, avoiding testing errors caused by movement or vibration, and enhancing the reliability and accuracy of the test.

[0063] By providing a through-hole connected to a negative pressure source in the bearing area 121, the chip under test can be adsorbed and precisely calibrated before the test begins, thereby establishing a stable electrical connection with the probe assembly 40. This optimization is particularly suitable for high-precision testing environments, such as high voltage, high frequency, and high current conditions, effectively preventing minute displacement of the chip during testing and reducing resulting contact problems or signal interference. Furthermore, negative pressure adsorption helps improve testing efficiency, shortens chip replacement and positioning time, is suitable for batch testing scenarios, and enhances the stability and practicality of the entire testing system.

[0064] like Figures 1 to 6 As shown, the top cover 20 is provided with a groove. When the top cover 20 is docked with the base 10, the groove and the bearing area 121 together form a sealed cavity. The chip to be tested is located in the sealed cavity. The base 10 is provided with an inert gas input pipe 50 that communicates with the sealed cavity, and the top cover 20 is provided with a gas outlet that communicates with the sealed cavity.

[0065] In this embodiment, the top cover 20 has a groove. When it mates with the base 10, the groove and the bearing area 121 together form a sealed cavity, allowing the chip under test to be placed inside the sealed cavity. The base 10 is equipped with an inert gas inlet pipe 50 connected to the sealed cavity, while the top cover 20 has a gas outlet. Together, they can inject inert gas into the sealed cavity and expel the existing air, thereby creating an inert gas atmosphere area that isolates the external environment. This design aims to provide a stable testing environment, preventing external contaminants from affecting the chip during testing. It also allows for adjustment of the gas pressure and temperature within the sealed cavity to adapt to different testing conditions, ensuring the accuracy and reliability of the test. Furthermore, a temperature control device can be added inside the sealed cavity to precisely control the temperature during testing, improving the accuracy and stability of chip testing. Through these measures, the power semiconductor chip testing device of this embodiment can effectively reduce external interference, providing strong support for high-precision testing.

[0066] Furthermore, in this embodiment, a pressure reducing valve and / or a flow meter are installed on the inert gas inlet pipe 50. This configuration can precisely control the pressure and flow rate of the inert gas entering the sealed cavity, ensuring the stability and safety of the test environment. The pressure reducing valve is used to reduce the pressure of the high-pressure inert gas source to a level suitable for the environment inside the sealed cavity, while the flow meter can monitor the gas flow rate to prevent excessive or insufficient gas from affecting the test results. Through this precise gas control, the test device can create an ideal test atmosphere, further improving the accuracy and reliability of the test. Of course, in other embodiments not shown in the figure, pressure reducing valves or flow meters can be selectively used according to actual needs, or other forms of pressure and flow control devices can be adopted to adapt to different test conditions and requirements.

[0067] like Figures 1 to 6 As shown, the output sub-probe 41 includes a first rod 411, a second rod 412, and an elastic member 413. The first rod 411 and the second rod 412 are nested together. The end of the first rod 411 away from the second rod 412 is connected to the top cover 20. The second rod 412 is movably disposed relative to the first rod 411. The end of the second rod 412 away from the first rod 411 is used for electrical connection with the chip under test. The elastic member 413 is disposed inside the first rod 411 and abuts against the second rod 412.

[0068] In this embodiment, the output sub-probe 41 includes a first rod 411, a second rod 412, and an elastic element 413. The first rod 411 and the second rod 412 are nested, with one end of the first rod 411 fixedly connected to the top cover 20 and the other end movingly engaged with the second rod 412. The distal end of the second rod 412 is designed to establish an electrical connection with the chip under test, while the elastic element 413, which abuts against the first rod 411, ensures stable contact of the second rod 412 during testing, maintaining a good electrical connection even in the presence of minor surface irregularities or chip displacement. This structural design effectively improves the adaptability and reliability of the probe assembly 40, enabling the testing device to handle different types of power semiconductor chips and maintain stable performance under extreme conditions such as high voltage, high frequency, and high current, thereby improving the accuracy and repeatability of the test. The intervention of the elastic element 413 can also reduce chip damage caused by hard contact and extend the service life of the testing equipment. In addition, the nested design of the first rod 411 and the second rod 412 helps to reduce the overall size of the test device, achieve a compact structure, further reduce parasitic inductance, and improve test accuracy.

[0069] In the description of this invention, it should be understood that "a plurality of" means two or more. Directional terms such as "front, back, up, down, left, right," "horizontal, vertical, perpendicular, horizontal," and "top, bottom" indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings. These terms are used solely for the convenience of describing the invention and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as limiting the scope of protection of this invention. The directional terms "inner" and "outer" refer to the inner or outer contours relative to the outline of each component itself.

[0070] For ease of description, spatial relative terms such as "above," "on top of," "on the upper surface of," "above," etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation of the device as described in the figures. For example, if the device in the figures were inverted, a device described as "above" or "on top of" other devices or structures would subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein will be interpreted accordingly.

[0071] Furthermore, it should be noted that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore should not be construed as limiting the scope of protection of this invention.

[0072] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A chip testing device, characterized in that, include: The base (10) includes a seat (11) and a mounting platform (12) disposed on the seat (11), the mounting platform (12) being used to place the chip to be tested; The top cover (20) is movably disposed relative to the base (10); A test circuit board (30) is disposed on the top cover (20). The test circuit board (30) includes a first conductive part (31), a second conductive part (32) and a third conductive part (33). The first conductive part (31), the second conductive part (32) and the third conductive part (33) are stacked in sequence and electrically isolated from each other. A probe assembly (40) is disposed on the top cover (20). The probe assembly (40) is used to electrically connect with the chip under test. The probe assembly (40) includes an output sub-probe (41), a first input sub-probe, and a second input sub-probe. The output sub-probe (41) is electrically connected to the second conductive part (32). The first input sub-probe is electrically connected to the first conductive part (31). The second input sub-probe is electrically connected to the third conductive part (33). The second conductive part (32) is used to connect to one of the positive and negative terminals of the power supply. The first conductive part (31) and the third conductive part (33) are used to connect to the other of the positive and negative terminals of the power supply.

2. The testing apparatus according to claim 1, characterized in that, The projections of the first conductive part (31) and the third conductive part (33) on the surface of the top cover (20) facing the base (10) are completely coincident.

3. The testing apparatus according to claim 2, characterized in that, The first conductive part (31), the second conductive part (32) and the third conductive part (33) all extend along a first direction. The first conductive part (31) and the second conductive part (32) are offset in a second direction. The second direction is perpendicular to the first direction and parallel to the surface of the top cover (20) facing the base (10).

4. The testing apparatus according to claim 3, characterized in that, The first conductive part (31) and the second conductive part (32) have a misalignment distance D1 in the second direction, and the second conductive part (32) has a width dimension D2 in the second direction. The ratio of the misalignment distance D1 to the width dimension D2 satisfies: 0.66≤D1 / D2≤0.

1.

5. The testing apparatus according to claim 4, characterized in that, The misalignment distance D1 satisfies: 1.6mm ≤ D1 ≤ 2.4mm; and / or, The width dimension D2 satisfies: 19.2mm≤D2≤28.8mm.

6. The testing apparatus according to claim 1, characterized in that, The test circuit board (30) further includes a first insulating layer (34) and a second insulating layer (35), wherein the first insulating layer (34) is disposed between the first conductive part (31) and the second conductive part (32), and the second insulating layer (35) is disposed between the second conductive part (32) and the third conductive part (33).

7. The testing apparatus according to claim 6, characterized in that, The first insulating layer (34) has a thickness dimension D3, which satisfies: 1.49mm≤D3≤2.23mm.

8. The testing apparatus according to any one of claims 1 to 7, characterized in that, The mounting platform (12) has a bearing area (121) and an insulating area (122) surrounding the outer periphery of the bearing area (121). The bearing area (121) is used to bear the chip to be tested, and the insulating area (122) is covered with an insulating portion.

9. The testing apparatus according to claim 8, characterized in that, The testing device also includes a negative pressure source, and a plurality of through holes (123) are provided in the bearing area (121). The plurality of through holes (123) are all connected to the negative pressure source to adsorb the chip to be tested into the bearing area (121).

10. The testing apparatus according to claim 8, characterized in that, The top cover (20) is provided with a groove. When the top cover (20) is connected to the base (10), the groove and the bearing area (121) together form a sealed cavity. The chip to be tested is located in the sealed cavity. The base (10) is provided with an inert gas input pipe (50) that communicates with the sealed cavity. The top cover (20) is provided with a gas outlet that communicates with the sealed cavity.

11. The testing apparatus according to claim 10, characterized in that, The inert gas inlet pipe (50) is equipped with a pressure reducing valve and / or a flow meter.

12. The testing apparatus according to any one of claims 1 to 7, characterized in that, The output sub-probe (41) includes a first rod (411), a second rod (412), and an elastic element (413). The first rod (411) and the second rod (412) are nested together. The end of the first rod (411) away from the second rod (412) is connected to the top cover (20). The second rod (412) is movably disposed relative to the first rod (411). The end of the second rod (412) away from the first rod (411) is used for electrical connection with the chip under test. The elastic element (413) is disposed inside the first rod (411) and abuts against the second rod (412).

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