A mixed low-bit quantization bistatic synchronization method, device and electronic equipment

Abstract

The application discloses a kind of mixed low bit quantization bistatic synchronization method, device and electronic equipment, method includes: generating LFM signal, extracting symbol bit after taking complex conjugate, as reference signal symbol bit sequence save;The echo signal received is down-converted and low-pass filtered, and baseband echo signal is obtained;The baseband echo signal and the reference signal symbol bit sequence are XORed, and the operation result is accumulated using a multi-stage pipeline structure, and the accumulation result is output;According to the accumulation result, relevant peak detection is carried out using dynamic threshold peak detection method to determine synchronization point, thereby providing a kind of double station synchronization method with high computational efficiency, strong anti-interference ability and robustness.

Description

Technical Field

[0001] This invention belongs to the field of signal processing technology, specifically relating to a dual-station synchronization method, apparatus, and electronic equipment using hybrid low-bit quantization. Background Technology

[0002] Bistatic radars, with their separate transmitting and receiving stations (at considerable distances) and silent receiving stations, possess excellent resistance to active directional jamming and anti-radiation missile capabilities. Furthermore, when conducting high-precision detection of long-range targets, this system also offers advantages such as enhanced cross-sectional area, clutter tuning suppression, and improved vertical plane resolution, making it highly valued in the radar field.

[0003] However, bistatic radars need to solve the time synchronization problem between transceiver stations—the receiving station must accurately know the start time of the transmitted pulse as a reference for subsequent signal processing.

[0004] For the dual-station synchronization problem, the conventional method is to perform cross-correlation operations on the received signals, but this is computationally inefficient and has high hardware requirements. To optimize efficiency, a scheme was proposed to design a training sequence (preamble) with conjugate symmetry: using conjugate sequence segments for correlation operations, thereby reducing the computational complexity of complex multiplication and addition to 1 / 2 and 1 / 3 of that of the traditional method, respectively. Although this method significantly reduces the computational complexity, it does not completely eliminate multiplication operations, and the hardware implementation complexity remains high. To avoid multiplication operations, subsequent research proposed quantizing the elements of the training sequence into fixed-point numbers that approximate integer powers of 2, replacing multiplication with shift operations. However, this scheme mainly focuses on complexity optimization and does not systematically analyze the loss of synchronization performance caused by quantization noise. Furthermore, its accumulation process does not employ a pipelined structure, affecting the system's timing convergence, and the fixed-threshold correlation peak detection mechanism further affects synchronization accuracy. While the subsequently proposed two-bit quantization synchronization algorithm significantly reduces computational complexity, its anti-interference capability is significantly reduced.

[0005] Therefore, how to provide a dual-station synchronization method that is computationally efficient, has strong anti-interference ability, and is robust has become an important issue. Summary of the Invention

[0006] To address the aforementioned problems in the prior art, this invention provides a dual-station synchronization method, apparatus, and electronic device using hybrid low-bit quantization.

[0007] The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides a dual-station synchronization method with hybrid low-bit quantization, the dual-station synchronization method comprising: Generate an LFM signal, extract the sign bit after taking the complex conjugate, and save it as a reference signal sign bit sequence; The received echo signal is down-converted and low-pass filtered to obtain the baseband echo signal; The baseband echo signal and the reference signal symbol bit sequence are XORed, and the result is accumulated using a multi-stage pipeline structure to output the accumulated result. Based on the accumulated results, a dynamic threshold peak detection method is used to detect relevant peaks and determine the synchronization point in order to achieve dual-station synchronization.

[0008] Secondly, the present invention provides a dual-station synchronization device with hybrid low-bit quantization, the dual-station synchronization device comprising: The extraction module is used to generate the LFM signal, extract the sign bit after taking the complex conjugate, and save it as a reference signal sign bit sequence. The processing module is used to perform down-conversion and low-pass filtering on the received echo signal to obtain the baseband echo signal; The accumulation module is used to perform an XOR operation on the baseband echo signal and the symbol bit sequence of the reference signal, and to accumulate the operation result using a multi-stage pipeline structure, and output the accumulation result. The determination module is used to determine the synchronization point by using the dynamic threshold peak detection method to detect the relevant peak based on the accumulated result, so as to achieve dual-station synchronization.

[0009] Thirdly, the present invention provides an electronic device, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, used to store computer programs; When a processor executes a computer program stored in memory, it implements the steps described in any of the above-described hybrid low-bit quantization dual-station synchronization methods.

[0010] Fourthly, the present invention provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of the above-described hybrid low-bit quantization dual-station synchronization method.

[0011] The present invention provides a dual-station synchronization method with hybrid low-bit quantization. The hybrid low-bit quantization strategy is to generate an LFM signal, extract only the symbol bits after taking the complex conjugate, and save it as the symbol bit sequence of the reference signal. The echo signal retains the symbol bits and all amplitude information. Compared with extracting only the symbol bits, the anti-interference capability is improved, and compared with retaining all amplitude information, the system complexity and cost are reduced.

[0012] By simplifying the existing complex multiplication into an XOR operation, introducing a multi-stage pipeline structure, and using a dynamic threshold peak detection method to dynamically capture relevant peaks, the influence of preceding and following pulses is eliminated, significantly improving computational efficiency while ensuring system synchronization accuracy.

[0013] The present invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description

[0014] Figure 1 This is a flowchart illustrating a dual-station synchronization method with hybrid low-bit quantization provided in an embodiment of the present invention. Figure 2 This is a flowchart illustrating another dual-station synchronization method with hybrid low-bit quantization provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of the echo signal after down-conversion provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the baseband echo signal provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the accumulation and cross-correlation results provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the operation of the four-stage pipeline accumulation structure provided in the embodiment of the present invention; Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0015] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0016] To address the problems of low computational efficiency, weak anti-interference capability, and poor robustness in existing dual-station synchronization methods, this invention provides a dual-station synchronization method with hybrid low-bit quantization, see [link to relevant documentation]. Figure 1 , Figure 1 This is a flowchart illustrating a dual-station synchronization method with hybrid low-bit quantization provided in an embodiment of the present invention, specifically including the following steps: Step S101: Generate an LFM signal, extract the sign bit after taking the complex conjugate, and save it as a reference signal sign bit sequence.

[0017] In this embodiment of the invention, a broadband linear frequency modulation (LFM) signal with specific parameters can be generated using direct digital frequency synthesis (DDS) technology. These parameters include: pulse width (number of signal points), clock frequency, bandwidth, initial phase, etc.; this signal is denoted as... And by taking its complex conjugate, we obtain Subsequently, from Extract the sign bit information, denoted as x, and store it as a reference signal sign bit sequence. See [link / reference]. Figure 2 , Figure 2 This is a flowchart illustrating another dual-station synchronization method with hybrid low-bit quantization provided in an embodiment of the present invention.

[0018] Step S102: Perform down-conversion and low-pass filtering on the received echo signal to obtain the baseband echo signal.

[0019] In this embodiment of the invention, the received echo signal is down-converted to shift its spectrum to the baseband and high-frequency bands, resulting in: ; in, This represents the echo signal after down-conversion; Indicates signal amplitude; Represents the imaginary unit; Indicates the carrier frequency; Indicates time; Indicates signal bandwidth; Indicates pulse width.

[0020] See Figure 3 , Figure 3 This is a schematic diagram of the down-converted echo signal provided in an embodiment of the present invention. The result diagram is obtained by exporting data from the ILA (Internal Logic Analyzer) to MatLab. The down-converted echo signal is filtered by a low-pass filter to remove high-frequency components, yielding the baseband echo signal. See [link / reference]. Figure 4 , Figure 4 This is a schematic diagram of the baseband echo signal provided in an embodiment of the present invention.

[0021] Step S103: Perform an XOR operation on the baseband echo signal and the symbol bit sequence of the reference signal, and use a multi-stage pipeline structure to accumulate the operation result and output the accumulated result.

[0022] In this embodiment of the invention, the symbol bit quantization method based on the reference signal simplifies the complex multiplication operation of the echo baseband signal and the symbol bit sequence of the reference signal into an XOR operation. The calculation process is as follows: ; in, Indicates the first bit in the reference signal symbol bit sequence The values ​​corresponding to each sampling point; Indicates the first digit in the echo baseband signal The values ​​corresponding to each sampling point; express The real part; express The imaginary part; express The real part; express The imaginary part; Represents the imaginary unit; Simulation results show that the imaginary part of the cross-correlation complex multiplication result can be ignored, thus the above equation can be simplified to: ; for , It can be represented as 16-bit signed data, specifically: ; ; in, Represents the result of the real part operation; The result of the complex multiplication of the real part is 1 bit wide; This represents the magnitude of the complex multiplication result of the real part, which is 15 bits. Indicates the result of the imaginary part operation; This indicates the bit width of the complex multiplication result of the imaginary part, which is 1 bit. This indicates the magnitude of the complex multiplication result of the imaginary part, which is 15 bits. The sign bit of the complex multiplication result is obtained by XORing the sign bits of the baseband echo signal and the reference signal sign bit sequence: ; ; in, This indicates an XOR operation. Since the baseband echo signal is a 16-bit signed number, the most significant bit, i.e., the fifteenth sign bit, is taken and XORed with the reference signal sign bit sequence.

[0023] Since the reference signal symbol bit sequence has no amplitude information, the amplitude information of the complex multiplication depends entirely on the baseband echo signal, i.e.: ; ; Will , Concatenate into 16-bit data to obtain , , spliced ​​together The complex multiplication operation is completed. The receiving clock is 300MHz, and the pulse width of the synchronization LFM signal is 1. Therefore, a total of 300 registers are needed to store the results of complex multiplication operations, denoted as . .

[0024] In this embodiment of the invention, based on the calculation results, a pipeline design is used to perform an accumulation operation.

[0025] Based on 300 calculation results, design a four-stage pipeline accumulation structure, including: The results of every four operations are grouped together and accumulated in parallel, with intermediate results temporarily stored in a buffer register. At each clock cycle, the updated results from the previous stage are passed to the next stage, and this process is repeated level by level until the pipelined parallel accumulation of all 300 complex multiplication results is completed. See [link to documentation]. Figure 5 , Figure 5 This is a schematic diagram of the accumulation and cross-correlation results provided in the embodiments of the present invention.

[0026] In this embodiment of the invention, the multi-stage pipeline structure is a four-stage pipeline accumulation structure, including a first-stage accumulation unit, a second-stage accumulation unit, a third-stage accumulation unit, and a fourth-stage accumulation unit cascaded sequentially. (See also...) Figure 6 , Figure 6 This is a schematic diagram of the operation of the four-stage pipeline accumulation structure provided in the embodiment of the present invention; The first-level accumulation unit is used to accumulate every four operation results in parallel to obtain the first-level accumulation result; The second-level accumulation unit is used to accumulate the first-level accumulation result again to obtain the second-level accumulation result; The third-level accumulation unit is used to simplify the accumulation of the second-level accumulation result to obtain the third-level accumulation result; The fourth-level accumulation unit is used to accumulate the results of the third-level accumulation and output the accumulated result. .

[0027] In this embodiment of the invention, the first-level accumulation unit includes 75 buffer registers; the second-level accumulation unit includes 19 buffer registers; the third-level accumulation unit includes 5 buffer registers; and the fourth-level accumulation unit includes 1 register.

[0028] Step S104: Based on the accumulated results, the dynamic threshold peak detection method is used to detect the relevant peaks and determine the synchronization point in order to achieve dual-station synchronization.

[0029] In this embodiment of the invention, based on the accumulated results, a dynamic threshold peak detection method is used to detect correlation peaks and determine the synchronization point to achieve dual-station synchronization, including: At the beginning of each pulse cycle, the accumulated result is compared with the current relevant peak value; If the accumulated result is greater than or equal to the current correlation peak value, update the current correlation peak value with the accumulated result, and return to the step of performing down-conversion and low-pass filtering on the received echo signal to obtain the baseband echo signal; The system continues until the accumulated result drops to no more than half of the current relevant peak value. At this point, a relevant peak is detected, a synchronization flag signal is output, and the synchronization point is determined.

[0030] Specifically, in the initial stage, the current relevant peak value is set. The initial minimum detection value To avoid the influence of noise, the initial minimum detection value can be set according to the range of noise levels in the experimental scenario.

[0031] A pulse period counter is introduced. When the counter reaches a preset pulse period value, Reset to This ensures that peak detection is performed independently for each pulse cycle; At the beginning of each pulse cycle, the accumulated result is compared with the current correlation peak. If the accumulated result is greater than or equal to the current correlation peak, the current correlation peak is updated with the accumulated result to achieve real-time capture of the correlation peak. Then, the process returns to perform down-conversion and low-pass filtering on the received echo signal to obtain the baseband echo signal, so as to continue to acquire new accumulated results. The peak value is detected using the half-peak detection method within each period, including: The half-peak detection method is used. When the accumulated result drops to no more than half of the current relevant peak value, it is determined to be a falling edge of the relevant peak. The judgment condition is as follows: ; When the falling edge of the correlation peak is detected, a cross-correlation success flag signal is output, and the flag jumps from low to high (rising edge) to determine the synchronization point.

[0032] In this embodiment of the invention, a hybrid low-bit quantization strategy is adopted, that is, an LFM signal is generated, and only the sign bit is extracted after taking the complex conjugate and stored as a reference signal sign bit sequence. The echo signal retains the sign bit and all amplitude information. Compared with only taking the sign bit, the anti-interference capability is improved, and compared with retaining all amplitude information, the system complexity and cost are reduced.

[0033] By simplifying the existing complex multiplication into an XOR operation, introducing a multi-stage pipeline structure, and using a dynamic threshold peak detection method to dynamically capture relevant peaks, the influence of preceding and following pulses is eliminated, significantly improving computational efficiency while ensuring system synchronization accuracy.

[0034] Based on the same inventive concept, embodiments of the present invention also provide a dual-station synchronization device with hybrid low-bit quantization, the dual-station synchronization device comprising: The extraction module is used to generate the LFM signal, extract the sign bit after taking the complex conjugate, and save it as a reference signal sign bit sequence. The processing module is used to perform down-conversion and low-pass filtering on the received echo signal to obtain the baseband echo signal; The accumulation module is used to perform an XOR operation on the baseband echo signal and the symbol bit sequence of the reference signal, and to accumulate the operation result using a multi-stage pipeline structure, and output the accumulation result. The determination module is used to determine the synchronization point by using the dynamic threshold peak detection method to detect the relevant peak based on the accumulated result, so as to achieve dual-station synchronization.

[0035] In this embodiment of the invention, a hybrid low-bit quantization strategy is adopted, that is, an LFM signal is generated, and only the sign bit is extracted after taking the complex conjugate and stored as a reference signal sign bit sequence. The echo signal retains the sign bit and all amplitude information. Compared with only taking the sign bit, the anti-interference capability is improved, and compared with retaining all amplitude information, the system complexity and cost are reduced.

[0036] By simplifying the existing complex multiplication into an XOR operation, introducing a multi-stage pipeline structure, and using a dynamic threshold peak detection method to dynamically capture relevant peaks, the influence of preceding and following pulses is eliminated, significantly improving computational efficiency while ensuring system synchronization accuracy.

[0037] Optionally, the extraction module generates an LFM signal, including: LFM signals are generated using direct digital frequency synthesis (DFD) technology.

[0038] Optionally, the processing module performs down-conversion on the received echo signal, including: ; in, This represents the echo signal after down-conversion; Indicates signal amplitude; Represents the imaginary unit; Indicates the carrier frequency; Indicates time; Indicates signal bandwidth; Indicates pulse width.

[0039] Optionally, the multi-stage pipeline structure is a four-stage pipeline accumulation structure, including a first-stage accumulation unit, a second-stage accumulation unit, a third-stage accumulation unit, and a fourth-stage accumulation unit cascaded in sequence. The first-level accumulation unit is used to accumulate every four operation results in parallel to obtain the first-level accumulation result; The second-level accumulation unit is used to accumulate the first-level accumulation result again to obtain the second-level accumulation result; The third-level accumulation unit is used to simplify the accumulation of the second-level accumulation result to obtain the third-level accumulation result; The fourth-level accumulation unit is used to output the accumulation result by accumulating the results of the third-level accumulation.

[0040] Optionally, the first-level accumulation unit includes 75 buffer registers; the second-level accumulation unit includes 19 buffer registers; the third-level accumulation unit includes 5 buffer registers; and the fourth-level accumulation unit includes 1 register.

[0041] Optionally, the determination module is specifically used to compare the accumulated result with the current correlation peak value at the beginning of each pulse period; if the accumulated result is greater than or equal to the current correlation peak value, update the current correlation peak value with the accumulated result, and return to perform down-conversion and low-pass filtering on the received echo signal to obtain the baseband echo signal; until the accumulated result is detected to drop to no more than half of the current correlation peak value, it is determined that a correlation peak has been detected, a synchronization flag signal is output, and the synchronization point is determined.

[0042] This invention also provides an electronic device, such as... Figure 7 As shown, it includes a processor 701, a communication interface 702, a memory 703, and a communication bus 704, wherein the processor 701, the communication interface 702, and the memory 703 communicate with each other through the communication bus 704. Memory 703 is used to store computer programs; When the processor 701 executes the program stored in the memory 703, it implements the method steps of any of the above-mentioned hybrid low-bit quantization dual-station synchronization methods.

[0043] The communication bus mentioned in the above electronic devices can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of representation, only one thick line is used in the diagram, but this does not indicate that there is only one bus or one type of bus.

[0044] The communication interface is used for communication between the aforementioned electronic devices and other devices.

[0045] The memory may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0046] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0047] The present invention also provides a computer-readable storage medium. A computer program is stored in the computer-readable storage medium, and when executed by a processor, the computer program implements the method steps of any of the above-described hybrid low-bit quantization dual-station synchronization methods.

[0048] Optionally, the computer-readable storage medium may be non-volatile memory (NVM), such as at least one disk storage device.

[0049] Optionally, the aforementioned computer-readable storage medium may also be at least one storage device located remotely from the aforementioned processor.

[0050] In another embodiment of the present invention, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to perform the steps of the method described in any of the above-described hybrid low-bit quantization dual-station synchronization methods.

[0051] It should be noted that the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention.

[0052] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0053] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings and the disclosure in carrying out the claimed invention. In the description of the invention, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.

[0054] The method provided in this invention can be applied to electronic devices. Specifically, the electronic device can be a desktop computer, a portable computer, a smart mobile terminal, a server, etc. No limitation is made herein; any electronic device that can implement this invention falls within the protection scope of this invention.

[0055] For the embodiments of the device / electronic device / storage medium, since they are basically similar to the method embodiments, the description is relatively simple, and relevant parts can be referred to in the description of the method embodiments.

[0056] It should be noted that the device, electronic device and storage medium in the embodiments of the present invention are respectively devices, electronic devices and storage media that apply the above-mentioned hybrid low bit quantization dual-station synchronization method. Therefore, all embodiments of the above-mentioned hybrid low bit quantization dual-station synchronization method are applicable to the device, electronic device and storage medium, and can achieve the same or similar beneficial effects.

[0057] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A dual-station synchronization method with hybrid low-bit quantization, characterized in that, The dual-station synchronization method includes: Generate an LFM signal, extract the sign bit after taking the complex conjugate, and save it as a reference signal sign bit sequence; The received echo signal is down-converted and low-pass filtered to obtain the baseband echo signal; The baseband echo signal and the reference signal symbol bit sequence are XORed, and the result is accumulated using a multi-stage pipeline structure to output the accumulated result. Based on the accumulated results, a dynamic threshold peak detection method is used to detect relevant peaks and determine the synchronization point in order to achieve dual-station synchronization.

2. The dual-station synchronization method according to claim 1, characterized in that, Generating an LFM signal includes: LFM signals are generated using direct digital frequency synthesis (DFD) technology.

3. The dual-station synchronization method according to claim 1, characterized in that, Down-conversion of the received echo signal includes: ； in, This represents the echo signal after down-conversion; Indicates signal amplitude; Represents the imaginary unit; Indicates the carrier frequency; Indicates time; Indicates signal bandwidth; Indicates pulse width.

4. The dual-station synchronization method according to claim 1, characterized in that, The multi-stage pipeline structure is a four-stage pipeline accumulation structure, including a first-stage accumulation unit, a second-stage accumulation unit, a third-stage accumulation unit, and a fourth-stage accumulation unit cascaded in sequence; The first-level accumulation unit is used to accumulate every four operation results in parallel to obtain the first-level accumulation result; The second-level accumulation unit is used to accumulate the first-level accumulation result again to obtain the second-level accumulation result; The third-level accumulation unit is used to simplify the accumulation of the second-level accumulation result to obtain the third-level accumulation result; The fourth-level accumulation unit is used to output the accumulation result by accumulating the results of the third-level accumulation.

5. The dual-station synchronization method according to claim 4, characterized in that, The first-level accumulation unit includes 75 buffer registers; the second-level accumulation unit includes 19 buffer registers; the third-level accumulation unit includes 5 buffer registers; and the fourth-level accumulation unit includes 1 register.

6. The dual-station synchronization method according to claim 1, characterized in that, Based on the accumulated results, a dynamic threshold peak detection method is used to detect correlation peaks and determine the synchronization point to achieve dual-station synchronization, including: At the beginning of each pulse cycle, the accumulated result is compared with the current relevant peak value; If the accumulated result is greater than or equal to the current correlation peak value, update the current correlation peak value with the accumulated result, and return to the step of performing down-conversion and low-pass filtering on the received echo signal to obtain the baseband echo signal; When the accumulated result drops to no more than half of the current relevant peak value, a relevant peak is detected, a synchronization flag signal is output, and a synchronization point is determined.

7. A dual-station synchronization device with hybrid low-bit quantization, characterized in that, The dual-station synchronization device includes: The extraction module is used to generate the LFM signal, extract the sign bit after taking the complex conjugate, and save it as a reference signal sign bit sequence. The processing module is used to perform down-conversion and low-pass filtering on the received echo signal to obtain the baseband echo signal; The accumulation module is used to perform an XOR operation on the baseband echo signal and the symbol bit sequence of the reference signal, and to accumulate the operation result using a multi-stage pipeline structure, and output the accumulation result. The determination module is used to determine the synchronization point by using the dynamic threshold peak detection method to detect the relevant peak based on the accumulated result, so as to achieve dual-station synchronization.

8. The dual-station synchronization device according to claim 7, characterized in that, The extraction module generates an LFM signal, including: LFM signals are generated using direct digital frequency synthesis (DFD) technology.

9. An electronic device, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, when executing a computer program stored in memory, implements the dual-station synchronization method with hybrid low-bit quantization as described in any one of claims 1-6.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the dual-station synchronization method with hybrid low-bit quantization as described in any one of claims 1-6.

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