Inter-core communication method and apparatus, multi-core controller and computer readable storage medium

Abstract

The application discloses a kind of inter-core communication method, device, multi-core controller and computer readable storage medium.The method comprises: obtaining the data encoding information corresponding to target data, the data encoding information includes sending core mask and receiving core mask;The validity check is carried out to the data encoding information, and the validity check result is determined;When the validity check result is check pass, the authority check is carried out based on the sending core mask or the receiving core mask, and the authority check result is determined;When the authority check result is check pass, the target data is transmitted through the inter-core communication queue in target inter-core memory;The target inter-core memory is the inter-core memory related to the authority of the target data to the current core among the two inter-core memories formed between the current core and target core.The method can improve the security and efficiency of inter-core communication, and reduce the load of processor core with higher load.

Description

Technical Field

[0001] This invention relates to the field of inter-core communication technology, and in particular to an inter-core communication method, apparatus, multi-core controller, and computer-readable storage medium. Background Technology

[0002] In existing multi-core controllers of aircraft or other equipment, there are multiple processor cores, each of which performs different functions. Data conflicts may occur during communication between any two processor cores, affecting the security of data transmission. Furthermore, some processor cores may have high loads, affecting the overall performance of multiple controllers. Summary of the Invention

[0003] This invention provides an inter-core communication method, apparatus, multi-core controller, and computer-readable storage medium to address the overall performance issues of security and excessive load during inter-core communication by a multi-core controller.

[0004] An inter-core communication method, comprising: Obtain the data encoding information corresponding to the target data, wherein the data encoding information includes a transmit kernel mask and a receive kernel mask; The data encoding information is validated to determine the validity result. When the validity verification result is successful, permission verification is performed based on the sending kernel mask or the receiving kernel mask to determine the permission verification result. When the permission verification result is successful, the target data is transmitted through the inter-core communication queue in the target inter-core memory; the target inter-core memory is the inter-core memory related to the current core's permission for the target data in the two inter-core memories formed between the current core and the target core.

[0005] Preferably, the current core is a sending core, and the sending core calls the data sending interface to perform the following steps: The data encoding information is validated to determine the validity result. When the validity check result is passed, write permission check is performed on the sending kernel mask based on the current kernel mask to determine the write permission check result; When the write permission verification result is successful, the target data is written to the inter-core communication queue of the first inter-core memory so that the target core can read the target data in the first inter-core memory; Wherein, the first inter-core memory is inter-core memory where the current core has write permissions and the target core has read permissions.

[0006] Preferably, writing the target data into the inter-core communication queue of the first inter-core memory includes: The shadow head pointer of the sending core is synchronized with the physical head pointer of the inter-core communication queue, and the physical head pointer is used to represent the cumulative number of reads of the receiving core; The current state of the inter-core communication queue is determined based on the shadow head pointer and shadow tail pointer of the sending core. If the current state of the inter-core communication queue is not full, the target data is written into the data buffer of the first inter-core memory. After the target data is written, the shadow tail pointer is updated and synchronized with the physical tail pointer of the inter-core communication queue. The physical tail pointer is used to represent the cumulative number of writes to the sending core.

[0007] Preferably, the current core is a receiving core, and the receiving core calls the data receiving interface to perform the following steps: The data encoding information is validated to determine the validity result. When the validity verification result is successful, read permission verification is performed on the received kernel mask based on the current kernel mask to determine the read permission verification result. When the read permission verification result is successful, the target data pre-written by the target core is read from the inter-core communication queue of the second inter-core memory; The second inter-core memory is the inter-core memory where the current core has read permissions and the target core has write permissions.

[0008] Preferably, reading the target data pre-written by the target core from the inter-core communication queue of the second inter-core memory includes: The current state of the inter-core communication queue is determined based on the physical head pointer and physical tail pointer of the inter-core communication queue. If the current state of the inter-core communication queue is not empty, then the target data pre-written by the target core is read from the data buffer corresponding to the second inter-core memory. After the target data is read, the physical head pointer of the inter-core communication queue is updated. The physical head pointer is used to represent the cumulative number of reads by the receiving core.

[0009] Preferably, the step of performing permission verification based on the sending kernel mask or the receiving kernel mask to determine the permission verification result includes: Based on the current kernel mask, perform a bitwise AND operation on either the transmitted kernel mask or the received kernel mask, and determine the bitwise AND operation result; When the result of the bitwise AND operation is 1, the permission verification result is determined to be successful. When the result of the bitwise AND operation is 0, the permission verification result is determined to be verification failure.

[0010] Preferably, before acquiring the data encoding information corresponding to the target data, the inter-core communication method further includes: A linker script is used to create two inter-core memory locations for the current core and the target core, and the permissions of the current core and the target core for each inter-core memory location are determined. Bind the inter-core communication variable corresponding to the inter-core communication queue to the inter-core memory corresponding to the inter-core communication variable.

[0011] An inter-nuclear communication device, comprising: The encoding acquisition module is used to acquire the data encoding information corresponding to the target data, the data encoding information including the sending kernel mask and the receiving kernel mask; The validity verification module is used to verify the validity of the data encoding information and determine the validity verification result. The permission verification module is used to perform permission verification based on the sending kernel mask or the receiving kernel mask when the validity verification result is that the verification is passed, and to determine the permission verification result. The inter-core transmission module is used to transmit the target data through the inter-core communication queue in the target inter-core memory when the permission verification result is successful; the target inter-core memory is the inter-core memory related to the current core's permission to the target data in the two inter-core memories formed between the current core and the target core.

[0012] A multi-core controller includes multiple processor cores as described above; each processor core includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the inter-core communication method described above.

[0013] A computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described inter-core communication method.

[0014] The aforementioned inter-core communication method, apparatus, multi-core controller, and computer-readable storage medium provide two inter-core memories between the current core and the target core. This allows the current core to perform read and write operations on the target data through two independent inter-core memories, avoiding data conflicts and improving the efficiency of inter-core communication. It also enables hardware-level area isolation combined with permission settings to prevent accidental manipulation of the target data, improving the security and reliability of inter-core communication. Furthermore, it reduces the load on some processor cores by sending data from heavily loaded processor cores to less loaded processor cores via their corresponding inter-core memories, thereby reducing the CPU utilization of the heavily loaded processor cores and ultimately lowering the overall load. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a flowchart of an inter-core communication method in an embodiment of the present invention; Figure 2 yes Figure 1 A detailed flowchart of the inter-core communication method is shown. Figure 3 yes Figure 1 Another specific flowchart of the inter-core communication method shown; Figure 4 yes Figure 1 A flowchart of step S103; Figure 5 yes Figure 1 A flowchart preceding step S101; Figure 6 This is a schematic diagram of inter-core memory partitioning in an embodiment of the present invention; Figure 7 This is a schematic diagram of an inter-core communication device in an embodiment of the present invention. Detailed Implementation

[0017] To make the technical problems solved, the technical solutions, and the beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0018] This invention provides an inter-core communication method applicable to communication between any two control cores of a multi-core controller. The method is illustrated using the current core as an example. Figure 1 As shown, the following steps are performed by the current kernel: S101: Obtain the data encoding information corresponding to the target data, including the transmit kernel mask and the receive kernel mask; S102: Perform validity verification on the data encoding information and determine the validity verification result; S103: When the validity check result is that the check passes, perform permission check based on the sent kernel mask or the received kernel mask, and determine the permission check result; S104: When the permission verification result is successful, the target data is transmitted through the inter-core communication queue in the target inter-core memory; the target inter-core memory is the inter-core memory related to the current core's permission for the target data in the two inter-core memories formed between the current core and the target core.

[0019] In this context, the current core is the control core currently executing the inter-core communication method, while the target core is the control core communicating with the current core. For example, the current core could be a security core implementing security functions, and the target core could be another slave core communicating with the security core. The target data is the data to be transmitted. The data encoding information is information formed by encoding relevant information of the target data using pre-set encoding rules. The inter-core communication (IPC) queue is a queue used to enable communication between different control cores.

[0020] As an example, in step S101, the current core obtains the data encoding information corresponding to the target data to be transmitted. This data encoding information indicates relevant information about the target data, specifically including but not limited to a queue type identifier, a sending core mask, a receiving core mask, and a data identifier. The queue type identifier indicates whether it is a queue type; for example, a queue type identifier of 1 indicates a queue type, while a queue type identifier of 0 indicates no queue type. The sending core mask indicates which control core sends the target data; this sending core mask can be a 6-bit mask. The receiving core mask indicates which control core receives the target data; this receiving core mask can also be a 6-bit mask. The data identifier uniquely identifies a specific target data; this data identifier is a 16-bit identifier.

[0021] For example, the target data is encoded using pre-set encoding rules, and its data encoding information is as follows: In this code, `queue` represents the queue type, `sender` represents the sending core mask, `receiver` represents the receiving core mask, and `dataId` represents the data identifier. Therefore, in `#define DATA_ID_DLT_2_MONITOR_CORE4 \ CHANNEL_ID_DEFINE(1, (1<<0), (1<<4), 1)`, 1 indicates the queue type; (1<<0) indicates that Core0 is the sending core, used to send target data; (1<<4) indicates that Core4 is the receiving core, used to receive target data; and 1 represents the data identifier.

[0022] As an example, in step S102, after obtaining the data encoding information, the current core needs to perform a validity check on the data identifier in the data encoding information to verify whether the data encoding information is valid and obtain the validity check result. For example, it can be used to check whether the data identifier (i.e., dataID) is a registered valid identifier. If the data identifier is a registered valid identifier, the validity check result corresponding to the data encoding information is determined to be a successful check; otherwise, if the data identifier is not a registered valid identifier, the validity check result corresponding to the data encoding information is determined to be a failed check. In this example, by performing a validity check on the data encoding information, the validity of the target data transmitted in inter-core communication is ensured.

[0023] As an example, in step S103, when the current core determines that the validity check result is passed, it needs to read its sending core mask and receiving core mask from the data encoding information. Then, based on its own corresponding current core mask, it determines whether the current core mask matches either the sending core mask or the receiving core mask. If the current core mask matches either the sending core mask or the receiving core mask, it can be determined that the current core is either a sending core that needs to send target data or a receiving core that needs to receive target data, and it is assumed that the current core has the authority to process the target data. Therefore, its permission check result is determined to be passed. Conversely, if the current core mask does not match either the sending core mask or the receiving core mask, it can be determined that the current core is neither a sending core that needs to send target data nor a receiving core that needs to receive target data. Therefore, its permission check result is determined to be failed. In this example, permission check is performed based on the sending core mask or the receiving core mask to ensure that the current core is a control core with the authority to process the target data.

[0024] As an example, in step S104, two inter-core memories are pre-created between the current core and the target core. One inter-core memory serves as a one-way channel for sending data from the current core to the target core, and the current core has write permissions. The other inter-core memory serves as a one-way channel for sending data from the target core to the current core, and the current core has read permissions. In this example, when the current core determines that the permission verification result is successful, it can determine its permissions for the target data based on whether the current core is a sending core or a receiving core. It then selects an inter-core memory that matches these permissions and designates it as the target inter-core memory, enabling the transmission of target data through this target inter-core memory.

[0025] For example, two inter-core memories, A and B, can be established between the current core and the target core. Inter-core memory A can be written to by the current core and read by the target core, while inter-core memory B can be written to by the target core and read by the current core. In other words, the current core has write permissions to inter-core memory A and read permissions to inter-core memory B. When the current core sends target data to the target core, it can write the target data to the inter-core communication queue corresponding to inter-core memory A. Conversely, when the current core receives target data sent by the target core, it can read the target data through the inter-core communication queue in inter-core memory B.

[0026] For example, the data structure used by the inter-core communication queue is as follows: As shown above, the data structure used in the inter-core communication queue includes a data buffer, physical pointers, and shadow pointers. The data buffer stores data, restricting the sending core to write access only and the receiving core to read access only. The physical pointer points to index values ​​in the inter-core memory of the multi-core controller. These are queue indices accessible to all control cores, but their access cost is relatively high. Specifically, it includes a physical tail pointer (tailPtr) and a physical head pointer (headPtr). The tail pointer (tailPtr) indicates the total number of entries written to the inter-core communication queue by the sending core (the cumulative write count), which is written by the sending core and read by the receiving core. The head pointer (headPtr) indicates the total number of entries read from the inter-core communication queue by the receiving core (the cumulative read count), which is written by the receiving core and received by the sending core. The shadow pointer is an index value cached in the sending core's local memory, synchronized to the physical pointer only when necessary. Specifically, it includes a shadow tail pointer (tailPtr_shadow) and a shadow head pointer (headPtr_shadow). The tail pointer (tailPtr_shadow) is the tail index in local memory, while the head pointer (headPtr_shadow) is the head index in local memory.

[0027] In this embodiment, two inter-core memories are provided between the current core and the target core. This allows the current core to perform read and write operations on the target data through two independent inter-core memories, avoiding data conflicts and improving the efficiency of inter-core communication. Hardware-level area isolation, combined with permission settings, prevents accidental manipulation of the target data, improving the security and reliability of inter-core communication. Furthermore, this also reduces the load on some processor cores. Specifically, processor cores with higher loads can send data to processor cores with lower loads via their corresponding inter-core memories, allowing the lower-load processor cores to process the data, thereby reducing the CPU utilization of the higher-load processor cores and ultimately lowering the overall load.

[0028] In one embodiment, the current core is the sending core, and the sending core calls the data sending interface to perform the following steps: A102: Perform validity verification on the data encoding information and determine the validity verification result; A103: When the validity check result is that the check passes, perform write permission check on the sending kernel mask based on the current kernel mask, and determine the write permission check result; A104: When the write permission verification result is successful, the target data is written to the inter-core communication queue of the first inter-core memory so that the target core can read the target data in the first inter-core memory; Among them, the first inter-core memory is the inter-core memory that the current core has write permission for and the target core has read permission for.

[0029] Wherein, A102 is a specific implementation of step S102, A103 is a specific implementation of step S103, and A104 is a specific implementation of step S104.

[0030] The data sending interface is a pre-defined interface for sending data, which can be represented by the `QueueSendData` function. The data sending interface includes a validity check function, a write permission check function, and a write operation function. The validity check function verifies the validity of the encoded data and can be represented by `CHANNEL_VALIDATE`. The write permission check function verifies whether the current core has write permissions and can be represented by `DATA_W_ACCESS_CHECK`. The write operation function writes the target data to the inter-core communication queue and can be represented by `IPC_Append`.

[0031] In one example, the code for sending target data by calling the data sending interface is shown below: The following explanation, based on the code above, details the execution process of the current core calling the data sending interface QueueSendData: In step A101, the current core (sending core) obtains the data encoding information corresponding to the target data.

[0032] In step A102, after obtaining the data encoding information, the current core (sending core) needs to perform a validity check on the data encoding information and obtain the validity check result. For example, the current core can use the validity check function CHANNEL_VALIDATE(dataId) to check the data identifier. If the check fails, it returns "ret = E_ID"; if the check passes, it proceeds to step A103.

[0033] In step A103, the current core (sending core) performs write permission verification on the sending core mask in the data encoding information based on the current core mask to determine whether the current core mask matches the sending core mask. This is used to check whether the current core mask has the write permission corresponding to the sending core mask and obtain the write permission verification result. If the verification fails, it returns "ret = E_ACCESS"; if the verification passes, it proceeds to step A104. For example, the current core can perform write permission verification using the write permission verification function DATA_W_ACCESS_CHECK(dataId) to determine the write permission verification result.

[0034] In step A104, when the write permission verification result is successful, the current core (sending core) writes the target data to the inter-core communication queue in the first core inter-core memory, enabling the target core to read the target data from the first core inter-core memory, thus achieving a one-way data transmission effect between cores. For example, when the current core's write permission verification result is successful, it can use the write operation function IPC_Append(dataId, param) to write the target data to the tail of the IPC queue corresponding to the data identifier (dataId), thereby completing the writing of the target data to the first core inter-core memory. This allows the target core to read the target data by accessing the first core inter-core memory, thus completing the inter-core communication process for the target data.

[0035] In this embodiment, when the current core is the sending core and the target core is the receiving core, the target data sent by the current core to the target core is transmitted through the pre-built first inter-core memory. This avoids conflicts between the transmission process of the target data and other data, enables area isolation at the hardware level, prevents accidental operation of the target data, and improves the security of data transmission. In addition, this inter-core communication method does not require a complex locking mechanism, which can reduce system complexity.

[0036] In one embodiment, such as Figure 2 As shown, step A104, which involves writing the target data into the inter-core communication queue of the first inter-core memory, includes: S201: Synchronize the shadow head pointer of the sending core with the physical head pointer of the inter-core communication queue. The physical head pointer is used to represent the cumulative number of reads by the receiving core. S202: Determine the current state of the inter-core communication queue based on the shadow head pointer and shadow tail pointer of the sending core; S203: If the current state of the inter-core communication queue is not full, then write the target data into the data buffer of the first inter-core memory; S204: After the target data is written, update the shadow tail pointer and synchronize the updated shadow tail pointer with the physical tail pointer of the inter-core communication queue. The physical tail pointer is used to represent the cumulative number of writes to the sending core.

[0037] As an example, when the current core is the sending core, to write the target data into the inter-core communication queue in the first core's inter-core memory, the following steps need to be performed in sequence: In step S201, the current core (sending core) first synchronizes its own shadow head pointer with the physical head pointer. The physical head pointer is the pointer that the receiving core updated most recently. Before performing a write operation, the shadow head pointer of the sending core is synchronized with the physical head pointer so that the sending core can determine the cumulative number of reads of the receiving core and ensure the accuracy of the judgment result of whether the inter-core communication queue is full.

[0038] In step S202, the current core (sending core) determines whether the current state of the inter-core communication queue is full based on the sending core's shadow head pointer and shadow tail pointer. In this example, the shadow head pointer represents the cumulative number of reads that the sending core has just synchronized from the physical head pointer, while the shadow tail pointer represents the cumulative number of writes. By calculating the difference between the shadow tail pointer and the shadow head pointer, the current occupied capacity of the inter-core communication queue can be determined, that is, the capacity occupied by data that has been written but not read. Then, the current occupied capacity is compared with the queue's physical capacity (i.e., the maximum capacity that the queue can withstand). If the current occupied capacity is greater than the queue's physical capacity, the current state of the inter-core communication queue is determined to be full, and the operation is exited to avoid newly written target data overwriting previously written but unread data. If the current occupied capacity is not greater than the queue's physical capacity, the current state of the inter-core communication queue is determined to be not full, and step S203 is executed.

[0039] In step S203, when the current core (sending core) determines that the current state of the inter-core communication queue is not full, it writes the target data into the data buffer of the first inter-core memory to avoid the target data overwriting the data that was written earlier but not read.

[0040] In step S204, after the target data is written to the data buffer, the current core (sending core) updates the shadow tail pointer, i.e., tailPtr_shadow = tailPtr_shadow + 1, which updates the cumulative number of target data written.

[0041] In step S205, after updating the shadow tail pointer, the current core (sending core) needs to synchronize the updated shadow tail pointer with the physical tail pointer so that the receiving core can know the cumulative number of target data written by the sending core to the inter-core memory based on the synchronized physical tail pointer.

[0042] In this embodiment, the sending core will only synchronize the updated shadow tail pointer with the physical tail pointer after the target data has been completely written into the data buffer, thereby reducing inter-core memory access and reducing performance loss. Since the shadow pointer is a variable in local memory, even if the update is interrupted, it will not destroy the physical tail pointer in the inter-core memory, thus ensuring interrupt safety. The physical tail pointer is only modified by the sending core and is read-only by the receiving core, so no locking is required during synchronization, only a memory barrier is needed to ensure the instruction order.

[0043] In one embodiment, the current core is the receiving core, and the receiving core calls the data receiving interface to perform the following steps: B102: Perform validity verification on the data encoding information and determine the validity verification result; B103: When the validity check result is successful, perform read permission check on the received kernel mask based on the current kernel mask, and determine the read permission check result; B104: When the read permission verification result is successful, read the target data pre-written by the target core from the inter-core communication queue of the second inter-core memory; The second inter-core memory is the inter-core memory where the current core has read permissions and the target core has write permissions.

[0044] Wherein, B102 is another specific implementation of step S102, B103 is another specific implementation of step S103, and B104 is another specific implementation of step S104.

[0045] The data receiving interface is a pre-defined interface for receiving data, which can be represented by the `QueueReceiveData` function. The data receiving interface includes a validity check function, a read permission check function, and a read operation function. The validity check function verifies the validity of the data identifier in the data encoding information and can be represented by `CHANNEL_VALIDATE`; it is the same function as the validity check function in the data sending interface. The read permission check function verifies whether the current core has read permissions and can be represented by `DATA_R_ACCESS_CHECK`. The read operation function reads data from the inter-core communication queue and can be represented by `IPC_Take`.

[0046] In this example, the code for the receiving kernel to call the data receiving interface to receive the target data is shown below: The following explanation, based on the code above, details the execution process of the current core calling the data receiving interface QueueReceiveData.

[0047] In step B101, the current core (receiving core) obtains the data encoding information corresponding to the target data.

[0048] In step B102, after obtaining the data encoding information, the current core (receiving core) needs to perform a validity check on the data encoding information and obtain the validity check result. For example, the current core can use the validity check function CHANNEL_VALIDATE(dataId) to check the data identifier. If the check fails, it returns "ret = E_ID"; if the check passes, it proceeds to step B103.

[0049] In step B103, the current core (receiving core) performs read permission verification on the receiving core mask in the data encoding information based on the current core mask to determine whether the current core mask matches the receiving core mask. This is used to check whether the current core mask has the read permission corresponding to the receiving core mask and obtain the read permission verification result. If the verification fails, it returns "ret = E_ACCESS"; if the verification passes, it proceeds to step B104. For example, the current core can perform read permission verification using the read permission verification function DATA_R_ACCESS_CHECK(dataId) to determine the read permission verification result.

[0050] In step B104, when the read permission verification result is successful, the current core (receiving core) reads the target data pre-written by the target core from the inter-core communication queue in the second core memory to achieve one-way data reception between cores. For example, when the read permission verification result is successful, the current core can use the read operation function IPC_Take(dataId, param) to read the target data pre-written by the target core into the second core memory from the IPC queue corresponding to the data identifier (dataId) to complete the inter-core communication process of the target data.

[0051] In this embodiment, when the current core is the receiving core and the target core is the sending core, the current core reads the target data sent by the target core through the pre-built second inter-core memory. This avoids conflicts between the target data and other data during the transmission process, enables area isolation at the hardware level, prevents accidental operation of the target data, and improves the security of data transmission. In addition, this inter-core communication method does not require a complex locking mechanism, which can reduce system complexity.

[0052] In one embodiment, such as Figure 3 As shown, step B104, which involves reading the target data pre-written by the target core from the inter-core communication queue in the second inter-core memory, includes: S301: Determine the current state of the inter-core communication queue based on the physical head pointer and physical tail pointer of the inter-core communication queue; S302: If the current state of the inter-core communication queue is not empty, then read the target data pre-written by the target core from the data buffer corresponding to the second inter-core memory; S303: After the target data is read, update the physical head pointer of the inter-core communication queue. The physical head pointer is used to represent the cumulative number of reads by the receiving core.

[0053] As an example, when the current core is the receiving core, the receiving core needs to read the target data pre-written by the target core from the inter-core communication queue in the second core memory, and needs to perform the following steps in sequence: In step S301, the current core (receiving core) needs to read the physical head pointer and physical tail pointer of the inter-core communication queue to determine whether the current state of the inter-core communication queue is empty. In this example, the physical head pointer represents the cumulative read count updated by the receiving core, while the physical tail pointer represents the cumulative write count updated by the sending core. By comparing whether the two values ​​are consistent, it is determined whether the current state of the inter-core communication queue is empty. Specifically, when the physical head pointer and physical tail pointer are the same, it indicates that the cumulative read count of the receiving core is consistent with the cumulative write count of the sending core, and it can be determined that the current state of the inter-core communication queue is empty, requiring the operation to end; when the physical head pointer is less than the physical tail pointer, it indicates that the cumulative read count of the receiving core is inconsistent with the cumulative write count of the sending core, indicating that there is unread target data, and it can be determined that the current state of the inter-core communication queue is not empty.

[0054] In step S302, when the current core (receiving core) determines that the current state of the inter-core communication queue is not empty, it needs to read the target data pre-written by the target core (sending core) from the data buffer corresponding to the second inter-core memory, so as to achieve the effect of reading the target data from the one-way transmission channel.

[0055] In step S303, after the current core (receiving core) finishes reading the target data, it needs to update the physical header pointer of the inter-core communication queue, i.e., tailPtr=tailPtr+1, in order to update the cumulative number of reads of the receiving core in real time so that the sending core and the receiving core can synchronize data.

[0056] In this embodiment, the receiving core will only read the target data from the second inter-core memory when it determines that the current state of the inter-core communication queue is not empty and that there is unread target data in the inter-core communication queue. After the target data is read, the physical header pointer of the inter-core communication queue needs to be updated so that the sending core can update the cumulative read count in real time by synchronizing the physical header pointer when sending the target data next time, thus ensuring data synchronization.

[0057] In one embodiment, such as Figure 4 As shown, step S103, which involves performing permission verification based on the sent or received kernel mask and determining the permission verification result, includes: S401: Perform a bitwise AND operation on the basis of the current core mask with respect to the transmit core mask or the receive core mask to determine the result of the bitwise AND operation; S402: When the result of the bitwise AND operation is 1, determine that the permission verification result is verification passed; S403: When the result of the bitwise AND operation is 0, determine that the permission verification result is verification failed.

[0058] As an example, when the current core is the transmit core, it is necessary to perform a bitwise AND operation on the current core mask with the transmit core mask in the data encoding information, and determine the write permission verification result according to the result of the bitwise AND operation. For example, the bitwise AND operation can be performed using DATA_W_ACCESS_CHECK(dataId) ((1u<<CORE_ID)&DATA_ID_SENDER(dataId)), where 1u<<CORE_ID is the current core mask and DATA_ID_SENDER(dataId) is the transmit core mask. Use the function DATA_W_ACCESS_CHECK(dataId) to perform a bitwise AND operation on these two masks. When the result of the bitwise AND operation is 1, determine that its write permission verification result is verification passed, that is, determine that the current core has write permission; when the result of the bitwise AND operation is 0, determine that its write permission verification result is verification failed, that is, determine that the current core does not have write permission.

[0059] As an example, when the current core is the receive core, it is necessary to perform a bitwise AND operation on the current core mask with the receive core mask in the data encoding information, and determine the read permission verification result according to the result of the bitwise AND operation. For example, the bitwise AND operation can be performed using DATA_R_ACCESS_CHECK(dataId) ((1u<<CORE_ID)&DATA_ID_RECEIVER(dataId)), where 1u<<CORE_ID) is the current core mask and DATA_ID_RECEIVER(dataId) is the receive core mask. Use the function DATA_R_ACCESS_CHECK(dataId) to perform a bitwise AND operation on the two masks. When the result of the bitwise AND operation is 1, determine that its read permission verification result is verification passed, that is, determine that the current core has read permission; when the result of the bitwise AND operation is 0, determine that its read permission verification result is verification failed, that is, determine that the current core does not have read permission.

[0060] In one embodiment, as Figure 5 shown, before step S101, before obtaining the data encoding information corresponding to the target data, the inter-core communication method further includes: S501: Use a linker script to create two inter-core memories for the current core and the target core, and determine the permissions of the current core and the target core for each inter-core memory; S502: Bind the inter-core communication variable corresponding to the inter-core communication queue to the inter-core memory corresponding to the inter-core communication variable.

[0061] The linker script is a core file in system development that controls the memory layout of the compiled program. Essentially, it tells the linker how to merge the compiled object files into the final executable file, and indicates the storage location and attributes of code, data, variables, etc., in physical memory. As an example, in step S501, before the current core communicates with the target core, two inter-core memories are created for the current core and the target core through a linker script. These are called the first inter-core memory and the second inter-core memory. The first inter-core memory is the inter-core memory where the current core has write permissions and the target core has read permissions; while the second inter-core memory is the inter-core memory where the current core has read permissions and the target core has write permissions.

[0062] The linker script's code is shown below: In the code above, `group` defines a memory group. `ordered` indicates that the partitions within the group are arranged in code order, specifically including partitions Partition01, Partition10, Partition02, and Partition20. `attributes` specifies the partition permissions: `rw` means read-write, i.e., the sending core has only write permissions, while the receiving core has only read permissions; `rws` means read-write sharing, i.e., both write and read permissions are available. `run_addr=mem:mpe:dlmu1_1` refers to the running address of the memory group; that is, when the program runs, the data in the memory between cores is actually stored at the physical memory address `dlmu1_1`. `not_cached` indicates that the CPU cache for this partition is disabled to ensure that multiple cores access the latest value of the memory group corresponding to the physical memory address, avoiding cache inconsistency. `select "*Partition01.32bit"` is the matching rule, indicating that all symbols named `Partition01.32bit` should be included in this memory group.

[0063] As an example, in step S502, the inter-core communication variables between the current core and the target core are bound to the inter-core memory corresponding to the inter-core communication variables. Specifically, through the macro definition code in MemMap.h, the inter-core communication variables involved in the communication between the current core and the target core are wrapped with the inter-core communication variables and the corresponding inter-core memory by pair macros: START_SEC_XXX for the start partition and STOP_SEC_XXX for the end partition. This allows developers to bind the inter-core communication variables to their corresponding inter-core memory without having to directly link the script.

[0064] For example, the following shows a portion of the code that binds inter-core communication variables to specified inter-core memory: For example, in a multi-core controller for an aircraft, a typical architecture is designed with a Safety Core and a Slave Core. The Safety Core is responsible for executing critical safety functions and needs to ensure real-time performance and reliability. The Slave Core is responsible for auxiliary functions, such as communication and data processing. In traditional multi-core controllers, the Safety Core not only needs to execute critical safety functions but also other operations unrelated to safety functions, including but not limited to debugging and printing operations. These operations consume the CPU resources of the Safety Core, leading to excessive load on the Safety Core, affecting the real-time performance of safety functions, significantly reducing the performance of the Safety Core, and even potentially causing critical tasks to time out.

[0065] To overcome the above problems, it is necessary to use a linker script to create multiple inter-core memories for the multi-core controller. For example, determine the security core and each slave core to create two inter-core memories, and determine the permissions of the security core and the slave core for each inter-core memory. Then, bind the inter-core communication variables corresponding to the inter-core communication queue to the inter-core memories corresponding to the inter-core communication variables.

[0066] like Figure 6As shown, Core0 is the security core, while Core4 is the slave core. Two inter-core memory locations, W0R4 and W4R0, are created for these two control cores, Core0 and Core4. W0R4 refers to the inter-core memory where Core0 has write access and Core4 has read access, with an address range of 9001 0000H-9001 7FFFH. W4R0 refers to the inter-core memory where Core4 has write access and Core0 has read access, with an address range of 9001 8000H-9001 7FFFH. Inter-core communication variables include, but are not limited to, data buffer, physical tail pointer, physical head pointer, shadow tail pointer, and shadow head pointer. When configuring a transmission channel between Core0 and Core4 for transmitting debug print data, Core0 is the sending core with write permissions, while Core4 is the receiving core with read permissions. During configuration, the data buffer needs to be placed in W0R4 (Core0 writes, Core4 reads) where Core0 has write permissions, so that debug print data can be written to the data buffer later. The physical tail pointer Tail_0_4 is placed in the W0R4 partition (Core0 can write, Core4 can read) so that the secure core Core0 can update the physical tail pointer Tail_0_4, i.e., update the cumulative write count. The physical head pointer Head_0_4 is placed in the W4R0 partition (Core4 can write, Core0 can read) so that the slave core Core4 can update the physical head pointer, i.e., update the cumulative read count. Both the shadow tail pointer and shadow head pointer are placed in the local partition of the sending core Core0, i.e., inter-core memory accessible only to the secure core Core0. In this example, debug print data is transferred to the slave core for processing, while the security core only needs to perform simple data sending operations, significantly reducing CPU utilization.

[0067] This method uses a hardware protection mechanism called MPU (Memory Protection Unit, referring to a multiprocessor chip or multimedia coprocessor) to set memory access permissions. Through this MPU hardware protection mechanism, it ensures that each core can only access memory areas according to predefined permissions, preventing illegal access and data conflicts. This offers the following advantages: First, high efficiency: pre-aligned linked files and lock-free communication mechanisms improve data transmission efficiency. Second, security: bidirectional independent read / write areas and MPU access permission control ensure data security. Third, reliability: pre-allocated memory and hardware protection mechanisms improve system reliability. Fourth, practicality: a simple and easy-to-use interface and clear implementation facilitate engineering applications.

[0068] The inter-core communication method provided in this invention can effectively solve the problem of excessive load on some processor cores (such as security cores) in multi-core controllers, improving the overall system performance. It is particularly suitable for low-altitude airborne controller systems with high requirements for real-time performance and reliability, and has the following overall technical effects: (1) It can effectively reduce the load of some processor cores. For example, the security core transmits debug print data to the slave core for processing. The security core only needs to perform simple data transmission operations, which significantly reduces the CPU utilization rate and thus reduces the load of the security core.

[0069] (2) It can effectively improve the efficiency of inter-core communication, specifically: the link file pre-alignment mechanism avoids the overhead of runtime memory allocation; the lock-free communication mechanism reduces the synchronization waiting time; and the hardware-level access control improves the reliability of data transmission.

[0070] (3) It can enhance the security of multi-core controllers, specifically: MPU hardware protection mechanism to prevent unauthorized access; bidirectional independent read / write area design to avoid data conflicts; access permission check to ensure the legality of data operations.

[0071] (4) It can improve the reliability of the system, specifically: pre-allocated memory avoids memory fragmentation and allocation failure; lock-free mechanism reduces the risk of deadlock; MPU hardware protection mechanism improves system robustness.

[0072] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0073] This invention provides an inter-core communication device, which corresponds one-to-one with the inter-core communication methods described in the above embodiments. For example... Figure 7 As shown, the inter-nuclear communication device includes: The encoding acquisition module 701 is used to acquire the data encoding information corresponding to the target data. The data encoding information includes the sending kernel mask and the receiving kernel mask. The validity verification module 702 is used to verify the validity of the data encoding information and determine the validity verification result. The permission verification module 703 is used to perform permission verification based on the sent or received kernel mask when the validity verification result is successful, and to determine the permission verification result. The inter-core transmission module 704 is used to transmit target data through the inter-core communication queue in the target inter-core memory when the permission verification result is successful; the target inter-core memory is the inter-core memory related to the current core's permission to the target data in the two inter-core memories formed between the current core and the target core.

[0074] Specific limitations regarding the inter-core communication device can be found in the limitations of the inter-core communication method above, and will not be repeated here. Each module in the aforementioned inter-core communication device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor core in hardware form or independently of the processor core, or stored in the processor core's memory in software form, so that the processor can call and execute the operations corresponding to each module.

[0075] This invention provides a multi-core controller, including multiple processor cores as described above; each processor core includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the inter-core communication method described above, for example... Figure 1 S101-S104 are shown below. To avoid repetition, they will not be described again here.

[0076] This invention provides a computer-readable storage medium storing a computer program. When executed by a processor, the computer program implements the inter-core communication method described in the above embodiments, for example... Figure 1 S101-S104 are shown below. To avoid repetition, they will not be described again here.

[0077] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A method for inter-core communication, characterized in that, include: Obtain the data encoding information corresponding to the target data, wherein the data encoding information includes a transmit kernel mask and a receive kernel mask; The data encoding information is validated to determine the validity result. When the validity verification result is successful, permission verification is performed based on the sending kernel mask or the receiving kernel mask to determine the permission verification result. When the permission verification result is successful, the target data is transmitted through the inter-core communication queue in the target core memory. The target inter-core memory refers to the inter-core memory between the current core and the target core that is related to the current core's permissions on the target data.

2. The inter-nuclear communication method according to claim 1, characterized in that, The current core is the sending core, and the sending core calls the data sending interface to perform the following steps: The data encoding information is validated to determine the validity result. When the validity check result is passed, write permission check is performed on the sending kernel mask based on the current kernel mask to determine the write permission check result; When the write permission verification result is successful, the target data is written to the inter-core communication queue of the first inter-core memory so that the target core can read the target data in the first inter-core memory; Wherein, the first inter-core memory is inter-core memory where the current core has write permissions and the target core has read permissions.

3. The inter-nuclear communication method according to claim 2, characterized in that, The step of writing the target data into the inter-core communication queue of the first inter-core memory includes: The shadow head pointer of the sending core is synchronized with the physical head pointer of the inter-core communication queue, and the physical head pointer is used to represent the cumulative number of reads of the receiving core; The current state of the inter-core communication queue is determined based on the shadow head pointer and shadow tail pointer of the sending core. If the current state of the inter-core communication queue is not full, the target data is written into the data buffer of the first inter-core memory. After the target data is written, the shadow tail pointer is updated and synchronized with the physical tail pointer of the inter-core communication queue. The physical tail pointer is used to represent the cumulative number of writes to the sending core.

4. The inter-nuclear communication method according to claim 1, characterized in that, The current core is the receiving core, and the receiving core calls the data receiving interface to perform the following steps: The data encoding information is validated to determine the validity result. When the validity verification result is successful, read permission verification is performed on the received kernel mask based on the current kernel mask to determine the read permission verification result. When the read permission verification result is successful, the target data pre-written by the target core is read from the inter-core communication queue of the second inter-core memory; The second inter-core memory is the inter-core memory where the current core has read permissions and the target core has write permissions.

5. The inter-nuclear communication method according to claim 4, characterized in that, The step of reading the target data pre-written by the target core from the inter-core communication queue of the second inter-core memory includes: The current state of the inter-core communication queue is determined based on the physical head pointer and physical tail pointer of the inter-core communication queue. If the current state of the inter-core communication queue is not empty, then the target data pre-written by the target core is read from the data buffer corresponding to the second inter-core memory. After the target data is read, the physical head pointer of the inter-core communication queue is updated. The physical head pointer is used to represent the cumulative number of reads by the receiving core.

6. The inter-nuclear communication method according to claim 1, characterized in that, The step of performing permission verification based on the sending kernel mask or the receiving kernel mask, and determining the permission verification result, includes: Based on the current kernel mask, perform a bitwise AND operation on either the transmitted kernel mask or the received kernel mask, and determine the bitwise AND operation result; When the result of the bitwise AND operation is 1, the permission verification result is determined to be successful. When the result of the bitwise AND operation is 0, the permission verification result is determined to be verification failure.

7. The inter-nuclear communication method according to claim 1, characterized in that, Before acquiring the data encoding information corresponding to the target data, the inter-core communication method further includes: A linker script is used to create two inter-core memory locations for the current core and the target core, and the permissions of the current core and the target core for each inter-core memory location are determined. Bind the inter-core communication variable corresponding to the inter-core communication queue to the inter-core memory corresponding to the inter-core communication variable.

8. An inter-nuclear communication device, characterized in that, include: The encoding acquisition module is used to acquire the data encoding information corresponding to the target data, the data encoding information including the sending kernel mask and the receiving kernel mask; The validity verification module is used to verify the validity of the data encoding information and determine the validity verification result. The permission verification module is used to perform permission verification based on the sending kernel mask or the receiving kernel mask when the validity verification result is that the verification is passed, and to determine the permission verification result. The inter-core transmission module is used to transmit the target data through the inter-core communication queue in the target core memory when the permission verification result is successful. The target inter-core memory refers to the inter-core memory between the current core and the target core that is related to the current core's permissions on the target data.

9. A multi-core controller comprising a plurality of processor cores, each processor core comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the inter-core communication method according to any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the inter-core communication method according to any one of claims 1 to 7.

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