Address remapping apparatus, method and processor

Abstract

The application discloses an address remapping device, method and processor, and the device comprises: a first calculation module which takes the complement of the low L bits of an original logical address to obtain a complement result; a second calculation module which dynamically obtains an offset correction value which keeps the order of an output channel group according to the original logical address; a third calculation module which determines the base address offset across the input channel group; a fourth calculation module which performs summation and one addition operation on the complement result and the offset correction value, and extracts the low L bits to obtain a local logical address; and finally, an address composition module which adds the local logical address and the base address offset to generate a target logical address corresponding to the original logical address. In the memory access path, the application can efficiently realize the 180° rotation of the convolution kernel at the hardware level through additional processing of the address, so as to fundamentally eliminate the efficiency loss caused by the software rotation.

Description

Technical Field

[0001] This invention relates to the field of artificial intelligence chip technology, and in particular to an address remapping device, method and processor. Background Technology

[0002] In the training process of a convolutional neural network, the backpropagation stage is a crucial step for iterative optimization of model parameters. This stage requires rotating the convolutional kernel by 180° to meet the mathematical requirements of gradient calculation.

[0003] To achieve a 180° rotation of the convolutional kernel, existing technologies employ a software-level data rearrangement scheme. Specifically, a software algorithm reads the convolutional kernel tensor stored in memory, rearranges each weight data according to the rotation rules, generates a new tensor after a 180° rotation, and then writes it back into memory for subsequent computation. Clearly, existing technologies involve a large number of data reads, position transformations, and write-back operations, resulting in significant time overhead; especially in scenarios with large convolutional kernel sizes and a high number of channels, the time overhead increases exponentially, drastically reducing the execution efficiency of the backpropagation phase. Summary of the Invention

[0004] The purpose of this invention is to provide an address remapping device, method, and processor that performs additional processing on addresses in the memory access path, enabling the convolution kernel to efficiently achieve 180° rotation under the same input and output channels without additional physical movement or data copying, thereby fundamentally eliminating the efficiency loss caused by software rotation.

[0005] A first aspect of the present invention provides an address remapping device, wherein the convolution kernel tensor is partitioned into N... ichg ×N w ×N ochg There are N blocks; where N is a subset of N blocks. ichg N represents the number of input channel groups. w N represents the total number of weight positions for a single convolutional kernel. ochg The number of output channel groups; each block is configured with an independent storage area and a corresponding raw logical address; the device includes: The first calculation module is used to invert the lower L bits of the input current original logical address to obtain an L-bit inverted result; where L is a set of bits that satisfy 2... L ≥N buf_ichg The smallest positive integer N; buf_ichg The total number of storage areas required to store all weight data within a single input channel group; The second calculation module is used to obtain the offset correction value of the corresponding output channel group based on the current original logical address, so as to ensure that N associated with the same weight position ochgThe order of the output channel groups remains unchanged; wherein, the offset correction value is in N... w ×N ochg -N ochg The initial value is 2, the tolerance is 2, and the length is N. ochg A specified value in the first sequence; The third calculation module is used to determine the base address offset of the corresponding input channel group relative to the first input channel group based on the current original logical address. The fourth calculation module is used to perform a summation operation and a one-by-one operation on the inverted result and the offset correction value, obtain the intermediate result and extract the low L bits to obtain the local logical address; The address synthesis module is used to add the local logical address to the base address offset to obtain the target logical address corresponding to the current original logical address.

[0006] Optionally, the original logical address of the block is allocated according to the priority order of the storage of the convolution kernel tensor; wherein the priority order is that the output channel takes precedence over the weight position, and the weight position takes precedence over the input channel.

[0007] Optionally, the second calculation module includes: a first loop counter; The update frequency of the first count value of the first loop counter is synchronized with the update frequency of the current original logical address, and the counting period is N. ochg The first count value is used to track the N values ​​associated with the output channel group corresponding to the current original logical address at the same weight position. ochg The sequential position within each output channel group.

[0008] Optionally, the second calculation module further includes: a correction parameter acquisition unit and a first offset calculation unit; The correction parameter acquisition unit is used to determine the correction parameter based on the first count value; wherein the correction parameter is in the form of -N ochg The initial value is 2, the tolerance is 2, and the length is N. ochg A specified value in the second sequence; The first offset calculation unit is used to calculate the offset correction value based on the correction parameters and the total number of storage areas.

[0009] Optionally, the third calculation module includes: a second loop counter and an index counting unit for the input channel group; The update frequency of the second count value of the second loop counter is synchronized with the update frequency of the current original logical address, and the counting period is N. buf_ichg ; The index counting unit is used to increment the index count value by one when the second loop counter overflows and returns to zero, so as to record the index of the input channel group corresponding to the current original logical address.

[0010] Optionally, the third calculation module further includes: a second offset calculation unit; The second offset calculation unit is used to calculate the base address offset based on the index count value and the total number of storage areas.

[0011] Optionally, the current original logical address is derived from the address information sent by the computing unit when performing a write or read operation.

[0012] Optionally, the intermediate result calculation process supports carry expansion.

[0013] A second aspect of the present invention provides an address remapping method, wherein the convolution kernel tensor is partitioned into N... ichg ×N w ×N ochg There are N blocks; where N is a subset of N blocks. ichg N represents the number of input channel groups. w N represents the total number of weight positions for a single convolutional kernel. ochg The number of output channel groups; each block is configured with an independent storage area and a corresponding original logical address; the method is applicable to the address remapping apparatus described in any embodiment of the first aspect, including: The first calculation module inverts the lower L bits of the input current original logical address to obtain the inverted L bits; where L is a set of bits that satisfy 2... L ≥N buf_ichg The smallest integer N; buf_ichg The total number of storage areas required to store all weight data within a single input channel group; The second calculation module obtains the offset correction value of the corresponding output channel group based on the current original logical address to ensure that N associated with the same weight position are correct. ochg The order of the output channel groups remains unchanged; wherein, the offset correction value is in N... w ×N ochg -N ochg The initial value is 2, the tolerance is 2, and the length is N. ochg A specified value in the first sequence; The third calculation module determines the base address offset of the corresponding input channel group relative to the first input channel group based on the current original logical address. The fourth calculation module performs a summation operation and a one-increment operation on the inverted result and the offset correction value to obtain an intermediate result and extract the low L bits to obtain the local logical address. The local logical address is added to the base address offset by the address synthesis module to obtain the target logical address corresponding to the current original logical address.

[0014] Optionally, the second calculation module includes: a first loop counter; The step of obtaining the offset correction value of the corresponding output channel group based on the current original logical address through the second calculation module includes: The update frequency of the first count value of the first loop counter is synchronized with the update frequency of the current original logical address, and the counting period is N. ochg The first count value is used to track the N values ​​associated with the output channel group corresponding to the current original logical address at the same weight position. ochg The sequential position within each output channel group.

[0015] Optionally, the second calculation module further includes: a correction parameter acquisition unit and a first offset calculation unit; The step of obtaining the offset correction value of the corresponding output channel group based on the current original logical address through the second calculation module also includes: The correction parameter acquisition unit is used to determine the correction parameter based on the first count value; wherein the correction parameter is in the form of -N ochg The initial value is 2, the tolerance is 2, and the length is N. ochg A specified value in the second sequence; The first offset calculation unit is used to calculate the offset correction value based on the correction parameters and the total number of storage areas.

[0016] A third aspect of the present invention provides a processor including the address remapping apparatus described in any of the first aspects.

[0017] Compared with existing technologies, this invention provides an address remapping device, method, and processor. Through real-time address translation in hardware, the access order (read or write order) of the storage area is adjusted, enabling efficient 180° rotation of convolutional kernels of arbitrary size without additional physical movement or copying of data, thus fundamentally eliminating the efficiency loss caused by software rotation. Furthermore, the entire address mapping calculation process involves only simple operations such as inversion, addition, multiplication, and bit truncation, meaning the hardware implementation is simple, belonging to lightweight hardware circuitry with low area overhead. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of an embodiment of the convolution kernel tensor provided by the present invention; Figure 2 This is a schematic diagram of an embodiment of the convolution kernel rotation provided by the present invention; Figure 3This is a schematic diagram of an embodiment of the address remapping device provided by the present invention; Figure 4 This is a flowchart illustrating an embodiment of the address remapping method provided by the present invention; Figure 5 This is an example diagram showing the connection relationship of the address remapping device provided by the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] To better understand the technical solutions in the embodiments of the present invention, the storage method of the convolution kernel tensor in memory space in the present invention will be explained in detail below: The kernel tensor is a four-dimensional tensor with the shape [output channel (och), input channel (ich), kernel height (Kh), kernel width (Kw)]. For example... Figure 1 The diagram shown is a schematic of an embodiment of the convolutional kernel tensor provided by the present invention. Its specific parameters are: 64 output channels, 32 input channels, and a convolutional kernel size of 2×2 (i.e., including four weight positions w0, w1, w2, and w3).

[0021] The convolutional kernel tensor is organized and stored in a specific memory space, where one addressing unit (i.e., one "logical address") corresponds to a 4KB storage buffer. If the weight data is stored in half-precision floating-point (FP16) format, one buffer can exactly hold a data block associated with a specified weight location, 8 input channels, and 32 output channels, i.e., 8ich × 32och × 16bit = 4KB. To accommodate the storage capacity of the buffer, this embodiment of the invention divides the convolutional kernel tensor into N parts based on three dimensions: output channel group, weight location, and input channel group. ichg ×N w ×N ochg The input channels are managed in blocks, meaning they are grouped into sets of eight, divided into (N) blocks. ichg =Number of input channels / 8) Number of input channel groups; N w The total number of weight positions (N) of a single convolutional kernel w =Kh×Kw); the output channels are grouped into groups of 32, divided into (N ochg=Number of output channels / 32) Output channel groups. In addition, each block corresponds to an independent buffer in the memory space.

[0022] It is worth noting that this invention does not limit the storage capacity of the buffer or the size of the blocks, which are determined when applied to a specific product or technology according to the embodiments of this invention. For example, when the weight data is in single-precision floating-point (FP32) format, the input channels will be divided into groups of four.

[0023] Figure 1 The convolutional kernel tensor is divided into 4×4×2=32 blocks. The arrangement of these blocks in each buffer (before the 180° rotation operation) follows the priority order of "och->w->ich", as shown in Table 1.

[0024] Table 1. Weights of convolutional kernel tensors in each storage area Table 1 shows only the memory layout of all weight data corresponding to the two input channel groups (ich0~7 and ich8~15). "Original id" is the original logical address, which is the position index (i.e., the buffer position index) assigned to the block before the convolution kernel undergoes a 180° rotation; "new_id" is the target logical address. In this embodiment of the invention, by changing the operation of "accessing the buffer corresponding to the original logical address" to "accessing the buffer corresponding to the target logical address" in the memory access path, a 180° rotation of the convolution kernel can be implemented at the hardware level.

[0025] Following the priority order of "och->w->ich", the innermost priority (fastest changing) is the output channel group. For fixed input channel groups and weight positions, all consecutive output channel groups are stored first. For example, for w0 and input channel groups (ich0~7), since the total number of output channels is 64, they need to be divided into two groups (och0~31 and och32~63) for storage, thus occupying two consecutive buffers (as shown in Table 1, with original id=0 and 1). The middle priority is the weight position. After storing all output channel groups for one weight position, the next weight position is stored. Therefore, the weight data for ich0~7 corresponding to w1 is located after w0, occupying original id=2 and 3. The outermost priority (slowest changing) is the input channel group. After storing all output channel group data for all weight positions within one input channel group (such as ich0~7), the next input channel group (such as ich8~15) is stored. Therefore, the starting address of the weight data for w0 within the ich8~15 group is the original id=8.

[0026] like Figure 2The diagram shown is a schematic of an embodiment of the convolution kernel rotation provided by this invention. Related technologies use software algorithms to rotate each convolution kernel in the convolution kernel tensor by 180°, such as "w0->w1->w2->w3" which becomes "w3->w2->w1->w0" after a 180° rotation. The inventors discovered that for a 180° rotation of the convolution kernel tensor, only the order of the convolution kernels within each channel (i.e., the input and output channels) needs to be reversed individually, without changing the sorting order of the channel dimensions. Further research revealed that since each buffer is stored with a complete weight position, a set of input channels, and a set of output channels as its granularity, the 180° rotation operation of the convolution kernel does not require modifying the weight data within each buffer. Address mapping can be performed directly using the buffer as the basic operation object. By adjusting the weight positions prioritized in the middle layer and ensuring that the mapped target logical address meets the following two key conditions, complete convolution kernel rotation can be achieved at the hardware level: (1) The order across the input channel groups remains unchanged, that is, after mapping, N ichg The overall order of the input channel groups remains the same as before the mapping; for example, the block associated with "ich0~7, w0 and och0~31" (original id=0) is mapped to the block associated with "ich0~7, w3 and och0~31" (new_id=6). (2) Within the input channel group, the N associated with each weight position ochg The order of the output channel groups remains unchanged; that is, for any weight position, the relative order of its corresponding multiple output channel groups remains unchanged before and after mapping.

[0027] Therefore, the rotation of each convolution kernel in the entire convolution kernel tensor can be transformed into a set of address mapping rules for deterministic computation of the original logical addresses, and implemented in hardware without any actual data movement or copying.

[0028] See Figure 3 This is a schematic diagram of an embodiment of the address remapping device provided by the present invention.

[0029] A first aspect of the present invention provides an address remapping device, wherein the convolution kernel tensor is partitioned into N... ichg ×N w ×N ochg There are N blocks; where N is a subset of N blocks. ichg N represents the number of input channel groups. w N represents the total number of weight positions for a single convolutional kernel. ochg The number of output channel groups; each block is configured with an independent storage area and a corresponding raw logical address; the device includes: The first calculation module 100 is used to invert the lower L bits of the input current original logical address to obtain an inverted L-bit result; where L is a set of bits that satisfy 2... L ≥N buf_ichg The smallest positive integer N; buf_ichg The total number of storage areas required to store all weight data within a single input channel group; The second calculation module 200 is used to obtain the offset correction value of the corresponding output channel group based on the current original logical address, so as to ensure that N associated with the same weight position ochg The order of the output channel groups remains unchanged; wherein, the offset correction value is in N... w ×N ochg -N ochg The initial value is 2, the tolerance is 2, and the length is N. ochg A specified value in the first sequence; The third calculation module 300 is used to determine the base address offset of the corresponding input channel group relative to the first input channel group based on the current original logical address. The fourth calculation module 400 is used to perform a summation operation and a one-by-one operation on the inverted result and the offset correction value, obtain an intermediate result and extract the lower L bits to obtain the local logical address; The address synthesis module 500 is used to add the local logical address to the base address offset to obtain the target logical address corresponding to the current original logical address.

[0030] It should be noted that each block corresponds to an independent storage area (buffer) and a unique original logical address, which reflects the logical storage location of the block before rotation.

[0031] The purpose of the first calculation module 100 performing a bitwise inversion operation on the lower L bits of the original logical address is to reverse the "weight position order" within the input channel group. As shown in Table 2, the inversion result Part1 of the L bits decreases from 7 to 0 as the original id increases, which corresponds exactly to the order after the weight positions are reversed (when N... ochg When N is 2, the inverted "w0->w3" of the 2×2 convolution kernel becomes "w3->w0". Similarly, the inversion result Part1 in Table 3 decreases from 15 to 4, corresponding to when N ochg When the value is 3, "w0->w3" becomes "w3->w0" after reversal.

[0032] The offset correction value Part2 in the second calculation module 200 is used to ensure that, during the address mapping process, N associated with the same weight position are consistent. ochg The relative order of the output channel groups remains unchanged. Part 2 is of length N. ochg A specified value in the first sequence, which is Nw ×N ochg -N ochg Starting with a common difference of 2, the values ​​in the first sequence are (N... w ×N ochg -N ochg ):2:(N w ×N ochg +N ochg -2). The second calculation module 200 can deduce the relative position of the corresponding output channel group based on the original logical address, and then select the corresponding specified value from the sequence as the offset correction value, or directly calculate the current required offset correction value to ensure that the relative order of the output channel group is not disrupted.

[0033] The base address offset Part3 in the third calculation module 300 is used for global address adjustment during cross-group mapping to ensure that the storage areas of different input channel groups do not overlap. Part3 = Index of the input channel group corresponding to the original logical address × N buf_ichg ; where N buf_ichg =N w ×N ochg Obviously, Part 3 and N buf_ichg They are in a multiple relationship.

[0034] In the fourth calculation module 400, the intermediate result = Part1 + 1 + Part2; then, the lower L bits of this intermediate result are extracted to obtain the local logical address tmp. The fourth calculation module 400 combines the local inverted offset with the fine correction related to the output channel, and by extracting the lower L bits, constrains the local logical address tmp within the logical address space (0~N) of the first input channel group. buf_ichg -1), so that the local logical address tmp corresponds to the buffer index after the weight position within the first input channel group is rotated.

[0035] The address synthesis module 500 adds the local logical address tmp obtained by the fourth calculation module 400 to the base address offset Part3 obtained by the third calculation module 300, and finally generates the target logical address new_id corresponding to the current original logical address, that is, new_id = tmp + Part3.

[0036] Table 2. N ochg A record table of the calculation results of each module and the final mapping result when the value is 2. Table 3. N ochg A record table of the calculation results of each module and the final mapping result when the value is 3. Tables 2 and 3 show the results for different numbers of output channel groups (N) ochg Under the configuration, the mapping process from "original logical address" (original id) to "target logical address" (new_id) is as follows.

[0037] Table 2 sets the number of output channel groups N ochg =2, and its offset correction value (Part2) cycles through the sequence {6, 8}, which conforms to the generation rule of the first sequence (initial value = N). w ×N ochg -N ochg Tolerance = 2, Length = N ochg ); when N w When the kernel size is 4 (2×2 convolution kernel), the first sequence is {4×2-2=6, 4×2-0=8}. Table 3 sets the number of output channel groups N. ochg =3, and its offset correction value (Part2) cycles in the sequence {9, 11, 13}. Different output channel groups at the same weight position correspond to different correction values.

[0038] As shown in Tables 2 and 3, within the same input channel group, the weight position corresponding to the original id and the weight position corresponding to the new_id are rotated by 180°; simultaneously, the N associated with the same weight position... ochg The order of each output channel group remains unchanged (e.g., in Table 2, "w0's original id is 0 and 1" -> "new_id is 6 and 7", the order of the output channel groups is not disrupted, and it is still "och0~31" to "och32~63"); in addition, the addresses of different input channel groups do not overlap and the order remains unchanged (e.g., in Table 2, the new_id=8~15 of ich8~15 is only superimposed with the base address offset 8 on the new_id=0~7 of ich0~7).

[0039] Therefore, this embodiment of the invention, through real-time address translation in hardware, adjusts the access order (read order or write order) of the storage area, enabling efficient 180° rotation of convolution kernels of arbitrary size without additional physical movement or copying of data, thus fundamentally eliminating the efficiency loss caused by software rotation. Furthermore, the entire address mapping calculation process involves only simple operations such as inversion, addition, multiplication, and bit truncation, meaning the hardware implementation is simple, belonging to lightweight hardware circuitry with low area overhead.

[0040] In an optional embodiment, the intermediate result calculation process supports carry expansion.

[0041] It should be noted that in the fourth calculation module 400, the operation of "intermediate result tmp = inverted result Part1 + 1 + offset correction value Part2" is not simply a modulo 2 operation within the L-bit range. LInstead of performing addition, the operation is treated as being performed on a wider bit width (at least L+1 bits). Therefore, the result of (Part1+1+Part2) is an intermediate result tmp with an expanded bit width. The bit width of tmp can be automatically expanded with the carry, without being limited by the original bit width (L bits) of the inverted result.

[0042] In an optional embodiment, the original logical address of the block is allocated according to the priority order of the convolution kernel tensor storage; wherein the priority order is that the output channel takes precedence over the weight position, and the weight position takes precedence over the input channel.

[0043] It should be noted that the original logical addresses are allocated before the convolution kernel is rotated 180° (i.e., before address mapping), and follow the priority order of "och->w->ich", specifically as follows: multiple blocks belonging to the same input channel group and the same weight position but different output channel groups have their corresponding original logical addresses allocated consecutively; after all output channel data of the same input channel group and the same weight position are allocated, the system switches to the next weight position of the same input channel group; after all data allocation for the current input channel group is completed, the system moves on to the allocation of the next input channel group. Therefore, data from different input channel groups form continuous and independent address segments in memory.

[0044] In an optional embodiment, the current original logical address is derived from the address information sent by the computing unit when performing a write or read operation.

[0045] It should be noted that in read operation mode, the computing unit initiates read requests according to its original access order (i.e., a logical view composed of the original logical address sequence). The address remapping device provided by this invention maps each original logical address to its corresponding target logical address in real time, thereby reorganizing the physical order in which the computing unit actually reads weight data from memory. Finally, the computing unit obtains the weight data after a 180° rotation. This conversion process involves no actual data movement or recalculation.

[0046] In write operation mode, the computation unit first completes the binding of "block -> pre-allocated storage area -> original logical address". Then, the address remapping device intervenes in the write link, converting the original logical address specified by the write operation (corresponding to the pre-allocated storage location before rotation) into the target logical address (corresponding to the desired storage location after rotation) in real time through the collaborative operation of its internal modules. This guides the computation unit to directly write the block data to the physical storage location pointed to by the target logical address. Through this process, the rotation result of the convolution kernel is permanently fixed in the specific layout of the memory. Subsequently, when the computation unit reads the convolution kernel again, it can directly obtain the weight data after 180° rotation without activating the address remapping device.

[0047] In an optional embodiment, the second calculation module 200 includes: a first loop counter; The update frequency of the first count value of the first loop counter is synchronized with the update frequency of the current original logical address, and the counting period is N. ochg The first count value is used to track the N values ​​associated with the output channel group corresponding to the current original logical address at the same weight position. ochg The sequential position within each output channel group.

[0048] Furthermore, the second calculation module 200 also includes: a correction parameter acquisition unit and a first offset calculation unit; The correction parameter acquisition unit is used to determine the correction parameter based on the first count value; wherein the correction parameter is in the form of -N ochg The initial value is 2, the tolerance is 2, and the length is N. ochg A specified value in the second sequence; The first offset calculation unit is used to calculate the offset correction value based on the correction parameters and the total number of storage areas.

[0049] It should be noted that the second calculation module 200, through the coordinated operation of the first loop counter, the correction parameter acquisition unit, and the first offset calculation unit, accurately generates offset correction values ​​adapted to different output channel groups, offsetting the interference of the first calculation module 100's "bit-by-bit inversion" operation on the output channel group order, thereby ensuring that N values ​​associated with the same weight position are... ochg The order of each output channel group remains unchanged after address remapping.

[0050] The update frequency of the first count value is strictly synchronized with the update frequency of the current original logical address input to the device. Whenever the address remapping device receives a new original logical address for translation, the first count value is updated accordingly.

[0051] The counting period of the first cycle counter is set to N. ochg (i.e., the total number of output channel groups), its first count value is between 0 and (N). ochg It cycles within the range of -1). For example, when N ochg When N=3, the first loop counter cycles through 0, 1, 2, 0, 1, 2, ... . This periodicity accurately reflects the time it takes to process N at a weight position. ochgAfter one output channel group, the next original logical address will belong to the new weight position, and the first loop counter will start counting again from 0 to track the first output channel group under the new weight position. Through the first loop counter, the hardware can know the sequential position (index) of the output channel group corresponding to the current address within its weight position in real time with low overhead, without parsing all the information of the original logical address.

[0052] The correction parameter Och_cnt is derived from a pre-generated parameter of length N. ochg The arithmetic sequence is the second sequence. The second sequence begins with -N. ochg The first term is 2, with a common difference of 2. When N... ochg When N=2, the second sequence is [-2, 0]; when N=2, the second sequence is [-2, 0]. ochg When the first count value is 3, the second sequence is [-3, -1, 1]. The correction parameter acquisition unit uses the first count value of the first loop counter as an index to directly select the corresponding value from the second sequence as the current correction parameter Och_cnt. For example, when the first count value is 0, the first item of the second sequence (-N) is selected. ochg When the first count value is 1, select the second item of the second sequence (-N). ochg +2), and so on; or the correction parameter acquisition unit uses a very simple combinational logic (such as Och_cnt=-N). ochg This can be achieved by adding 2 × the first count value, resulting in minimal hardware overhead.

[0053] The offset correction value Part2 is obtained through an addition operation: Part2 = N buf_ichg +Och_cnt; where N buf_ichg The total number of storage areas required to store all weight data within a single input channel group, i.e., N buf_ichg =N w ×N ochg .

[0054] It is worth noting that, in embodiments of the present invention, the correction parameter acquisition unit and the first offset calculation unit may not be used. Instead, the offset correction value may be directly selected from the first sequence based on the first count value; or it may be directly selected based on another logical combination (i.e., Part2=N). buf_ichg -N ochg The offset correction value is obtained by adding 2 × the first count value.

[0055] In an optional embodiment, the third computing module 300 includes: a second loop counter and an index counting unit for the input channel group; The update frequency of the second count value of the second loop counter is synchronized with the update frequency of the current original logical address, and the counting period is N. buf_ichg ; The index counting unit is used to increment the index count value by one when the second loop counter overflows and returns to zero, so as to record the index of the input channel group corresponding to the current original logical address.

[0056] Furthermore, the third calculation module 300 also includes: a second offset calculation unit; The second offset calculation unit is used to calculate the base address offset based on the index count value and the total number of storage areas.

[0057] It should be noted that the third calculation module 300, through the collaborative work of the second loop counter, the index counting unit of the input channel group and the second offset calculation unit, accurately determines the base address offset of the input channel group corresponding to the current original logical address, ensuring that the address ranges of different input channel groups do not overlap, and providing a position reference at the input channel level for the accurate synthesis of the final target logical address.

[0058] The update frequency of the second count value of the second loop counter is strictly synchronized with the update frequency of the current original logical address input to the device; that is, the second count value is incremented once for each new original logical address processed.

[0059] The counting period of the second cycle counter is set to N. buf_ichg (i.e., the total number of storage areas required to store all weight data within a single input channel group), its second count value is between 0 and (N). buf_ichg The second count increments from 0 to (N) and cycles within the range of -1). buf_ichg When the count reaches -1, it indicates that the third calculation module 300 is sequentially processing all data blocks within the same input channel group. Once the second count value reaches its maximum value and returns to 0 (i.e., "overflow and return to zero"), it means that "the processing of the current original logical address has moved on to the next input channel group".

[0060] The input channel group index counting unit is used to record the index of the input channel group to which the currently processed original logical address belongs. This index counting unit counts the overflow event of the second loop counter (i.e., from N...). buf_ichg The transition from -1 to 0 serves as the trigger condition, incrementing the internally maintained index count value (Ich_cnt) by one. Clearly, this occurs within a complete counting cycle of the second loop counter (from 0 to N). buf_ichg Within -1), the index count value output by the index counting unit remains unchanged.

[0061] The base address offset Part3 is obtained through a multiplication operation: Part3 = Ich_cnt × N buf_ichg ; where N buf_ichgThis represents the span that each input channel group "occupies" in the logical address space. Multiplying the index (numbered starting from 0) of the current input channel group by this span gives the starting offset address of the input channel group's data in the logical address space. For example, the offset of the first input channel group (numbered 0) is 0, and the offset of the second input channel group (numbered 1) is 1×N. buf_ichg The offset of the third input channel group (numbered 2) is 2×N. buf_ichg And so on.

[0062] See Figure 4 This is a flowchart illustrating an embodiment of the address remapping method provided by the present invention.

[0063] A second aspect of the present invention provides an address remapping method, wherein the convolution kernel tensor is partitioned into N... ichg ×N w ×N ochg There are N blocks; where N is a subset of N blocks. ichg N represents the number of input channel groups. w N represents the total number of weight positions for a single convolutional kernel. ochg The number of output channel groups is specified; each block is configured with an independent storage area and a corresponding original logical address; the method is applicable to the address remapping apparatus described in any embodiment of the first aspect above, including steps S1 to S5, as follows: Step S1: The first calculation module 100 inverts the lower L bits of the input current original logical address to obtain the inverted L bits; where L is a set of bits that satisfy 2... L ≥N buf_ichg The smallest integer N; buf_ichg The total number of storage areas required to store all weight data within a single input channel group; Step S2: The second calculation module 200 obtains the offset correction value of the corresponding output channel group based on the current original logical address to ensure that N associated with the same weight position ochg The order of the output channel groups remains unchanged; wherein, the offset correction value is in N... w ×N ochg -N ochg The initial value is 2, the tolerance is 2, and the length is N. ochg A specified value in the first sequence; Step S3: The third calculation module 300 determines the base address offset of the corresponding input channel group relative to the first input channel group based on the current original logical address; Step S4: The fourth calculation module 400 performs a summation operation and a one-increment operation on the inverted result and the offset correction value to obtain an intermediate result and extract the low L bits to obtain the local logical address; Step S5: The local logical address is added to the base address offset by the address synthesis module 500 to obtain the target logical address corresponding to the current original logical address.

[0064] Optionally, the second calculation module 200 includes: a first loop counter; The step of obtaining the offset correction value of the corresponding output channel group by the second calculation module 200 based on the current original logical address includes: The update frequency of the first count value of the first loop counter is synchronized with the update frequency of the current original logical address, and the counting period is N. ochg The first count value is used to track the N values ​​associated with the output channel group corresponding to the current original logical address at the same weight position. ochg The sequential position within each output channel group.

[0065] Optionally, the second calculation module 200 further includes: a correction parameter acquisition unit and a first offset calculation unit; The step of obtaining the offset correction value of the corresponding output channel group based on the current original logical address through the second calculation module also includes: The correction parameter acquisition unit is used to determine the correction parameter based on the first count value; wherein the correction parameter is in the form of -N ochg The initial value is 2, the tolerance is 2, and the length is N. ochg A specified value in the second sequence; The first offset calculation unit is used to calculate the offset correction value based on the correction parameters and the total number of storage areas.

[0066] It should be noted that the address remapping method provided in this embodiment of the invention can implement all the processing flows of the address remapping device described in any of the embodiments of the first aspect above. The specific implementation schemes and technical effects of the address remapping method correspond to the same specific implementation schemes and technical effects of the address remapping device described in any of the embodiments of the first aspect above, and will not be repeated here.

[0067] A third aspect of the present invention provides a processor including the address remapping apparatus described in any of the first aspects of the present invention.

[0068] The processor can be any of the following: CPU (Central Processing Unit), GPU (Graphics Processing Unit), TPU (Tensor Processing Unit), NPU (Neural Network Processing Unit), DPU (Deep Learning Processing Unit), APU (Accelerated Processing Unit), and GPGPU (General-Purpose computing on Graphics Processing Unit). The address remapping device is a dedicated hardware module within the processor used to generate the target logical address corresponding to the original logical address, thereby obtaining the weight data after a 180° spatial rotation of the convolution kernel, and for use by the processor's computing units (CUs).

[0069] like Figure 5 The diagram illustrates an example of the connection relationship of the address remapping device provided by this invention. The computing unit in the processor is responsible for core tasks such as convolution operations and gradient calculations. It sends the original logical address of the buffer to the address remapping device by initiating read or write requests. Upon receiving the original logical address, the address remapping device, through the coordinated processing of its internal modules, converts the original logical address into the corresponding target logical address and transmits the target logical address to the memory / cache system. The memory / cache system includes multiple buffers, such as buffer0, buffer1, and buffer2. Based on the target logical address, the memory / cache system writes weight data into the buffer corresponding to the target logical address (when the computing unit initiates a write request), or transmits the weight data from the buffer corresponding to the target logical address to the computing unit (when the computing unit initiates a read request). Clearly, the address remapping device does not directly manipulate the weight data in the buffer; instead, it adjusts the "order of accessing the buffer" through address conversion to obtain the weight data after a 180° spatial rotation of the convolution kernel.

[0070] Furthermore, the buffer can be distributed inside the processor, such as on-chip static random access memory (SRAM) or group shared memory (GSM), or it can be distributed outside the processor, such as dynamic random access memory (DRAM) or high-bandwidth memory (HBM), depending on the specific product or technology in which this invention is applied.

[0071] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. An address remapping device, characterized in that, The convolution kernel tensor is divided into N ichg ×N w ×N ochg There are N blocks; where N is a subset of N blocks. ichg N represents the number of input channel groups. w N represents the total number of weight positions for a single convolutional kernel. ochg The number of output channel groups; each block is configured with an independent storage area and a corresponding raw logical address; the device includes: The first calculation module is used to invert the lower L bits of the input current original logical address to obtain an L-bit inverted result; where L is a set of bits that satisfy 2... L ≥N buf_ichg The smallest positive integer N; buf_ichg The total number of storage areas required to store all weight data within a single input channel group; The second calculation module is used to obtain the offset correction value of the corresponding output channel group based on the current original logical address, so as to ensure that N associated with the same weight position ochg The order of the output channel groups remains unchanged; wherein, the offset correction value is in N... w ×N ochg -N ochg The initial value is 2, the tolerance is 2, and the length is N. ochg A specified value in the first sequence; The third calculation module is used to determine the base address offset of the corresponding input channel group relative to the first input channel group based on the current original logical address. The fourth calculation module is used to perform a summation operation and a one-by-one operation on the inverted result and the offset correction value, obtain the intermediate result and extract the low L bits to obtain the local logical address; The address synthesis module is used to add the local logical address to the base address offset to obtain the target logical address corresponding to the current original logical address.

2. The address remapping device as described in claim 1, characterized in that, The original logical addresses of the blocks are allocated according to the priority order of the storage of the convolution kernel tensors; wherein the priority order is that the output channel takes precedence over the weight position, and the weight position takes precedence over the input channel.

3. The address remapping device as described in claim 1, characterized in that, The second calculation module includes: a first loop counter; The update frequency of the first count value of the first loop counter is synchronized with the update frequency of the current original logical address, and the counting period is N. ochg The first count value is used to track the N values ​​associated with the output channel group corresponding to the current original logical address at the same weight position. ochg The sequential position within each output channel group.

4. The address remapping device as described in claim 3, characterized in that, The second calculation module further includes: a correction parameter acquisition unit and a first offset calculation unit; The correction parameter acquisition unit is used to determine the correction parameter based on the first count value; wherein the correction parameter is in the form of -N ochg The initial value is 2, the tolerance is 2, and the length is N. ochg A specified value in the second sequence; The first offset calculation unit is used to calculate the offset correction value based on the correction parameters and the total number of storage areas.

5. The address remapping apparatus as described in claim 1, characterized in that, The third calculation module includes: a second loop counter and an index counting unit for the input channel group; The update frequency of the second count value of the second loop counter is synchronized with the update frequency of the current original logical address, and the counting period is N. buf_ichg ; The index counting unit is used to increment the index count value by one when the second loop counter overflows and returns to zero, so as to record the index of the input channel group corresponding to the current original logical address.

6. The address remapping apparatus as described in claim 5, characterized in that, The third calculation module further includes: a second offset calculation unit; The second offset calculation unit is used to calculate the base address offset based on the index count value and the total number of storage areas.

7. The address remapping apparatus as described in claim 1, characterized in that, The current original logical address originates from the address information sent by the computing unit when performing a write or read operation.

8. The address remapping apparatus as described in claim 1, characterized in that, The intermediate result calculation process supports carry extension.

9. An address remapping method, characterized in that, The convolution kernel tensor is divided into N ichg ×N w ×N ochg There are N blocks; where N is a subset of N blocks. ichg N represents the number of input channel groups. w N represents the total number of weight positions for a single convolutional kernel. ochg The number of output channel groups; each block is configured with an independent storage area and a corresponding original logical address; the method is applicable to the address remapping apparatus as described in any one of claims 1 to 8, comprising: The first calculation module inverts the lower L bits of the input current original logical address to obtain the inverted L bits; where L is a set of bits that satisfy 2... L ≥N buf_ichg The smallest integer N; buf_ichg The total number of storage areas required to store all weight data within a single input channel group; The second calculation module obtains the offset correction value of the corresponding output channel group based on the current original logical address to ensure that N associated with the same weight position are correct. ochg The order of the output channel groups remains unchanged; wherein, the offset correction value is in N... w ×N ochg -N ochg The initial value is 2, the tolerance is 2, and the length is N. ochg A specified value in the first sequence; The third calculation module determines the base address offset of the corresponding input channel group relative to the first input channel group based on the current original logical address. The fourth calculation module performs a summation operation and a one-increment operation on the inverted result and the offset correction value to obtain an intermediate result and extract the low L bits to obtain the local logical address. The local logical address is added to the base address offset by the address synthesis module to obtain the target logical address corresponding to the current original logical address.

10. The address remapping method as described in claim 9, characterized in that, The second calculation module includes: a first loop counter; The step of obtaining the offset correction value of the corresponding output channel group based on the current original logical address through the second calculation module includes: The update frequency of the first count value of the first loop counter is synchronized with the update frequency of the current original logical address, and the counting period is N. ochg The first count value is used to track the N values ​​associated with the output channel group corresponding to the current original logical address at the same weight position. ochg The sequential position within each output channel group.

11. The address remapping method as described in claim 10, characterized in that, The second calculation module further includes: a correction parameter acquisition unit and a first offset calculation unit; The step of obtaining the offset correction value of the corresponding output channel group based on the current original logical address through the second calculation module also includes: The correction parameter acquisition unit is used to determine the correction parameter based on the first count value; wherein the correction parameter is in the form of -N ochg The initial value is 2, the tolerance is 2, and the length is N. ochg A specified value in the second sequence; The first offset calculation unit is used to calculate the offset correction value based on the correction parameters and the total number of storage areas.

12. A processor, characterized in that, Includes the address remapping device as described in any one of claims 1 to 8.

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