Electrostatic discharge protection circuit

Abstract

An electrostatic discharge protection circuit is coupled between a first voltage terminal and a second voltage terminal and includes first and second bipolar junction transistors. First ends of the first and second bipolar junction transistors are coupled to the first and second voltage terminals, respectively. Second ends of the first and second bipolar junction transistors are coupled to each other. Control terminals of the first and second bipolar junction transistors are coupled to each other. A breakdown voltage of a junction between the first end and the control terminal of the first bipolar junction transistor is greater than a breakdown voltage of a junction between the second end and the control terminal of the first bipolar junction transistor. A breakdown voltage of a junction between the first end and the control terminal of the second bipolar junction transistor is greater than a breakdown voltage of a junction between the second end and the control terminal of the second bipolar junction transistor.

Description

Technical Field

[0001] This invention relates to a circuit design technique, and more particularly to an electrostatic discharge (ESD) protection circuit. Background Technology

[0002] Electrostatic discharge (ESD) protection circuits are primarily designed to prevent damage to circuit systems caused by the current generated during ESD events, such as human body mannequin (HBM), systemic ESD, and electrical surges. ESD protection circuits are widely used in various integrated circuits. To suit different technical applications, ESD protection circuits can employ different types of transistors and diverse circuit structures. Summary of the Invention

[0003] This invention provides an electrostatic discharge protection (ESD) circuit that increases the overall anti-interference capability of the ESD circuit by using the base (B)-collector (C) junction in a heterojunction transistor.

[0004] The electrostatic discharge protection circuit of this invention is coupled between a first voltage terminal and a second voltage terminal. The electrostatic discharge protection circuit includes a first bipolar junction transistor (BJT) and a second BJT. The first BJT has a first terminal, a second terminal, and a control terminal, and the first terminal of the first BJT is coupled to the first voltage terminal. The second BJT has a first terminal, a second terminal, and a control terminal, the second terminal of the second BJT is coupled to the second terminal of the first BJT, the first terminal of the second BJT is coupled to the second voltage terminal, and the control terminal of the first BJT is coupled to the control terminal of the second BJT. A first breakdown voltage at a first junction between the first terminal and the control terminal of the first BJT is greater than a second breakdown voltage at a second junction between the second terminal and the control terminal of the first BJT. Furthermore, the third breakdown voltage of a third junction between the first terminal and the control terminal of the second bipolar junction transistor is greater than the fourth breakdown voltage of a fourth junction between the second terminal and the control terminal of the second bipolar junction transistor.

[0005] The electrostatic discharge protection circuit of this embodiment is coupled between a first voltage terminal and a second voltage terminal. The electrostatic discharge protection circuit includes a first bipolar junction transistor (BJT) and a second BJT. The first BJT has a first terminal, a second terminal, and a control terminal, and the first terminal of the first BJT is coupled to the first voltage terminal. The second BJT has a first terminal, a second terminal, and a control terminal, the second terminal of the second BJT is coupled to the second terminal of the first BJT, the first terminal of the second BJT is coupled to the second voltage terminal, and the control terminal of the first BJT is coupled to the control terminal of the second BJT. A first doping concentration of the semiconductor material forming the first end of the first bipolar junction transistor is less than a second doping concentration of the semiconductor material forming the second end of the first bipolar junction transistor, and a third doping concentration of the semiconductor material forming the first end of the second bipolar junction transistor is less than a fourth doping concentration of the semiconductor material forming the second end of the second bipolar junction transistor.

[0006] Based on the above, the electrostatic discharge protection circuit of this embodiment of the invention uses a specific circuit structure to couple the base (B)-collector (C) junction of a heterojunction transistor to the corresponding voltage terminal, instead of using the base (B)-emitter (E) junction with a lower breakdown voltage. Therefore, in the event of a voltage electrostatic discharge (ESD) event, the ESD protection circuit can increase its anti-interference capability based on the base-collector junction with a higher breakdown voltage. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of an electrostatic discharge (ESD) protection circuit according to an embodiment of the present invention.

[0008] Figures 2A to 2H These are circuit diagrams of ESD protection circuits according to the first to eighth embodiments of the present invention.

[0009] Figure 3 This is a circuit diagram of the impedance circuit according to various embodiments of the present invention.

[0010] Figures 4A to 4B These are circuit diagrams of ESD protection circuits according to the ninth to tenth embodiments of the present invention.

[0011] Figures 5A to 5G These are circuit diagrams of ESD protection circuits according to the eleventh to seventeenth embodiments of the present invention.

[0012] Symbol explanation:

[0013] 100, 100-1~100-17: Electrostatic discharge protection circuit

[0014] 210, 220, 210-1~210-M, 220-1~220-N, 211-1~211-9: Impedance circuits

[0015] 215, 225: Dashed arrows

[0016] HBT1, HBT2, HBTM1, HBTM2: Bipolar Junction Transistor / Transistor

[0017] HBN11, HBN12, HBN21, HBN22: Terminals of bipolar junction transistors

[0018] HBN1C, HBN2C: Control terminals of bipolar junction transistors

[0019] VN1, VN2: Voltage terminals

[0020] M1~M6: Semiconductor materials

[0021] VDD: Voltage input terminal

[0022] GND: Reference voltage terminal

[0023] R1: Resistor

[0024] C1: Capacitor

[0025] L1: Inductor

[0026] D1, D2: Diodes

[0027] FET1, FET2: Field-Effect Transistors

[0028] M1, M2: Metal-oxide-semiconductor field-effect transistors Detailed Implementation

[0029] Figure 1 This is a schematic diagram of an electrostatic discharge (ESD) protection circuit 100 according to an embodiment of the present invention. The ESD protection circuit 100 is coupled between voltage terminals VN1 and VN2. The ESD protection circuit 100 can be disposed at the input or output terminal of an electronic circuit (e.g., a high-power radio frequency signal processing circuit). The aforementioned high-power radio frequency signal processing circuit is, for example, an amplifier circuit, where voltage terminal VN1 is used to input a radio frequency signal, the power of which can be greater than or equal to 30 dBm.

[0030] Under normal operating voltage conditions, the ESD protection circuit 100 will not affect the operation of the electronic circuit. Conversely, if a surge occurs at either voltage terminal VN1 or VN2 due to electrostatic discharge, the ESD protection circuit 100 can divert the surge to the other voltage terminal, thereby protecting the input or output terminal of the electronic circuit from the impact of the surge. It is assumed here that the voltage value at voltage terminal VN1 is higher than the voltage value at voltage terminal VN2.

[0031] Although ESD protection circuits can be implemented using a single heterojunction transistor (HBT), the emitter (E) of the HBT is heavily doped with semiconductor material, making it highly conductive. This results in a low breakdown voltage at the base (B)-emitter (E) junction. Therefore, during positive / negative voltage ESD events—that is, when the voltage at terminal VN1 is higher / lower than the voltage at terminal VN2 for a certain period—the base (B)-emitter (E) junction of the HBT is prone to conduction due to its low breakdown voltage, leading to a decrease in the ESD protection circuit's immunity to these events. To achieve better immunity, a larger circuit layout area is required to house the HBT within the ESD protection circuit.

[0032] This invention employs a specific circuit structure to couple the base (B)-collector (C) junction of a heterojunction transistor to the corresponding voltage terminals VN1 and VN2. Therefore, in the event of the aforementioned positive / negative voltage ESD events, the ESD protection circuit can increase its anti-interference capability by utilizing the base-collector junction with a higher breakdown voltage.

[0033] Figures 2A to 2H These are circuit diagrams of ESD protection circuits 100-1 to 100-8 according to the first to eighth embodiments of the present invention. Figure 2A The ESD protection circuit 100-1 is coupled between voltage terminals VN1 and VN2. In this embodiment, voltage terminal VN1 is exemplified by the voltage input terminal VDD, and the voltage value of voltage terminal VN1 can be positive or negative. Voltage terminal VN2 is exemplified by the reference voltage terminal GND. Users of this embodiment can adjust the voltage values ​​on voltage terminals VN1 and VN2 according to their needs.

[0034] Figure 2AThe ESD protection circuit 100-1 includes bipolar junction transistors HBT1 and HBT2 (hereinafter referred to as transistors HBT1 and HBT2). Transistors HBT1 and HBT2 are disposed on the same integrated circuit substrate. In this embodiment, transistors HBT1 and HBT2 are implemented using heterojunction transistors (HBTs). The materials of transistors HBT1 and HBT2 may include, for example, silicon germanium, gallium arsenide, or silicon. Transistor HBT1 has a terminal HBN11 (e.g., collector terminal), a terminal HBN12 (e.g., emitter terminal), and a control terminal HBN1C (e.g., base terminal). Terminal HBN11 of transistor HBT1 is coupled to voltage terminal VN1.

[0035] Transistor HBT2 has terminals HBN21 (e.g., collector), HBN22 (e.g., emitter), and HBN2C (e.g., base). Terminal HBN22 (e.g., emitter) of transistor HBT2 is coupled to terminal HBN12 (e.g., emitter) of transistor HBT1. Terminal HBN21 of transistor HBT2 is coupled to voltage terminal VN2. The control terminal HBN1C of transistor HBT1 is coupled to the control terminal HBN2C of transistor HBT2.

[0036] In this embodiment, the breakdown voltage of the junction between terminal HBN11 and control terminal HBN1C of transistor HBT1 (referred to as the first junction) is greater than the breakdown voltage of the junction between terminal HBN12 and control terminal HBN1C of transistor HBT1 (referred to as the second junction). Furthermore, the breakdown voltage of the junction between terminal HBN21 and control terminal HBN2C of transistor HBT2 (referred to as the third junction) is greater than the breakdown voltage of the junction between terminal HBN22 and control terminal HBN2C of transistor HBT2 (referred to as the fourth junction).

[0037] Figure 2A The transistors HBT1 and HBT2 are NPN heterojunction bipolar transistors. Figure 2A The HBN11 terminal of transistor HBT1 is formed of semiconductor material M1, and the control terminal HBN1C of transistor HBT1 is formed of semiconductor material M2. The HBN21 terminal of transistor HBT2 is formed of semiconductor material M3, and the control terminal HBN2C of transistor HBT2 is formed of semiconductor material M4. The HBN12 terminal of transistor HBT1 and the HBN22 terminal of transistor HBT2 are both formed of semiconductor material M5.

[0038] Figure 2A Semiconductor materials M1, M3, and M5 possess the same conductivity type, for example, N-type or P-type conductivity. Semiconductor materials M2 and M4 possess the same conductivity type, but different conductivity types from the aforementioned semiconductor materials M1, M3, and M5. That is to say, such as Figure 2AIn one embodiment, semiconductor materials M1, M3, and M5 are N-type conductive semiconductor materials, while semiconductor materials M2 and M4 are P-type conductive semiconductor materials. On the other hand, in similar embodiments described later... Figure 2C In the diagram, semiconductor materials M1, M3, and M5 are P-type conductive semiconductor materials, while semiconductor materials M2 and M4 are N-type conductive semiconductor materials.

[0039] In this embodiment, transistors HBT1 and HBT2 are implemented using heterojunction transistors. Therefore, semiconductor material M5 is different from semiconductor material M1 or semiconductor material M3.

[0040] Figure 2A Semiconductor materials M1 and M3 are each lightly doped N-type semiconductor materials. Semiconductor materials M2 and M4 are each P-type semiconductor materials. Semiconductor material M5 is a heavily doped N-type semiconductor material. Therefore, it is possible to achieve a breakdown voltage at the first junction of transistor HBT1 that is greater than the breakdown voltage at the second junction of transistor HBT1, and a breakdown voltage at the third junction of transistor HBT2 that is greater than the breakdown voltage at the fourth junction of transistor HBT2. In other words, the doping concentration of semiconductor material M1 forming terminal HBN11 of transistor HBT1 will be less than the doping concentration of semiconductor material M5 forming terminal HBN12 of transistor HBT1, and the doping concentration of semiconductor material M3 forming terminal HBN21 of transistor HBT2 will be less than the doping concentration of semiconductor material M5 forming terminal HBN22 of transistor HBT2. The doping concentration of semiconductor material M1 is, for example, equal to the doping concentration of semiconductor material M3.

[0041] In this embodiment, both transistors HBT1 and HBT2 are designed as identical NPN or PNP heterojunction bipolar transistors. Therefore, the breakdown voltage of the first junction is equal to the breakdown voltage of the third junction, and the breakdown voltage of the second junction is equal to the breakdown voltage of the fourth junction.

[0042] Figure 2A The ESD protection circuit 100-1 further includes an impedance circuit 210. The impedance circuit 210 is coupled between the control terminal HBN1C of transistor HBT1 and the control terminal HBN2C of transistor HBT2. Detailed circuit structure of the impedance circuit 210 can be found below. Figure 3 And a description of the corresponding embodiments.

[0043] Impedance circuit 210 can provide a bias voltage to turn on transistors HBT1 and HBT2 when an ESD event occurs, thereby allowing transistors HBT1 and HBT2 to discharge ESD current. In this embodiment, the product of the impedance value of impedance circuit 210 and the breakdown current of the first junction in transistor HBT1 is greater than or equal to the turn-on voltage of the second junction in transistor HBT1. (Refer to...) Figure 2A An ESD event occurs when the voltage at voltage terminal VN1 is greater than the voltage at voltage terminal VN2, and the voltage difference between voltage terminals VN1 and VN2 is greater than the breakdown voltage of the first junction (the junction between terminal HBN11 and control terminal HBN1C) in transistor HBT1. At this time, because terminal HBN11 of transistor HBT1 is formed of a lightly doped semiconductor material, the breakdown voltage of the first junction of transistor HBT1 is high, thus resulting in high immunity to interference. Therefore, the first junction of transistor HBT1 will not be damaged, and a breakdown current will be generated. The breakdown current can flow along... Figure 2A The path indicated by the dashed arrow 215 flows through the impedance circuit 210. When the product of the impedance value of the impedance circuit 210 and the breakdown current of the first junction in transistor HBT1 is greater than the turn-on voltage of the second junction in transistor HBT1 (the junction between terminal HBN12 and control terminal HBN1C), transistor HBT1 can be turned on, and the aforementioned breakdown current can turn on transistor HBT2, thus forming an ESD current discharge path. In this way, the ESD current can be conducted from voltage terminal VN1 through transistors HBT1 and HBT2 to voltage terminal VN2. On the other hand, when the voltage value of voltage terminal VN1 is less than the voltage value of voltage terminal VN2, and the voltage difference between voltage terminals VN1 and VN2 is greater than the breakdown voltage of the third junction in transistor HBT2 (the junction between terminal HBN21 and control terminal HBN2C), an ESD event occurs. At this point, because the HBN21 terminal of transistor HBT2 is formed of a lightly doped semiconductor material, the breakdown voltage of the third junction of transistor HBT2 is relatively high, thus resulting in high interference immunity. Therefore, the third junction of transistor HBT2 will not be damaged, and a breakdown current will be generated. The breakdown current can flow along... Figure 2A The path indicated by the dashed arrow 225 flows through the impedance circuit 210. When the product of the impedance value of the impedance circuit 210 and the breakdown current of the third junction in transistor HBT2 is greater than the turn-on voltage of the fourth junction in transistor HBT2 (the junction between terminal HBN22 and control terminal HBN1C), transistor HBT2 can be turned on, and the aforementioned breakdown current can turn on transistor HBT1, thus forming an ESD current discharge path. In this way, the ESD current can be conducted from voltage terminal VN2 through transistors HBT2 and HBT1 to voltage terminal VN1.

[0044] Figure 2A and Figure 2B Both HBT1 and HBT2 are NPN heterojunction bipolar transistors. Figure 2B ESD protection circuit 100-2 and Figure 2AThe difference between the ESD protection circuits 100-1 and 100-2 is that in ESD protection circuit 100-2, the terminal HBN12 of transistor HBT1 is coupled to the control terminal HBN1C of transistor HBT1, and the terminal HBN22 of transistor HBT2 is coupled to the control terminal HBN2C of transistor HBT2, and the terminal HBN22 of transistor HBT1 is coupled to the terminal HBN22 of transistor HBT2. On the other hand, Figure 2B The ESD protection circuit 100-2 includes impedance circuits 210 and 220. Impedance circuit 210 is coupled between the control terminal HBN1C and terminal HBN12 of transistor HBT1. Impedance circuit 220 is coupled between the control terminal HBN2C and terminal HBN22 of transistor HBT2. Detailed circuit structures of impedance circuits 210 and 220 can be found below. Figure 3 And a description of the corresponding embodiments.

[0045] Impedance circuits 210 and 220 can provide bias voltage to turn on transistors HBT1 and HBT2 when an ESD event occurs, thereby allowing transistors HBT1 and HBT2 to discharge ESD current. In this embodiment, the sum of the impedance values ​​of impedance circuit 210 and impedance circuit 220 is the combined impedance value. The product of the combined impedance value and the breakdown current of the first junction in transistor HBT1 is greater than or equal to the on-state voltage of the second junction in transistor HBT1. (Refer to...) Figure 2B When the voltage at voltage terminal VN1 is greater than the voltage at voltage terminal VN2, and the voltage difference between voltage terminals VN1 and VN2 is greater than the breakdown voltage of the first junction (the junction between terminal HBN11 and control terminal HBN1C) in transistor HBT1, an ESD event occurs. At this time, because terminal HBN11 of transistor HBT1 is formed of a lightly doped semiconductor material, the breakdown voltage of the first junction of transistor HBT1 is high, thus resulting in high anti-interference capability. Therefore, the first junction of transistor HBT1 will not be damaged, and a breakdown current will be generated. The breakdown current can flow along... Figure 2BThe path indicated by the dashed arrow 215 flows through impedance circuits 210 and 220. When the combined impedance of impedance circuits 210 and 220, plus the breakdown current at the first junction of transistor HBT1, is greater than the turn-on voltage at the second junction of transistor HBT1 (the junction between terminal HBN12 and control terminal HBN1C), transistor HBT1 can be turned on, and the aforementioned breakdown current can turn on transistor HBT2, thus forming an ESD current discharge path. In this way, the ESD current can be conducted from voltage terminal VN1 through transistors HBT1 and HBT2 to voltage terminal VN2. On the other hand, when the voltage value at voltage terminal VN1 is less than the voltage value at voltage terminal VN2, and the voltage difference between voltage terminals VN1 and VN2 is greater than the breakdown voltage at the third junction of transistor HBT2 (the junction between terminal HBN21 and control terminal HBN2C), an ESD event occurs. At this point, because the HBN21 terminal of transistor HBT2 is formed of a lightly doped semiconductor material, the breakdown voltage of the third junction of transistor HBT2 is relatively high, thus resulting in high interference immunity. Therefore, the third junction of transistor HBT2 will not be damaged, and a breakdown current will be generated. The breakdown current can flow along... Figure 2B The path indicated by the dashed arrow 225 flows through impedance circuit 210. When the combined impedance of impedance circuits 210 and 220, plus the breakdown current at the third junction of transistor HBT2, is greater than the on-state voltage at the fourth junction of transistor HBT2 (the junction between terminal HBN22 and control terminal HBN1C), transistor HBT2 can be turned on, and the aforementioned breakdown current can turn on transistor HBT1, thus forming an ESD current discharge path. In this way, the ESD current can be conducted from voltage terminal VN2 through transistors HBT2 and HBT1 to voltage terminal VN1.

[0046] Compared to Figure 2A and Figure 2B , Figure 2C ESD protection circuit 100-3 and Figure 2D The ESD protection circuit 100-4 uses different types of heterojunction bipolar transistors to implement transistors HBT1 and HBT2. Figure 2C and Figure 2D Both HBT1 and HBT2 are PNP heterojunction bipolar transistors. That is to say, Figure 2A and Figure 2C The coupling relationships of the circuit structures are the same; the only difference between the two is that transistors HBT1 and HBT2 are NPN or PNP heterojunction bipolar transistors. Figure 2B and Figure 2D The coupling relationships of the circuit structures are the same; the only difference between the two is that transistors HBT1 and HBT2 are NPN or PNP heterojunction bipolar transistors. Figure 2C and Figure 2D In the transistors HBT1 and HBT2, semiconductor materials M1 and M3 are low-doped P-type semiconductor materials, semiconductor materials M2 and M4 are N-type semiconductor materials, and semiconductor material M5 is a high-doped P-type semiconductor material.

[0047] Compared to Figures 2A to 2D , Figures 2E to 2H In the ESD protection circuits 100-5 to 100-8, transistors HBT1 and HBT2 are implemented using different types of heterojunction bipolar transistors. For example, Figure 2E and Figure 2F PNP and NPN transistors are used to implement transistors HBT1 and HBT2 respectively; Figure 2G and Figure 2H The transistors HBT1 and HBT2 are implemented using NPN and PNP type transistors respectively. Figures 2E to 2G In this transistor, the HBN11 terminal of HBT1 is formed of semiconductor material M1, and the control terminal HBN1C of HBT1 is formed of semiconductor material M2. The HBN21 terminal of HBT2 is formed of semiconductor material M3, and the control terminal HBN2C of HBT2 is formed of semiconductor material M4. The HBN12 terminal of HBT1 is formed of semiconductor material M5, and the HBN22 terminal of HBT2 is formed of semiconductor material M6. The doping concentration of semiconductor material M1 forming the HBN11 terminal of HBT1 is less than the doping concentration of semiconductor material M5 forming the HBN12 terminal of HBT1, and the doping concentration of semiconductor material M3 forming the HBN21 terminal of HBT2 is less than the doping concentration of semiconductor material M6 forming the HBN22 terminal of HBT2. For example, the doping concentration of semiconductor material M1 is equivalent to the doping concentration of semiconductor material M3. For example, the doping concentration of semiconductor material M5 is equivalent to the doping concentration of semiconductor material M6.

[0048] Figure 2E and Figure 2F Semiconductor materials M1, M4, and M5 possess the same conductivity type, for example, N-type or P-type conductivity. Semiconductor materials M2, M3, and M6 possess the same conductivity type, but different conductivity types from the aforementioned semiconductor materials M1, M4, and M5. That is to say, such as Figure 2E and Figure 2F In one embodiment, semiconductor materials M1, M4, and M5 are P-type conductive semiconductor materials, while semiconductor materials M2, M3, and M6 are N-type conductive semiconductor materials. On the other hand, in similar embodiments described later... Figure 2G and Figure 2HIn the diagram, semiconductor materials M1, M4, and M5 are N-type conductive semiconductor materials, while semiconductor materials M2, M3, and M6 are P-type conductive semiconductor materials.

[0049] In this embodiment, transistors HBT1 and HBT2 are implemented using heterojunction transistors. Therefore, semiconductor material M1 is different from semiconductor material M5, and semiconductor material M3 is different from semiconductor material M6.

[0050] exist Figure 2E ESD protection circuit 100-5 and Figure 2F In the ESD protection circuit 100-6, transistor HBT1 is a PNP heterojunction bipolar transistor, and transistor HBT2 is an NPN heterojunction bipolar transistor. Specifically, semiconductor material M1 is a lightly doped P-type semiconductor material, semiconductor material M2 is an N-type semiconductor material, and semiconductor material M3 is a lightly doped N-type semiconductor material. Semiconductor material M4 is a P-type semiconductor material, semiconductor material M5 is a heavily doped P-type semiconductor material, and semiconductor material M6 is a heavily doped N-type semiconductor material.

[0051] Figure 2E The control terminal HBN1C of transistor HBT1 is coupled to the control terminal HBN2C of transistor HBT2 through impedance circuit 210.

[0052] Figure 2F The control terminal HBN1C of transistor HBT1 is coupled to terminal HBN12 of transistor HBT1 through impedance circuit 210. Figure 2F The control terminal HBN2C of transistor HBT2 is coupled to terminal HBN22 of transistor HBT2 through impedance circuit 220. Furthermore, terminal HBN12 of transistor HBT1 is coupled to terminal HBN22 of transistor HBT2.

[0053] exist Figure 2G ESD protection circuit 100-7 and Figure 2H In the ESD protection circuit 100-8, transistor HBT1 is an NPN heterojunction bipolar transistor, and transistor HBT2 is a PNP heterojunction bipolar transistor. Specifically, semiconductor material M1 is a lightly doped N-type semiconductor material, semiconductor material M2 is a P-type semiconductor material, and semiconductor material M3 is a lightly doped P-type semiconductor material. Semiconductor material M4 is an N-type semiconductor material, semiconductor material M5 is a heavily doped N-type semiconductor material, and semiconductor material M6 is a heavily doped P-type semiconductor material.

[0054] Figure 2G The control terminal HBN1C of transistor HBT1 is coupled to the control terminal HBN2C of transistor HBT2 through impedance circuit 210.

[0055] Figure 2H The control terminal HBN1C of transistor HBT1 is coupled to terminal HBN12 of transistor HBT1 through impedance circuit 210. Figure 2H The control terminal HBN2C of transistor HBT2 is coupled to terminal HBN22 of transistor HBT2 through impedance circuit 220. Furthermore, terminal HBN12 of transistor HBT1 is coupled to terminal HBN22 of transistor HBT2.

[0056] Figure 3 This is a circuit diagram of the impedance circuit 210 according to various embodiments of the present invention. The impedance circuits 210 and 220 of various embodiments of the present invention can be... Figure 3 Impedance circuits 211-1 to 211-9 or other circuit structures can be used to implement this. In the various embodiments of the present invention, impedance circuits 210, 220, 210-1 to 210-M (representing an arrangement from 210-1, 210-2, 210-3 up to 210-M) and 220-1 to 220-N (representing an arrangement from 220-1, 220-2, 220-3 up to 220-N) can be of the same circuit structure, or derived from... Figure 3 The impedance circuits 211-1 to 211-9 can be selected arbitrarily to achieve this.

[0057] Figure 3 The various impedance circuits 211-1 to 211-9 may include one or a combination of a resistor R1 (impedance circuit 211-1), a capacitor C1 (impedance circuit 211-2), an inductor L1 (impedance circuit 211-3), at least one diode (e.g., diodes D1 and D2), at least one first field-effect transistor (e.g., field-effect transistors FET1 and FET2), and at least one first metal-oxide-semiconductor field-effect transistor (MOSFET) (e.g., metal-oxide-semiconductor field-effect transistors M1 and M2). Impedance circuits 211-4 and 211-5 respectively include one or more diodes D1 and D2 connected in series. In other words, impedance circuits 211-4 and 211-5 are formed by stacking multiple diodes D1 and D2.

[0058] Impedance circuits 211-6 and 211-7 are each composed of multiple field-effect transistors (FETs) 1 or 2 connected in series. The control terminal of each FET1 or FET2 is coupled to its source or drain terminal. FET1 or FET2 can be N-type or P-type FETs. In other words, impedance circuits 211-6 and 211-7 are formed by stacking multiple FET1 and FET2 transistors, respectively.

[0059] Impedance circuits 211-8 and 211-9 are each composed of multiple MOSFETs M1 or M2 connected in series, with the control terminal of each MOSFET M1 or M2 coupled to its source or drain terminal. MOSFET M1 or M2 can be N-type or P-type field-effect transistors. In other words, impedance circuits 211-8 and 211-9 are formed by stacking multiple MOSFETs M1 and M2, respectively.

[0060] Figures 2A to 2H In this embodiment, terminal HBN12 of transistor HBT1 is directly coupled to terminal HBN22 of transistor HBT2. Alternatively, in this embodiment, terminal HBN12 of transistor HBT1 can be coupled to terminal HBN22 of transistor HBT2 through one or more intermediate transistors, such as... Figures 4A-4B and Figure 5A-5G As shown.

[0061] Figures 4A to 4B These are circuit diagrams of ESD protection circuits 100-9 to 100-10 according to the ninth to tenth embodiments of the present invention. Figures 4A to 4B The transistors HBT1, HBT2, HBTM1, and HBTM2 in the diagram are all implemented based on NPN heterojunction bipolar transistors. The terminal of transistor HBT1 (e.g., the emitter terminal) is connected to one or more intermediate transistors (e.g.,...). Figures 4A-4B and Figure 5A-5G One or more transistors HBTM1 and HBTM2 are coupled to the terminals (e.g., emitter terminals) of transistor HBT2. Figure 4A An impedance circuit 210-1 to 210-M (representing 210-1, 210-2, 210-3, and so on up to 210-M) can be provided between the control terminal of transistor HBT1 and the control terminal of the next stage transistor (e.g., transistor HBTM1). It is worth noting that... Figure 4A In a variant embodiment, the impedance circuit can use only the impedance circuit 210-M closest to the middle (this impedance circuit 210-M is coupled to the control terminal of transistor HBTM1 and the control terminal of transistor HBTM2), and the impedance circuits 210-1, 210-2, 210-3...210-(M-1) can be omitted. Figure 4B Furthermore, an impedance circuit 220-1 to 220-N (representing 220-1, 220-2, 220-3, and so on up to 220-N) can be additionally provided between the control terminal of transistor HBT2 and the control terminal of the next stage transistor (e.g., transistor HBTM2). It is worth noting that... Figure 4BIn a variant embodiment, the impedance circuit may use only the impedance circuit 210-M closest to the middle and the impedance circuit 220-N (this impedance circuit 210-M is directly coupled to this impedance circuit 220-N), and the impedance circuits 210-1, 210-2, 210-3…210-(M-1) and impedance circuits 220-1, 220-2, 220-3…220-(N-1) may be omitted.

[0062] The control terminals of the transistors HBTM1 and HBTM2 closest to the middle do not need to be coupled to their emitter terminals (e.g., Figure 4A (As shown), or, the control terminals of the transistors HBTM1 and HBTM2 closest to the middle can be coupled to their emitter terminals (as shown). Figure 4B (As shown). Transistors HBT1 and HBT2 have base-collector junctions with high breakdown voltages coupled to voltage terminals VN1 and VN2.

[0063] On the other hand, the series connection method between the junctions of the transistors located between transistors HBT1 and HBT2 (e.g., transistors HBTM1 and HBTM2) is not limited to the embodiments of the present invention. Figures 5A to 5G These are circuit diagrams of ESD protection circuits 100-11 to 100-17 according to the eleventh to seventeenth embodiments of the present invention. Figure 5A and Figure 4B The difference is that, Figure 5A The coupling method between the emitter and collector terminals of the transistor HBTM1, which is closest to the center in the ESD protection circuit 100-11, is similar to... Figure 4B The ESD protection circuit in the middle is different from the HBTM1 transistor in the 100-10 transistor.

[0064] Figure 5B and Figure 4B The difference is that, Figure 5B The coupling method between the emitter and collector terminals of the transistor HBTM2, which is closest to the center in the ESD protection circuit 100-12, is similar to... Figure 4B The ESD protection circuit in the middle is different from the 100-10 transistor HBTM2.

[0065] Figures 5C to 5E In the ESD protection circuit 100-13 to 100-15, transistors HBT1 and HBT2 are PNP heterojunction bipolar transistors, and... Figure 4B The ESD protection circuits in the Chinese version 100-10 are different. Furthermore, Figure 5C The transistors HBTM1 and HBTM2 in the ESD protection circuit 100-13 are NPN heterojunction bipolar transistors.

[0066] Figure 5DIn the ESD protection circuit 100-14, transistor HBTM1 is a PNP heterojunction bipolar transistor, and transistor HBTM2 is an NPN heterojunction bipolar transistor.

[0067] Figure 5E In the ESD protection circuit 100-15, transistor HBTM1 is an NPN heterojunction bipolar transistor, and transistor HBTM2 is a PNP heterojunction bipolar transistor.

[0068] Figure 5F In the ESD protection circuit 100-16, transistor HBT1 is a PNP heterojunction bipolar transistor, while transistors HBTM1, HBTM2, and HBT2 are NPN heterojunction bipolar transistors.

[0069] Figure 5G In the ESD protection circuit 100-17, transistors HBT1 and HBTM2 are NPN heterojunction bipolar transistors, while transistors HBTM1 and HBT2 are PNP heterojunction bipolar transistors.

[0070] In summary, the electrostatic discharge protection circuit of this invention, through a specific circuit structure, utilizes the base (B)-collector (C) junction of a heterojunction transistor to couple to the corresponding voltage terminal, instead of using the base (B)-emitter (E) junction with a lower breakdown voltage. Therefore, in the event of a voltage electrostatic discharge (ESD) event, the ESD protection circuit can increase its anti-interference capability based on the base-collector junction with a higher breakdown voltage.

[0071] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. An electrostatic discharge protection circuit, coupled between a first voltage terminal and a second voltage terminal, characterized in that, The electrostatic discharge protection circuit includes: A first bipolar junction transistor has a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first bipolar junction transistor is coupled to the first voltage terminal; and A second bipolar junction transistor (BJT) has a first terminal, a second terminal, and a control terminal. The second terminal of the second BJT is coupled to the second terminal of the first BJT. The first terminal of the second BJT is coupled to a second voltage terminal. The control terminal of the first BJT is coupled to the control terminal of the second BJT. Wherein, a first breakdown voltage at a first junction between the first terminal of the first bipolar junction transistor and the control terminal is greater than a second breakdown voltage at a second junction between the second terminal of the first bipolar junction transistor and the control terminal. Furthermore, the third breakdown voltage of a third junction between the first terminal of the second bipolar junction transistor and the control terminal is greater than the fourth breakdown voltage of a fourth junction between the second terminal of the second bipolar junction transistor and the control terminal.

2. The electrostatic discharge protection circuit according to claim 1, characterized in that, The first terminal of the first bipolar junction transistor is formed of a first type of semiconductor material, and the control terminal of the first bipolar junction transistor is formed of a second type of semiconductor material. The first terminal of the second bipolar junction transistor is formed of a third type of semiconductor material, and the control terminal of the second bipolar junction transistor is formed of a fourth type of semiconductor material. The second terminal of both the first bipolar junction transistor and the second bipolar junction transistor is formed of a type 5 semiconductor material. The first type semiconductor material, the third type semiconductor material, and the fifth type semiconductor material have the same conductivity type, and the fifth type semiconductor material is different from the first type semiconductor material or the third type semiconductor material. The second type semiconductor material and the fourth type semiconductor material have the same conductivity type.

3. The electrostatic discharge protection circuit according to claim 2, characterized in that, The first type semiconductor material and the third type semiconductor material are each a lightly doped N-type semiconductor material, the second type semiconductor material and the fourth type semiconductor material are each a P-type semiconductor material, and the fifth type semiconductor material is a heavily doped N-type semiconductor material.

4. The electrostatic discharge protection circuit according to claim 2, characterized in that, The first type semiconductor material and the third type semiconductor material are each a lightly doped P-type semiconductor material, the second type semiconductor material and the fourth type semiconductor material are each an N-type semiconductor material, and the fifth type semiconductor material is a heavily doped P-type semiconductor material.

5. The electrostatic discharge protection circuit according to claim 1, characterized in that, The first terminal of the first bipolar junction transistor is formed of a first type of semiconductor material, and the control terminal of the first bipolar junction transistor is formed of a second type of semiconductor material. The first terminal of the second bipolar junction transistor is formed of a third type of semiconductor material, and the control terminal of the second bipolar junction transistor is formed of a fourth type of semiconductor material. The second terminal of the first bipolar junction transistor is formed of a type 5 semiconductor material, and the second terminal of the second bipolar junction transistor is formed of a type 6 semiconductor material. The first type semiconductor material, the fourth type semiconductor material, and the fifth type semiconductor material have the same conductivity type, and the second type semiconductor material, the third type semiconductor material, and the sixth type semiconductor material have the same conductivity type.

6. The electrostatic discharge protection circuit according to claim 5, characterized in that: The first type of semiconductor material is a lightly doped P-type semiconductor material, the second type of semiconductor material is an N-type semiconductor material, the third type of semiconductor material is a lightly doped N-type semiconductor material, the fourth type of semiconductor material is a P-type semiconductor material, the fifth type of semiconductor material is a heavily doped P-type semiconductor material, and the sixth type of semiconductor material is a heavily doped N-type semiconductor material. Alternatively, the first type of semiconductor material is a lightly doped N-type semiconductor material, the second type of semiconductor material is a P-type semiconductor material, the third type of semiconductor material is a lightly doped P-type semiconductor material, the fourth type of semiconductor material is an N-type semiconductor, the fifth type of semiconductor material is a heavily doped N-type semiconductor material, and the sixth type of semiconductor material is a heavily doped P-type semiconductor material.

7. The electrostatic discharge protection circuit according to claim 1, characterized in that, The first breakdown voltage is equal to the third breakdown voltage, and the second breakdown voltage is equal to the fourth breakdown voltage.

8. The electrostatic discharge protection circuit according to claim 1, characterized in that, The first terminal of the first bipolar junction transistor is a first collector, the second terminal of the first bipolar junction transistor is a first emitter, the first terminal of the second bipolar junction transistor is a second collector, the second terminal of the second bipolar junction transistor is a second emitter, and the first emitter is coupled to the second emitter.

9. The electrostatic discharge protection circuit according to claim 1, characterized in that, The second terminal of the first bipolar junction transistor is coupled to the second terminal of the second bipolar junction transistor through one or more intermediate transistors.

10. The electrostatic discharge protection circuit according to claim 1, characterized in that, It also includes a first impedance circuit and a second impedance circuit. The first impedance circuit is coupled between the control terminal and the second terminal of the first bipolar junction transistor. The second impedance circuit is coupled between the control terminal and the second terminal of the second bipolar junction transistor, and the second terminal of the first bipolar junction transistor is coupled to the second terminal of the second bipolar junction transistor.

11. The electrostatic discharge protection circuit according to claim 10, characterized in that, The first impedance circuit includes one or a combination of a first resistor, a first capacitor, a first inductor, a first diode, at least one first field-effect transistor, and at least one first metal-oxide-semiconductor field-effect transistor. The second impedance circuit includes one or a combination of a second resistor, a second capacitor, a second inductor, a second diode, at least one second field-effect transistor, and at least one second metal-oxide-semiconductor field-effect transistor.

12. The electrostatic discharge protection circuit according to claim 10, characterized in that, The sum of the impedance values ​​of the first impedance circuit and the second impedance circuit is a composite impedance value. When the voltage value of the first voltage terminal is greater than the voltage value of the second voltage terminal and an electrostatic discharge event occurs, the product of the composite impedance value and a first breakdown current at the first junction of the first bipolar junction transistor is greater than or equal to a first on-state voltage at the second junction of the first bipolar junction transistor. When the voltage value of the second voltage terminal is greater than the voltage value of the first voltage terminal and an electrostatic discharge event occurs, the product of the composite impedance value and a third breakdown current at the third junction of the second bipolar junction transistor is greater than or equal to a second on-state voltage at the fourth junction of the second bipolar junction transistor.

13. The electrostatic discharge protection circuit according to claim 1, characterized in that, It also includes a first impedance circuit, which is coupled between the control terminal of the first bipolar junction transistor and the control terminal of the second bipolar junction transistor.

14. The electrostatic discharge protection circuit according to claim 13, characterized in that, The first impedance circuit includes one or a combination of a resistor, capacitor, inductor, diode, field-effect transistor and metal-oxide-semiconductor field-effect transistor.

15. The electrostatic discharge protection circuit according to claim 13, characterized in that, When the voltage value at the first voltage terminal is greater than the voltage value at the second voltage terminal, and an electrostatic discharge event occurs, the product of the impedance value of the first impedance circuit and a first breakdown current at the first junction of the first bipolar junction transistor is greater than or equal to a first turn-on voltage at the second junction of the first bipolar junction transistor. When the voltage value at the second voltage terminal is greater than the voltage value at the first voltage terminal, and an electrostatic discharge event occurs, the product of the impedance value of the first impedance circuit and a third breakdown current at the third junction of the second bipolar junction transistor is greater than or equal to a second turn-on voltage at the fourth junction of the second bipolar junction transistor.

16. The electrostatic discharge protection circuit according to claim 1, characterized in that, Both the first bipolar junction transistor and the second bipolar junction transistor are heterojunction bipolar transistors.

17. The electrostatic discharge protection circuit according to claim 1, characterized in that, The first voltage terminal is the voltage input terminal, and the second voltage terminal is the reference voltage terminal.

18. The electrostatic discharge protection circuit according to claim 1, characterized in that, The electrostatic discharge protection circuit is used in a high-power radio frequency signal processing circuit.

19. An electrostatic discharge protection circuit, coupled between a first voltage terminal and a second voltage terminal, characterized in that, The electrostatic discharge protection circuit includes: A first bipolar junction transistor has a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first bipolar junction transistor is coupled to the first voltage terminal; and A second bipolar junction transistor (BJT) has a first terminal, a second terminal, and a control terminal. The second terminal of the second BJT is coupled to the second terminal of the first BJT, the first terminal of the second BJT is coupled to a second voltage terminal, and the control terminal of the first BJT is coupled to the control terminal of the second BJT. Wherein, a first doping concentration of the semiconductor material forming the first end of the first bipolar junction transistor is less than a second doping concentration of the semiconductor material forming the second end of the first bipolar junction transistor, and a third doping concentration of the semiconductor material forming the first end of the second bipolar junction transistor is less than a fourth doping concentration of the semiconductor material forming the second end of the second bipolar junction transistor.

20. The electrostatic discharge protection circuit according to claim 19, characterized in that, The first doping concentration is equal to the third doping concentration, and the second doping concentration is equal to the fourth doping concentration.

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