A method for distributed power equalization and voltage regulation of a cluster of current-controlled power converters

Abstract

The application provides a distributed power balancing and voltage regulating method for a current control type converter cluster. The method belongs to the field of micro-grid control, and is based on reactive voltage droop and voltage amplitude control to generate a reference current amplitude of the parallel converter, so that each parallel converter outputs the same current amplitude; meanwhile, the phase of the current vector is determined by four-quadrant power factor control, so as to ensure that the output currents among the parallel converters are in the same phase state, and the load side currents are effectively superimposed and the maximum load current is obtained. In view of the harmonic problem caused by the access of a nonlinear load, the application further adopts harmonic virtual impedance control at a fundamental frequency and selected harmonic frequencies, and combines with the multi-resonance controller adjustment of the current loop to effectively reduce the amplitude of the equivalent harmonic impedance of the DG unit, so that the harmonic circulating current among the DGs is minimized, and the power quality at the point of common coupling (PCC) is improved.

Description

Technical Field

[0001] This invention belongs to the field of microgrid system control, specifically relating to a distributed power balancing and voltage regulation method for a current-controlled converter cluster. This method, based on power factor control and reactive voltage control, ensures that the current of parallel converters operates at the same amplitude. Simultaneously, it utilizes multi-resonant control of the fundamental frequency and selected harmonic virtual impedances, significantly improving the power quality of the common bus. Background Technology

[0002] With the increasing penetration of distributed photovoltaic, energy storage, and various power electronic interface power supplies in distribution networks and microgrids, connecting multiple converters in parallel to the point of common coupling (PCC) to achieve capacity expansion and redundant power supply has become a common application scenario. Parallel systems need to have voltage support, frequency support, and power sharing capabilities simultaneously under islanded operation or weak grid conditions. However, in engineering practice, they generally face problems such as uneven power distribution, difficulty in suppressing circulating current, and deterioration of power quality.

[0003] On the one hand, the line impedances from multiple DG units to the PCC are often inconsistent. Combined with filter parameter deviations and measurement errors, this leads to differences in port voltages and output characteristics across parallel systems. This results in reactive power distribution deviations, increased parallel circulating current, and increased current stress in local units. In severe cases, it triggers current limiting or overcurrent protection, reducing system stability margin and available capacity. On the other hand, nonlinear loads such as rectifiers and frequency converters are widespread in microgrids. The injection of load harmonic currents into the feeder impedance generates harmonic voltage drops, distorting the PCC voltage and causing a redistribution of harmonic power among parallel branches. This results in uneven harmonic current distribution across each DG unit, increased harmonic circulating current, and consequently, increased device losses, temperature rise, and the risk of protection malfunctions.

[0004] In existing parallel control methods, traditional grid-type droop strategies primarily target voltage source converters, whose output side exhibits low impedance voltage characteristics. However, in parallel scenarios with current-controlled converters, the control objective is primarily current, leading to stronger line impedance coupling between voltage and power. Without coordinated design for "current phase consistency," "current amplitude consistency," and "controllable equivalent impedance in the harmonic frequency band," problems such as non-phase parallel currents, current sharing deviations, and difficulty in suppressing harmonic circulating currents can easily arise. Therefore, a control method for current-controlled parallel converter clusters is urgently needed, capable of achieving power balance and voltage regulation in parallel systems even with inconsistent line impedances and nonlinear loads, while effectively reducing PCC harmonic distortion and harmonic circulating currents. Summary of the Invention

[0005] This invention proposes a distributed power balancing and voltage regulation method for current-controlled converter clusters, applicable to multiple DGs in parallel and nonlinear load conditions. It achieves in-phase operation and improved power quality of the parallel system through coordinated control of the fundamental power loop, harmonic compensation, and the inner current loop. At the fundamental level, an angular velocity reference is generated using four-quadrant power factor droop and integrated to obtain a phase reference, ensuring that the output currents of each DG remain in phase and frequency. Simultaneously, a voltage amplitude reference is obtained using reactive power-voltage droop, and a fundamental current amplitude command is generated based on the squared voltage amplitude closed-loop adjustment, enabling the parallel DGs to operate with consistent current amplitudes, achieving load current superposition and power balancing. At the harmonic level, each DG locally samples the PCC voltage and extracts selected harmonic components. Based on the line harmonic impedance and the preset shunt target, a virtual harmonic impedance is constructed. The harmonic voltage is converted into a harmonic compensation current and synthesized with the fundamental reference. The inner current loop uses a multi-resonant PR controller to perform high-gain tracking / suppression of the fundamental and multiple harmonics, and is combined with dynamic amplitude limiting to ensure that the synthesized current does not exceed the limit, thereby suppressing harmonic circulating current, reducing PCC voltage distortion, and improving the system's operational robustness.

[0006] The objective of this invention is achieved through the following technical solution: The method of this invention is implemented by the local controller of the parallel DG unit, and its technical solution includes at least the following key steps: First, the local controller collects the PCC voltage and output current and calculates the active / reactive power in the αβ coordinate system, and obtains the fundamental power component after filtering; based on the four-quadrant power factor droop, an angular velocity reference is generated and integrated to obtain the phase, which is used as the phase reference for synthesizing the fundamental current vector, thereby ensuring that the output current of the parallel DG tends to be in phase; at the same time, a voltage amplitude reference is obtained based on the reactive power-voltage droop, and a fundamental current amplitude command is generated by the voltage amplitude squared closed-loop PI regulation, combined with a dynamic limiter to constrain the synthesized current of "fundamental current + harmonic compensation current" from exceeding the limit, thus obtaining the fundamental current reference. Secondly, for a preset set of harmonic orders (e.g., 5th, 7th, 11th, and 13th), the harmonic voltage components of each order are obtained from the local voltage signal via a harmonic extraction module. Based on the line harmonic impedance and the preset harmonic shunt target, a virtual harmonic impedance is constructed. The harmonic voltage is then converted into the harmonic compensation current for each order through the virtual impedance, forming a harmonic current reference. This reference is then combined with the fundamental current reference to obtain the total current reference. Finally, the inner current loop uses a multi-resonant PR controller to track and adjust the total current reference, outputting the reference signal required for modulation. After coordinate transformation and normalization with the DC bus voltage, the PWM modulation amount is obtained to drive the inverter to output the target current, thereby achieving power balance, voltage regulation, and PCC harmonic suppression under parallel operation.

[0007] Compared with the prior art, the beneficial effects of the technical solution of the present invention are: 1. By applying the technical solution proposed in this invention, it is possible to achieve synchronous current and power balance in parallel distributed generation (DG) systems. The phase is obtained through four-quadrant power factor droop, and a consistent current amplitude command is generated by reactive voltage droop and voltage amplitude control, ensuring that the current amplitude and phase of each unit are consistent.

[0008] 2. Applying the technical solution proposed in this invention can reduce the risks of circulating current and overcurrent caused by inconsistent line impedance. Using a current reference as the core and combined with dynamic limiting of the synthesized current, parallel circulating current can still be suppressed and operational stability improved under load disturbances and parameter mismatches.

[0009] 3. By applying the technical solution proposed in this invention, voltage and current distortion caused by nonlinear loads can be suppressed and the power quality at the PCC point can be improved. Through specific frequency harmonic virtual impedance, combined with a multi-resonant PR current loop, the 5th and 7th harmonic components and PCC voltage distortion can be effectively reduced. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a distributed power balancing and voltage regulation method for a current-controlled converter cluster provided in an embodiment of the present invention; Figure 2 A block diagram of a distributed power balancing and voltage regulation controller for a current-controlled converter cluster is provided in this embodiment of the invention. Figure 3 An equivalent circuit diagram of a distributed power balancing and voltage regulation method for a current-controlled converter cluster provided in this embodiment of the invention; Figure 4 Root locus diagrams of different control parameters for a current source converter provided in an embodiment of the present invention; Figure 5 This is a diagram showing the variation of system harmonic THD provided in an embodiment of the present invention. Figure 6 A system power allocation diagram provided for an embodiment of the present invention; Figure 7 The simulation effect diagram of system load change provided in the embodiment of the present invention; Figure 8 Simulation results of different control parameters of the system provided in this embodiment of the invention; Figure 9 The simulation effect diagram of PCC point harmonic suppression provided in the embodiment of the present invention; Figure 10 A schematic diagram of a module embodiment of a distributed power balancing and voltage regulation method for a current-controlled converter cluster provided in this invention. Figure 11 This is a schematic diagram of a distributed power balancing and voltage regulation method device for a current-controlled converter cluster provided in an embodiment of the present invention. Detailed Implementation

[0011] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The specific operational methods in the method embodiments can also be applied to the system embodiments. It should be noted that in the description of this application, "at least one" refers to one or more, where "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / ", unless otherwise specified, generally indicates that the preceding and following related objects have an "or" relationship. Furthermore, it should be understood that in the description of this application, terms such as "first" and "second" are only used for distinguishing the descriptive purpose and should not be construed as indicating or implying relative importance, nor should they be construed as indicating or implying order. The invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only for explaining the invention and are not intended to limit the invention.

[0012] The distributed power balancing and voltage regulation method for a current-controlled converter cluster proposed in this invention includes the following steps: Please refer to Figure 1 A distributed power balancing and voltage regulation method for a current-controlled converter cluster includes: Figure 1 This invention relates to a distributed power balancing and voltage regulation method for current-controlled converter clusters applied to a microgrid (MG) parallel system. Multiple current-source grid-connected converters (CCGFM#1 to CCGFM#n) are connected via their respective LC filters. Z f,i With feeder impedance Z line The power supply (DG) is connected in parallel to the common coupling point (PCC). The PCC can be connected to resistive and nonlinear loads. Each DG employs local closed-loop control: it collects the voltage and current at the PoC point and calculates the output in the power calculation module. P e , Q e and power factor A phase reference is generated by the power factor droop in the four quadrants. θ Simultaneously, the voltage amplitude reference is provided by the reactive voltage droop. E ref Then, the fundamental current amplitude command is obtained through closed-loop regulation of the voltage amplitude squared, and... θ Synthetic fundamental current reference Then, through current loop control, the output currents of each DG are made to be in phase and frequency, with consistent amplitude, thus achieving parallel power balancing and bus voltage support. To address the harmonic problem caused by nonlinear loads, this invention introduces a local harmonic virtual impedance module to control harmonics at specific frequencies (…). h Voltage harmonics (=5, 7, 11, 13) are extracted and converted using equivalent virtual harmonic impedance to generate harmonic compensation current. i h After being synthesized with the fundamental reference, it is tracked by the inner current loop to achieve reduction of equivalent harmonic impedance, suppression of harmonic circulating current and improvement of power quality at the PCC point.

[0013] Please refer to Figure 2 A controller block diagram for a distributed power balancing and voltage regulation method for a current-controlled converter cluster, comprising: like Figure 2 As shown, the current-controlled converter (DG unit) of the present invention is composed of a power loop and a current inner loop, and includes: a power factor droop and reactive voltage droop module, a voltage amplitude control module, a limiter module, a harmonic extraction and harmonic virtual impedance module, a multi-resonant PR current inner loop module, and a modulation signal generation module.

[0014] The power loop is used to generate the amplitude and phase of the fundamental current reference, and the harmonic virtual impedance is used to generate the required harmonic compensation current. The two are combined to form the final current reference, which is then used to obtain a modulation signal through the PR current loop to drive the converter, enabling the parallel system to achieve power balance and port voltage regulation, while also suppressing harmonic circulating current and improving the power quality at the PCC point.

[0015] Step S201: Networking strategy for power droop control 1) Power Calculation and Filtering: The local controller collects the voltage and inductor current (or output current) at point PCC and transforms them to the αβ coordinate system. Instantaneous power is calculated and low-pass filtered to obtain the fundamental active and reactive components. Specifically, the power calculation formula in equation (1) is used to obtain: (1) 2) Four-quadrant power factor control to determine frequency: To keep the output current of the parallel converter in phase, this invention uses a four-quadrant power factor loop for frequency droop control. The phase is obtained by adjusting the angular velocity reference through power factor deviation and integrating, as shown in the following formula: (2) (3) in, ω 0 is the rated angular frequency, cos φ ref Given a value for the power factor, k φThis is the power factor droop coefficient. From the above formula, θ The phase reference, serving as the fundamental current vector, passes through [cos... θ sin θ The generation model enables each DG to automatically tend to operate in the same phase when connected in parallel.

[0016] 3) Reactive voltage droop control: To achieve voltage regulation and reactive power balance in parallel systems, a voltage amplitude reference is generated using the reactive voltage droop relationship. (4) in, V 0 represents the rated voltage amplitude. Q ref For reference only. k q This is the reactive power droop coefficient.

[0017] 4) Voltage amplitude control and fundamental current reference: Voltage amplitude control is achieved through a closed-loop voltage squared-loop control system. and As a voltage amplitude control command, the current amplitude command is obtained through PI regulation. I mag : (5) in, k pp , k pi This is a PI parameter for voltage amplitude control. To prevent the converter from overcurrent due to excessive total current when harmonic compensation current is present, a dynamic current amplitude limiter is set. (6) in, I max To allow the maximum current amplitude, I h To ensure that the amplitude of the equivalent harmonic current component to be injected does not exceed the protection threshold, the limiter ensures that the total current of "fundamental current + harmonic compensation current" does not exceed the protection threshold, thereby avoiding false tripping of the DG overcurrent protection.

[0018] Furthermore, the fundamental current reference is generated by the current amplitude. I With phase θ Synthetic fundamental current reference: (7)

[0019] Step S202: Harmonic Virtual Impedance Control

[0020] Each DG local controller acquires the local PoC voltage via a voltage sensor. By pre-setting a specified frequency harmonic hHarmonic extraction is performed on frequencies ∈{5,7,11,13}. The extraction formula for each harmonic frequency is shown below: (8) Based on the line harmonic impedance, the preset shunt matching target, and the virtual impedance parameters, construct the virtual harmonic impedance to be injected: (9) Combinatorial logic derives the equivalent harmonic virtual impedance from the relationship between preset harmonic impedance and harmonic line impedance, used to achieve specified harmonic sharing and circulating current suppression objectives. Subsequently, the extracted harmonic voltage is converted into harmonic current through the virtual impedance. Figure 2 Implementing the complex impedance division in the form of αβ decoupling, we obtain: (10) The harmonic compensation current reference is obtained by summing the harmonic currents of each frequency using the following formula, which reduces the harmonic output impedance amplitude of DG and suppresses the harmonic circulating current of the parallel system, thereby reducing the harmonic voltage distortion at PCC and improving power quality.

[0021] (11)

[0022] Step S203: Current inner loop control (reference synthesis, multi-resonant PR adjustment and modulation generation) The fundamental current reference generated by the power loop is subtracted from the harmonic compensation current reference to form the total current reference. This total current reference is then used to regulate the output voltage through the multi-resonant PR current control within the inner current loop. The PR controller is as follows: (12) in k p,v This is the proportionality coefficient. k i,h For the coefficients of each resonant branch, ω cut This is a bandwidth / damping related parameter. It can simultaneously guarantee high gain suppression and tracking capability at a specified harmonic frequency.

[0023] The PR controller output is transformed by αβ / abc coordinates and normalized with the DC bus voltage to generate a three-phase modulation signal m. abc It drives PWM and outputs the target current to achieve current in-phase and amplitude consistency of parallel DG, and has harmonic compensation capability.

[0024] Please refer to Figure 3 The equivalent circuit diagram of a distributed power balancing and voltage regulation method for a current-controlled converter cluster provided in this embodiment of the invention is shown below. Figure 3 This is the equivalent network for multiple distributed generation (DG) units connected in parallel to a common coupling point (PCC). Figure 3 (a) is the fundamental equivalent circuit: each DG is equivalent to an output current source. i o1 ~ i on With equivalent impedance Z eq1 ~ Z eqn Parallel connection, through feeder impedance Z line1 ~ Z linen The load impedance is connected to the PCC terminal. Z load The vector diagram within the dashed box illustrates the current synchronization / current sharing mechanism of this invention: Under given PCC terminal equivalent voltage and total impedance conditions, current synchronization control causes the output current vector of each DG to be synchronized. I 1. I 2… I n Maintaining phase consistency and superimposing in the same direction, they ultimately combine at the PCC to form the total load current. I load This enables current sharing and power balance in parallel systems. Figure 3 (b) Harmonic equivalent circuit: The nonlinear load is equivalent to a harmonic current source injected into the PCC. By superimposing adjustable harmonic virtual impedances at each DG port (corresponding to DG1~DGn respectively) and harmonic impedance of each DG branch line Together they constitute the equivalent harmonic impedance This enables the parallel system to exhibit the desired equivalent impedance characteristics in the harmonic frequency band, thereby suppressing harmonic circulating currents and improving power quality at the PCC.

[0025] Please refer to Figure 4 The root locus diagram of different control parameters of the current source converter provided in this embodiment of the invention. Figure 4 The root locus of the eigenvalues ​​(poles) of the established small-signal model during parameter variations is presented, which characterizes the influence of control parameters on system stability. The left figure shows the power factor droop coefficient. k The pole distribution is such that the poles are distributed in conjugate pairs on the complex plane, and as... k φ As the gain increases (in the direction indicated by the arrow), a pair of dominant complex poles move along an arc-shaped trajectory in the left half-plane. Their real and imaginary parts change synchronously, reflecting the adjustment of system damping and oscillation frequency as the droop gain changes. The right figure shows the parameters of the voltage amplitude control loop. k pp and k piPole migration under changing conditions: when k pp When the poles increase, they mainly move along the real axis, reflecting the impact on the system's equivalent damping and response speed; when k pi As the integral action increases, the poles expand towards the higher imaginary part and form a set of conjugate trajectories, reflecting the trend of increased oscillation characteristics and changes in stability margin after the integral action is enhanced. The dashed line in the figure represents the imaginary axis (the boundary where the real part is 0). All poles located to the left of the dashed line indicate system stability; when parameter adjustments cause the poles to approach the imaginary axis, it indicates a decrease in stability margin and may trigger oscillation risk. Furthermore, the operating points #1 to #4 marked in the figure correspond to... Figure 8 The four operating conditions in the text have their pole locations varying. k φ The increase gradually approaches the imaginary axis, especially at operating point #4 when the dominant pole is close to the stability boundary, thus aligning with... Figure 8 middle k φ This is consistent with the phenomenon of significant oscillations or even instability when the value is 30.

[0026] Please refer to Figure 5, which shows the system harmonic THD variation diagram provided in this embodiment of the invention. Figure 5 To evaluate the power quality improvement effect of parallel systems under the influence of harmonic virtual impedance, the following studies were conducted on the first... h The 5th, 7th, 11th, and 13th harmonics give the total harmonic distortion rate of the voltage at the PCC point as a function of the number of parallel DGs n and the equivalent harmonic impedance amplitude. Z eq The relationship between the changes is shown in the figure. Different surfaces in the figure reflect the changing trends of THD under different parameter combinations: when the number of parallel units and the equivalent harmonic impedance change, the THD at PCC exhibits obvious nonlinear fluctuations, with peak values ​​appearing in local areas, indicating that the system harmonic level is simultaneously affected by both the parallel scale and the degree of harmonic equivalent impedance matching. Overall, by adjusting... Z eq (Equivalent to changing the harmonic virtual impedance) By changing the harmonic impedance characteristics of each branch, the THD is suppressed to a lower level under different harmonic orders. Furthermore, as the number of parallel DGs increases, the harmonic shunt paths increase and the equivalent impedance adjustability is enhanced. The THD at the PCC remains near the target limit over a wider range, thus verifying the effectiveness of the proposed method in improving power quality in multiple harmonic frequency bands.

[0027] Please refer to Figure 6 The system power allocation diagram provided in this embodiment of the invention Figure 6 The reactive power distribution deviation characteristics of two parallel converters under reactive power-voltage droop control are presented, where the vertical axis represents the reactive power difference between the two converters. The horizontal axis is selected from the reactive power droop coefficient. k q And inconsistencies in line parameters. The left figure shows reactance difference. and k q As the independent variable, the surface shows: when there is a deviation in the line reactance from the two converters to the PCC, Will follow Significant changes are observed, manifested as a greater reactance mismatch leading to a more unbalanced reactive power distribution; simultaneously, the reactive power droop factor is altered. k q This will change the slope and overall horizontality of the surface, indicating... k q To a certain extent, this determines the sensitivity of the reactive power loop to line impedance differences and the magnitude of reactive power sharing errors.

[0028] The right figure shows the resistance difference. and k q As the independent variable, it reflects the influence of inconsistent line resistance on reactive power distribution deviation. It can be seen that... k q Under different values, Follow The same monotonic trend indicates that resistance mismatch affects the consistency of reactive power distribution through active / reactive coupling and voltage drop distribution; and when k q When the value is small, right Changes in reactive power are more sensitive, and large reactive power differentials are easily generated. Appropriately increasing... k q This allows the curved surface to be wider. Closer within range = The zero-plane design enhances the reactive power sharing capability and robustness of parallel converters.

[0029] Figure 7 This is a simulation diagram showing the effect of sudden load changes in the system, where two DG units are connected in parallel. t = 0.7s (dashed line) load change was applied to verify the dynamic power sharing, bus voltage regulation and circulating current suppression capabilities of the proposed control strategy. Figure 7 (a) and (b) respectively give the active power of the two inverters. P 1. P 2 and reactive power Q 1. Q2. Response curves: Before the sudden change, the two DGs stably supplied 10kW and 5kVar power to the load; when the load increased stepwise to 20kW and 10kVar, the active and reactive power of the two DGs rose rapidly and entered a new steady state after a short transition. The two curves remained very close, with only a small amplitude deviation, indicating that good dynamic power sharing and stable load sharing could still be achieved during the sudden increase in load.

[0030] Figure 7 Figures (c) and (d) show the voltage amplitude and angular frequency changes of the power loop output, and typical steady-state values ​​are marked in the figures. Figure 7 (c) As can be seen, before the load surge, the output voltage amplitudes of the two DGs were stable at approximately 290V (inverter #1) and 289V (inverter #2), respectively, with a slight difference between them. After the surge, the voltage amplitudes dropped and quickly converged to new steady-state values ​​of approximately 271V (inverter #1) and 269V (inverter #2), respectively. This difference corresponds to the different voltage drops caused by the inconsistent line impedances between the two DGs and the PCC. However, the overall voltage regulation process was smooth and without obvious continuous oscillations, demonstrating the adaptive adjustment capability of reactive power-voltage droop and voltage amplitude control to sudden load increases. Figure 7 (d) Display angular frequency ω Before the sudden change, the frequency remained near the rated value. After a brief shift when the load suddenly increased, it quickly converged to a new stable level. The frequency curves of the two DGs were basically the same and changed synchronously, indicating that the phase reference generated based on power factor droop / frequency regulation can maintain the frequency consistency of the parallel system during dynamic processes, thus providing synchronization conditions for "current in phase".

[0031] Figure 7 (e) gives the parallel circulating current. i oo The waveform. It can be seen that, both before and after the load mutation, i oo All values ​​fluctuated slightly and randomly around zero, with consistently small amplitudes that did not significantly amplify due to load steps. This indicates that the proposed method can effectively suppress parallel circulating currents caused by inconsistent line impedances and control differences, thus avoiding ineffective power exchange and overcurrent risks between DGs. Figure 7 (f) Further, the time-domain waveforms of the phase a voltage and current of the two inverters are given: Due to the inconsistent line impedance, there is an observable difference in the amplitude of the voltage at the ports of the two DGs; however, the output currents of the two DGs remain approximately in phase and frequency before and after the abrupt change, and in... t = After 0.7s, the current amplitude increased significantly with the increase of load, indicating that even with voltage differences, the current reference synthesis and phase synchronization mechanism can still ensure that the parallel system operates in the "current source type in-phase parallel" manner, realizing the effective superposition and sharing of load current.

[0032] like Figure 8 As shown, this is to verify the effect of load mutation and power factor droop coefficient on two parallel inverters. k φ The dynamic response and stability of the system under different values t A load step change occurs at 0.2s (shown by the dashed line "Load Sudden Change" in the figure), with the load abruptly changing from 10kW, 5kVar to 20kW, 20kVar. The figure shows the waveforms of the angular frequency, voltage amplitude, active and reactive power of the two inverters (DG1 and DG2) from top to bottom; the entire process is divided into four segments by vertical dashed lines, corresponding to... k φ1 = k φ2 =1、 k φ1 = k φ2 =5、 k φ1 = k φ2 =10 and k φ1 = k φ2 =30. After a sudden load change, the active and reactive power outputs of both inverters rose rapidly and stabilized near the new steady state, indicating that the system has the ability to track load steps; k φ When the values ​​are 1, 5, and 10, the frequency at the PCC point remains basically near the rated value with only a small ripple, and the voltage also remains stable. The active and reactive power sharing curves of the two machines are closely matched, indicating that the parallel current synchronization and power balance are effective. k φ Increasing the gain further to 30 leads to a significant deterioration in system stability: the PCC frequency rises and exhibits large swings; the PCC voltage amplitude drops sharply before stabilizing near zero; simultaneously, significant pulsations and imbalances in active and reactive power distribution occur, indicating that excessive power factor droop gain introduces strong coupled oscillations and reduces stability margin. The output current of phase a is further given. i a1 , i a2 The local waveform shows that before instability, the currents of the two machines are approximately the same amplitude, demonstrating good synchronous current sharing; however, after instability, the phases of the currents of the two machines begin to separate and the deviation gradually increases, thus destroying the synchronization characteristics.

[0033] Figure 9 To verify the power quality improvement effect of the proposed harmonic suppression strategy after the addition of nonlinear loads, the three-phase current at the PCC point is compared. i pcc Three-phase voltage vpcc The time-domain waveform and spectrum analysis results are shown, with the left side showing the waveform before harmonic suppression and the right side showing the waveform after harmonic suppression. As seen on the left, under the action of a nonlinear load, both the current and voltage waveforms at the PCC point exhibit significant distortion, deviating from the ideal sine wave. In the spectrum, besides the fundamental wave, low-order harmonic components such as the 5th and 7th harmonics are prominent, corresponding to a THD of 8.87%. The harmonic current introduced by the nonlinear load generates harmonic voltage drops across the system impedance, leading to PCC voltage distortion. As seen on the right, after enabling harmonic suppression using virtual impedance / multiresonance control, the current and voltage waveforms at the PCC point recover to approximately sinusoidal, with a significant reduction in distortion. The peak values ​​of major harmonics such as the 5th and 7th harmonics in the spectrum are significantly suppressed, resulting in a substantial decrease in overall harmonic content and a THD reduction to 2.67%. The comparative results demonstrate that the harmonic suppression method described in this invention can effectively weaken the characteristic harmonic components caused by nonlinear loads, significantly improving the waveform quality of the voltage and current at the PCC and the system power quality level.

[0034] This invention is not limited to the embodiments described above. The above description of specific embodiments is intended to illustrate and explain the technical solutions of this invention. The specific embodiments described above are merely illustrative and not restrictive. Without departing from the spirit and scope of the claims, those skilled in the art can make many specific modifications based on the teachings of this invention, and these modifications all fall within the scope of protection of this invention.

[0035] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0036] Example module Figure 10 As shown, a schematic diagram of an embodiment of a distributed power balancing and voltage regulation method for a current-controlled converter cluster is presented, including: Sampling module 1001 measures the voltage at each DG local PoC point based on voltage and current sensors. v PoC,abc and filter inductor current i L,abc The sampled signal is then sent to the local controller as input for power calculation, voltage amplitude calculation, and current closed-loop control.

[0037] The power calculation module 1002 is used to perform coordinate transformation and fundamental frequency extraction on the sampled signal: v PoC,abc , i L,abc Transform to αβ coordinates to obtain , The active / reactive power is calculated, and the power factor cosφ is obtained. After filtering, the result is... P e , Q e and the square of voltage amplitude V 2 Feedback volume, etc.

[0038] The harmonic extraction module 1003 extracts voltage / current harmonic components based on the sampled signal and targets the preset harmonic order, forming the harmonic information required for harmonic compensation and outputting it to the power control module.

[0039] The power control module 1004, based on fundamental power feedback and harmonic information, performs power factor droop to generate a frequency reference and reactive power-voltage droop to generate a voltage amplitude reference. It also obtains the fundamental current amplitude command through a voltage amplitude squared closed loop and superimposes the harmonic compensation current to form a total current reference.

[0040] The voltage modulation ratio generation module 1005 performs inner-loop current regulation using the total current reference and current feedback, outputs the voltage command required for modulation, and normalizes it in combination with the DC bus voltage to generate the modulation ratio of the inverter, thereby realizing power balancing, voltage regulation, and harmonic suppression for nonlinear loads in parallel DG.

[0041] The distributed power balancing and voltage regulation method module for a current-controlled converter cluster may include, but is not limited to, a parallel inverter circuit 1101, a controller 1102, and a memory 1103. The parallel inverter circuit 1101 consists of at least two inverter circuits (such as inverter circuit #1 and inverter circuit #2), each operating in parallel under the drive of the controller 1102 and supplying power to the PCC point. The sampling circuit is used to collect key electrical quantities of each inverter circuit in real time (including but not limited to PoC / PCC voltage, inductor current / output current, etc.), and sends the sampled signals to the analog-to-digital conversion module for digital processing before inputting them into the controller 1102.

[0042] The controller 1102 can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. It includes sub-control units (such as controller #1 and controller #2) corresponding to each inverter circuit, which execute the power calculation, power factor / reactive power droop, voltage amplitude control, harmonic compensation, and current inner-loop control algorithms of this invention based on the sampled signals, and output the modulation / drive signals required by their respective inverter circuits to achieve power balance and voltage regulation in the parallel system.

[0043] The memory 1103 can be an internal storage unit of the parallel converter device, or an external storage circuit of the parallel converter device. Examples include plug-in hard drives, SmartMediaCards (SMCs), Secure Digital (SD) cards, and FlashCards equipped on the converter device. Furthermore, the memory 1103 can include both internal storage units of the converter device and external storage devices. It stores a computer program 1104 and the data parameters required for its operation. The controller 1102 reads and executes the computer program 1104 to complete the aforementioned control functions.

[0044] Those skilled in the art will understand that Figure 11 This is merely a schematic diagram of the device structure. The actual device may have additional or fewer components added or removed according to engineering needs, or the sampling, conversion and control units may be integrated or separated without affecting the implementation of the technical solution of this invention.

[0045] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0046] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0047] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0048] In the embodiments provided by this invention, it should be understood that the disclosed apparatus / terminal devices and methods can be implemented in other ways. For example, the method / terminal device embodiments described above are merely illustrative. For instance, the division of the controller or modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, or indirect coupling or communication connection between devices or units, and may be electrical, mechanical, or other forms.

[0049] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some units can be selected to achieve the purpose of this embodiment according to actual needs.

[0050] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0051] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0052] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A distributed power balancing and voltage regulation method for a current-controlled converter cluster, characterized in that, include: Distributed generation (DG), inverter circuit module, filter circuit, harmonic extraction module, linear and nonlinear loads, local controllers for each DG, current sensor, voltage sensor; The current source grid-connected control strategy is applied to a microgrid (MG) parallel system, where multiple current source grid-connected converters (CCGFM#1 to CCGFM#n) are connected via their respective LC filters. Z f,i With feeder impedance Z line The loads are connected in parallel to the common coupling point (PCC), which can accommodate both linear and nonlinear loads. Each DG employs local closed-loop control: it collects voltage and current at the PoC point and calculates them in the power calculation module. P e , Q e and power factor A phase reference is generated through four-quadrant power factor droop control. θ Simultaneously, the voltage amplitude reference is provided by the reactive voltage droop. E ref Then, the fundamental current amplitude command is obtained through closed-loop regulation of the voltage amplitude squared, and... θ Synthetic fundamental current reference Then, through current loop control, the output currents of each DG are made to be in phase and frequency, with consistent amplitude, thus achieving parallel power balancing and bus voltage support. To address harmonic issues caused by nonlinear loads, this invention introduces a local harmonic virtual impedance module to control harmonics at specific frequencies (…). h Voltage harmonics (=5, 7, 11, 13) are extracted and converted into harmonic compensation currents through equivalent virtual harmonic impedance. i h After being synthesized with the fundamental reference, it is tracked by the inner current loop to achieve reduction of equivalent harmonic impedance, suppression of harmonic circulating current and improvement of power quality at the PCC point.

2. A control system structure used in a distributed power balancing and voltage regulation method for a current-controlled converter cluster, characterized in that: Includes the following steps: Step 1, Networking strategy for power droop control. Power calculation and filtering: The local controller collects the voltage and inductor current at the PCC point and transforms them to the αβ coordinate system. The instantaneous power is calculated and the fundamental active and reactive components are obtained through low-pass filtering. Specifically, the power calculation formula in equation (1) is used to obtain: (1) Four-quadrant power factor control determines the frequency: To keep the output current of the parallel converter in phase, this invention uses a four-quadrant power factor loop for frequency droop control. The phase is obtained by adjusting the angular velocity reference through power factor deviation and integrating. The power factor droop coefficient is then determined by the sign function. Sgn ( Q e Update as shown in the following formula: (2) (3) in, ω 0 is the rated angular frequency, cos φ ref Given a value for the power factor, k φ This is the power factor droop coefficient. From the above formula, θ The phase reference, serving as the fundamental current vector, passes through [cos... θ sin θ The generation model enables each DG to automatically tend to operate in the same phase when connected in parallel; Reactive voltage droop control: To achieve voltage regulation and reactive power balance in parallel systems, a voltage amplitude reference is generated using the reactive voltage droop relationship. (4) in, V 0 represents the rated voltage amplitude. Q ref For reference only. k q This is the reactive power droop coefficient; Voltage amplitude control and fundamental current reference: Voltage amplitude control is achieved through a closed-loop voltage squared method. and As a voltage amplitude control command, the current amplitude command is obtained through PI regulation. I mag : (5) in, k pp , k pi This is a PI parameter for voltage amplitude control. To prevent the converter from overcurrent due to excessive total current when harmonic compensation current is present, a dynamic current amplitude limiter is set. (6) in, I max To allow the maximum current amplitude, I h To ensure that the amplitude of the equivalent harmonic current component to be injected does not exceed the protection threshold, the limiter ensures that the total current of "fundamental current + harmonic compensation current" does not exceed the protection threshold, thereby avoiding false tripping of the DG overcurrent protection. Furthermore, the fundamental current reference is generated by the current amplitude. I With phase θ Synthetic fundamental current reference: (7) Step 2: Harmonic Virtual Impedance Control. Each DG local controller acquires the local PoC voltage via a voltage sensor. By pre-setting a specified frequency harmonic h Harmonic extraction is performed on frequencies ∈{5,7,11,13}. The extraction formula for each harmonic frequency is shown below: (8) Based on the line harmonic impedance, the preset shunt matching target, and the virtual impedance parameters, construct the virtual harmonic impedance to be injected: (9) Combinatorial logic for obtaining equivalent harmonic virtual impedance from the relationship between preset harmonic impedance and harmonic line impedance is used to achieve specified harmonic sharing and circulating current suppression objectives. Subsequently, the extracted harmonic voltage is converted into harmonic current through virtual impedance (Figure 2 shows complex impedance division implemented in an αβ decoupling form), resulting in: (10) The harmonic compensation current reference is obtained by summing the harmonic currents of each frequency using the following formula, which reduces the harmonic output impedance amplitude of DG and suppresses the harmonic circulating current of the parallel system, thereby reducing the harmonic voltage distortion at PCC and improving power quality. (11) Step 3: Current Inner Loop Control (Reference Synthesis, Multi-Resonant PR Adjustment). The fundamental current reference generated by the power loop is subtracted from the harmonic compensation current reference to form the total current reference. This total current reference is then adjusted by the multi-resonant PR current control within the current inner loop. The PR controller is as follows: (12) in k p,v This is the proportionality coefficient. k i,h For the coefficients of each resonant branch, ω cut These are bandwidth / damping related parameters. They can simultaneously guarantee high gain suppression and tracking capability at specified harmonic frequencies, while also ensuring fundamental frequency tracking. The PR controller output is transformed by αβ / abc coordinates and normalized with the DC bus voltage to generate a three-phase modulation signal m. abc It drives PWM and outputs the target current to achieve current in-phase and amplitude consistency of parallel DG, and has harmonic compensation capability.

Images