Epitaxial structure, manufacturing method thereof, light emitting chip and display panel
By dividing the quantum barrier layer into three segments and performing N-type doping in the epitaxial structure, the problem of reduced carrier recombination efficiency in quaternary red Micro LEDs after size reduction was solved, thus improving the luminous brightness.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHONGQING KONKA PHOTOELECTRIC TECH RES INST CO LTD
- Filing Date
- 2024-11-28
- Publication Date
- 2026-05-29
AI Technical Summary
As the size of quaternary red Micro LEDs decreases, the recombination efficiency of charge carriers in the active layer light-emitting region decreases, leading to brightness issues.
In the epitaxial structure, the quantum barrier layer is divided into three segments, with N-type doping only in the middle segment to form the first sub-barrier layer, the second sub-barrier layer with N-type doping, and the third sub-barrier layer, thereby increasing the number of charge carriers and improving recombination efficiency.
The luminescence brightness was enhanced by improving the recombination efficiency of charge carriers in the active layer.
Smart Images
Figure CN122121350A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of LED chip technology, and in particular to an epitaxial structure and its fabrication method, a light-emitting chip, and a display panel. Background Technology
[0002] Micro LED, as an emerging display technology, reduces the size from millimeters to micro-nano scale compared to traditional LEDs. When integrated into high-density, small-sized arrays and applied in the display field, it has advantages such as high brightness, high resolution, high contrast, low energy consumption, and long lifespan. It also has excellent performance in response speed and thermal stability.
[0003] However, a major challenge facing existing quaternary red light is its brightness. Because the size effect of quaternary red light is particularly pronounced, the luminous efficiency decreases sharply as the size decreases, meaning that the recombination efficiency of charge carriers in the active layer light-emitting region decreases. Summary of the Invention
[0004] In view of the shortcomings of the prior art, the purpose of this application is to provide an epitaxial structure and its fabrication method, a light-emitting chip and a display panel, which aims to improve the efficiency of carrier recombination in the active layer light-emitting region.
[0005] In a first aspect, this application provides a method for fabricating an epitaxial structure, comprising: providing a substrate and growing an N-type semiconductor layer on the substrate;
[0006] A multi-quantum-well structure on the N-type semiconductor layer, the multi-quantum-well structure comprising periodically alternating quantum well layers and quantum barrier layers, the quantum barrier layer comprising a first sub-barrier layer, a second sub-barrier layer with N-type doping and a third sub-barrier layer;
[0007] A P-type semiconductor layer is formed on the side of the multi-quantum well structure facing away from the substrate.
[0008] In one possible embodiment, the doping concentration of the second sub-barrier layer is 6E17 to 1E18 / cm3.
[0009] In one possible embodiment, the thickness of the second sub-barrier layer is 2–4 nm.
[0010] In one possible embodiment, the first sub-barrier layer has the same thickness as the third sub-barrier layer.
[0011] In one possible embodiment, the thickness of the first sub-barrier layer or the third sub-barrier layer is less than the thickness of the second sub-barrier layer.
[0012] In one possible embodiment, the first sub-barrier layer and the third sub-barrier layer are undoped layers.
[0013] In one possible embodiment, the thickness of the first sub-barrier layer or the third sub-barrier layer is 1.5 to 3.5 nm.
[0014] Secondly, this application provides an extensional structure, including:
[0015] Substrate, and an N-type semiconductor layer disposed on the substrate;
[0016] A multi-quantum-well structure is disposed on the N-type semiconductor layer; wherein the multi-quantum-well structure includes periodically alternating quantum well layers and quantum barrier layers, and the quantum barrier layer includes a first sub-barrier layer, a second sub-barrier layer with N-type doping, and a third sub-barrier layer;
[0017] A P-type semiconductor layer is disposed on the side of the multi-quantum well structure facing away from the substrate.
[0018] In one possible embodiment, the doping concentration of the second sub-barrier layer is 6E17 to 1E18 / cm3.
[0019] In one possible embodiment, the thickness of the bisublayer is 2–4 nm.
[0020] In one possible embodiment, the thickness of the first sub-barrier layer or the third sub-barrier layer is less than the thickness of the second sub-barrier layer.
[0021] Thirdly, this application also provides a light-emitting chip, comprising:
[0022] The first electrode, the second electrode, and the epitaxial structure as described in any of the second aspects, wherein the first electrode is electrically connected to the N-type semiconductor layer and the second electrode is electrically connected to the P-type semiconductor layer.
[0023] Fourthly, this application also provides a display panel, comprising:
[0024] The driving substrate and a plurality of light-emitting chips as described in the third aspect, wherein the plurality of light-emitting chips are disposed on the driving substrate and electrically connected to the driving substrate, and the driving substrate is used to transmit electrical signals to the plurality of light-emitting chips to control the plurality of light-emitting chips to emit light.
[0025] Beneficial effects:
[0026] The epitaxial structure, fabrication method, light-emitting chip, and display panel provided in this application involve growing an N-type semiconductor layer on a substrate, then constructing a multi-quantum well structure on the N-type semiconductor layer. The multi-quantum well structure includes periodically alternating quantum well layers and quantum barrier layers. The quantum barrier layer includes a first sub-barrier layer, a second sub-barrier layer with N-type doping, and a third sub-barrier layer. Finally, a P-type semiconductor layer is formed on the side of the multi-quantum well structure facing away from the substrate. By dividing the barrier layer into three segments and performing N-type doping only in the middle segment of the barrier layer, the number of charge carriers is increased, providing more charge carriers for recombination in the active layer light-emitting region, thereby improving recombination efficiency and increasing luminous brightness. Attached Figure Description
[0027] Figure 1 This is a schematic diagram of a method for fabricating an epitaxial structure provided in an embodiment of this application;
[0028] Figure 2 for Figure 1 A schematic diagram of the structure after growing an N-type semiconductor layer in an epitaxial structure fabrication method is shown.
[0029] Figure 3 for Figure 1 A schematic diagram of the structure after deposition of a multi-quantum-well structure in an epitaxial structure fabrication method is shown.
[0030] Figure 4 for Figure 3 The diagram shows the structure of the multi-quantum-well structure.
[0031] Figure 5 for Figure 1 A schematic diagram of the structure after growing a P-type semiconductor layer in the epitaxial structure fabrication method shown;
[0032] Figure 6 This is a schematic diagram of an epitaxial structure provided in an embodiment of this application;
[0033] Figure 7 for Figure 6 The diagram shows the physical structure of the multi-quantum-well structure in the epitaxial structure.
[0034] Explanation of reference numerals in the attached figures:
[0035] 1-Substrate; 2-Buffer layer; 3-Etching cutoff layer; 4-Ohmic contact layer; 5-N-type current spreading layer; 6-N-type confinement layer; 7-Multiple quantum well structure; 71-Quantum well layer; 73-Quantum barrier layer; 731-First sub-barrier layer; 733-Second sub-barrier layer; 736-Third sub-barrier layer; 8-P-type confinement layer; 9-P-type window layer. Detailed Implementation
[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.
[0037] This invention discloses many different embodiments or examples for implementing different structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described herein. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.
[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Generally, terms can be understood at least in part according to their usage in accordance with the invention. For example, the term "one or more" as used herein, depending at least in part on the invention, can be used to describe any component, structure, or feature in the singular or in the plural form to describe a combination of components, structures, or features. Similarly, terms such as "a," "an," or "the" can also be understood, depending at least in part on the invention, to convey either a singular or a plural usage. Furthermore, the term "based on..." can be understood not necessarily to convey an exclusive set of factors, but rather, depending at least in part on the invention, can alternatively allow for additional factors that do not necessarily have to be explicitly described.
[0039] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this invention should be interpreted in the broadest sense, such that “on” means not only “directly on something,” but also “on something” including the presence of an intermediate component or layer between the two, and “on something” or “above something” means not only “on something” or “above something,” but also “on something” or “above something” where no intermediate component or layer between the two exists.
[0040] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used in this invention to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways, rotated 90°, or otherwise oriented, and the spatial relative descriptive terms used in this invention can be interpreted accordingly.
[0041] As used in this invention, the term "layer" refers to a portion of material comprising a region of a certain thickness. A layer may extend over the entire lower or upper layer structure, or may have a extent smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A single layer may include multiple layers. For example, a semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.
[0042] refer to Figure 1 This is a schematic flowchart of an epitaxial structure fabrication method provided in an embodiment of this application. The method includes:
[0043] 101: Provide a substrate on which an N-type semiconductor layer is grown.
[0044] In the embodiments of this application, the substrate is a GaAs substrate.
[0045] Optionally, the N-type semiconductor layer includes a buffer layer, an etching stop layer, an ohmic contact layer, an N-type current spreading layer, and an N-type confinement layer.
[0046] As one implementation method, for example, such as Figure 2 As shown, a buffer layer 2, an etching stop layer 3, an ohmic contact layer 4, an N-type current spreading layer 5, and an N-type confinement layer 6 are sequentially grown on a GaAs substrate 1.
[0047] 102: A multi-quantum-well structure on the N-type semiconductor layer.
[0048] The aforementioned multi-quantum-well structure includes periodically alternating quantum well layers and quantum barrier layers, wherein the quantum barrier layer includes a first sub-barrier layer, a second sub-barrier layer with N-type doping, and a third sub-barrier layer.
[0049] Optionally, in this embodiment, the epitaxial structure is AlGaInP based.
[0050] Optionally, the cycle time is 2-8. That is, the number of cycles of the superlattice of the active layer (quantum well layer and quantum barrier layer) is between 2 and 8. The specific cycle time can be adjusted according to different operating currents and chip sizes to grow the multi-quantum well structure. No specific limitation is made here.
[0051] Optionally, the doping concentration of the second sub-barrier layer is 6E17 to 1E18 / cm3, and the doping element is silicon (silyl silane).
[0052] Optionally, the thickness of the second sub-barrier layer is 2–4 nm.
[0053] Optionally, the first sub-barrier layer and the third sub-barrier layer have the same thickness.
[0054] Optionally, the thickness of the first sub-barrier layer or the third sub-barrier layer is less than the thickness of the second sub-barrier layer.
[0055] Optionally, the first sub-barrier layer and the third sub-barrier layer are undoped layers.
[0056] Optionally, the thickness of the first sub-barrier layer or the third sub-barrier layer is 1.5 to 3.5 nm.
[0057] For example, when the thickness of the first sub-barrier layer and the third sub-barrier layer is 2nm, the thickness of the second sub-barrier layer must be greater than 2nm, which can be 2.5nm, 3nm, or 4nm.
[0058] Optionally, the thickness of the quantum well layer is 3.5-6 nm, and the In composition of the light-emitting layer is 0.5 to maintain lattice matching.
[0059] In other words, the materials of the first sub-barrier layer, the second sub-barrier layer, and the third sub-barrier layer are (Al). x Ga (1-x) ) 0.5 In 0.5 P.
[0060] Optionally, x is 0.7.
[0061] It should be noted that the multi-quantum-well structure in this application begins and ends with a well layer.
[0062] For example, such as Figure 3 and Figure 4As shown, an MQW (active layer) is first deposited on the N-type confinement layer 6. The main process conditions are: a set temperature of 650-670℃, a chamber pressure of 50 mbar, phosphine as a group V source, hydrogen as a carrier gas, and a certain amount of trimethylaluminum, trimethylgallium, and trimethylindium as group III sources. The deposition time is controlled. A quantum well layer 71 is first grown with a thickness of 3.5-6 nm. Then, a quantum barrier layer 73 is grown, which is further divided into three sub-layers: the first sub-barrier layer 731, the second sub-barrier layer 733, and the third sub-barrier layer 736. The amount of trimethylaluminum introduced is controlled so that the aluminum composition in the material is 0.7, that is, x in (AlxGa1-x)InP is 0.7. Then, the quantum well layer 71 and the quantum barrier layer 73 are grown cyclically 2-8 times, and finally, another quantum well layer 71 is grown.
[0063] It should be noted that when the number of quantum well pairs exceeds 10, the total thickness may become too thick, which may negatively impact the final chip performance, resulting in increased bulk resistance and reduced brightness.
[0064] In one possible embodiment, the thickness of the quantum well layer 71 is less than the thickness of the quantum barrier layer 73, that is, the thickness of the quantum well layer 71 is less than the sum of the thicknesses of the first sub-barrier layer 731, the second sub-barrier layer 733, and the third sub-barrier layer 736.
[0065] 103: A P-type semiconductor layer is formed on the side of the multi-quantum well structure facing away from the substrate.
[0066] Optionally, the P-type semiconductor layer includes a P-type confinement layer and a P-type window layer.
[0067] For example, such as Figure 5 As shown, in Figure 4 Based on this, a P-type confinement layer 8 and a P-type window layer 9 are sequentially grown on the last quantum well layer 71 of the multi-quantum well structure 7.
[0068] In summary, in this embodiment, without changing the structure of the quantum well layer, the quantum barrier layer is divided into a first sub-barrier layer, a second sub-barrier layer with N-type doping, and a third sub-barrier layer. This allows N-type doping to be performed only on the middle section of the barrier layer, thereby increasing the number of charge carriers and providing more charge carriers for recombination in the active layer's light-emitting region, thus improving recombination efficiency and increasing luminous brightness.
[0069] refer to Figure 6Based on the same inventive concept, this application also provides an epitaxial structure, comprising: a substrate 1; an N-type semiconductor layer disposed on the substrate 1; a multiple quantum well structure 7 disposed on the N-type semiconductor layer; wherein the multiple quantum well structure 7 includes periodically alternating quantum well layers 71 and quantum barrier layers 73, the quantum barrier layer 73 including a first sub-barrier layer 731, a second sub-barrier layer 733 having N-type doping, and a third sub-barrier layer 736; and a P-type semiconductor layer disposed on the side of the multiple quantum well structure 7 facing away from the substrate 1.
[0070] In this embodiment, the substrate 1 is a GaAs substrate, and the N-type semiconductor layer may include a buffer layer 2, an etching stop layer 3, an ohmic contact layer 4, an N-type current spreading layer 5, and an N-type confinement layer 6.
[0071] Optionally, the material of the corrosion stop layer 3 can be GaInP.
[0072] Optionally, the ohmic contact layer 4 can be made of n-type GaAs.
[0073] Optionally, in this embodiment, the epitaxial structure is AlGaInP based.
[0074] Optionally, the alternation period between the quantum well layer 71 and the quantum barrier layer 73 is 2-8 times. That is, the number of cycles of the superlattice of the active layer (quantum well layer and quantum barrier layer) is between 2 and 8. The specific period can be adjusted according to different operating currents and chip sizes to increase the number of cycles in the growth of the multi-quantum well structure. No specific limitation is made here.
[0075] It should be noted that the multi-quantum-well structure 7 in this application begins and ends with quantum well layer 71, and its specific structure is as follows: Figure 7 As shown.
[0076] It should be noted that when the number of quantum well pairs exceeds 10, the total thickness may become too thick, which may negatively impact the final chip performance, resulting in increased bulk resistance and reduced brightness.
[0077] Optionally, the doping concentration of the second sub-barrier layer 733 is 6E17 to 1E18 / cm3, and the doping element is silicon (silyl silane).
[0078] It is understandable that by doping the center of the barrier layer, the number of charge carriers in the quantum well can be increased, thereby increasing the speed of movement under low current conditions and raising the luminous brightness.
[0079] Optionally, the thickness of the second sub-barrier layer 733 is 2 to 4 nm.
[0080] Optionally, the first sub-barrier layer 731 and the third sub-barrier layer 736 have the same thickness.
[0081] Optionally, the thickness of the first sub-barrier layer 731 or the third sub-barrier layer 736 is less than the thickness of the second sub-barrier layer 733.
[0082] Optionally, the first sub-barrier layer 731 and the third sub-barrier layer 736 are undoped layers, that is, the first sub-barrier layer 731 and the third sub-barrier layer 736 are not doped.
[0083] Optionally, the thickness of the first sub-barrier layer 731 or the third sub-barrier layer 736 is 1.5 to 3.5 nm.
[0084] For example, when the thickness of the first sub-barrier layer 731 and the third sub-barrier layer 736 is 2nm, the thickness of the second sub-barrier layer 733 must be greater than 2nm, and can be 2.5nm, 3nm, or 4nm.
[0085] Optionally, the thickness of the quantum well layer 71 is 3.5-6 nm. To maintain lattice matching, the In composition of the light-emitting layer is 0.5, that is, the indium content of the quantum barrier layer 73 is 0.5.
[0086] In other words, the materials of the first sub-barrier layer 731, the second sub-barrier layer 733, and the third sub-barrier layer 736 are (Al) x Ga (1-x) ) 0.5 In 0.5 P.
[0087] Optionally, x is 0.7.
[0088] In one possible embodiment, the thickness of the quantum well layer 71 is less than the thickness of the quantum barrier layer 73, that is, the thickness of the quantum well layer 71 is less than the sum of the thicknesses of the first sub-barrier layer 731, the second sub-barrier layer 733, and the third sub-barrier layer 736.
[0089] Optionally, the P-type semiconductor layer includes: a P-type confinement layer 8 and a P-type window layer 9.
[0090] Among them, the P-type confinement layer 8 is disposed on the last quantum well layer 71 of the multi-quantum well structure 7, and the P-type window layer 9 is disposed on the P-type confinement layer 8.
[0091] Optionally, the material of the P-type window layer 9 can be GaP.
[0092] Optionally, the material of the P-type confinement layer 8 can be P-type AlGaInP.
[0093] Based on the same inventive concept, this application also provides a light-emitting chip, including: a first electrode, a second electrode, and an epitaxial structure as described in the above embodiments, wherein the first electrode is electrically connected to the N-type semiconductor layer, and the second electrode is electrically connected to the P-type semiconductor layer.
[0094] Optionally, the first electrode is an N-type metal electrode and the second electrode is a P-type metal electrode.
[0095] Based on the same inventive concept, this application also provides a display panel, including: a driving substrate and a plurality of light-emitting chips as described above, wherein the plurality of light-emitting chips are disposed on the driving substrate and electrically connected to the driving substrate, and the driving substrate is used to transmit electrical signals to the plurality of light-emitting chips to control the plurality of light-emitting chips to emit light.
[0096] In summary, the epitaxial structure, fabrication method, light-emitting chip, and display panel provided in this embodiment grow an N-type semiconductor layer on the substrate, then construct a multi-quantum well structure on the N-type semiconductor layer. The multi-quantum well structure includes periodically alternating quantum well layers and quantum barrier layers. The quantum barrier layer includes a first sub-barrier layer, a second sub-barrier layer with N-type doping, and a third sub-barrier layer. Finally, a P-type semiconductor layer is formed on the side of the multi-quantum well structure facing away from the substrate. By dividing the barrier layer into three segments and performing N-type doping only in the middle segment of the barrier layer, the number of charge carriers is increased, providing more charge carriers for recombination in the active layer light-emitting region, thereby improving recombination efficiency and increasing luminous brightness.
[0097] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.
Claims
1. A method for fabricating an epitaxial structure, characterized in that, include: A substrate is provided on which an N-type semiconductor layer is grown; A multi-quantum-well structure on the N-type semiconductor layer, the multi-quantum-well structure comprising periodically alternating quantum well layers and quantum barrier layers, the quantum barrier layer comprising a first sub-barrier layer, a second sub-barrier layer with N-type doping and a third sub-barrier layer; A P-type semiconductor layer is formed on the side of the multi-quantum well structure facing away from the substrate.
2. The method for fabricating an epitaxial structure as described in claim 1, characterized in that, The doping concentration of the second sub-barrier layer is 6E17 to 1E18 / cm3.
3. The method for fabricating an epitaxial structure as described in claim 2, characterized in that, The thickness of the second sub-barrier layer is 2–4 nm.
4. The method for fabricating an epitaxial structure as described in claim 2, characterized in that, The first sub-barrier layer has the same thickness as the third sub-barrier layer.
5. The method for fabricating an epitaxial structure as described in claim 4, characterized in that, The thickness of the first sub-barrier layer or the third sub-barrier layer is less than the thickness of the second sub-barrier layer.
6. The method for fabricating an epitaxial structure as described in claim 4 or 5, characterized in that, The first sub-barrier layer and the third sub-barrier layer are undoped layers.
7. The method for fabricating an epitaxial structure as described in claim 6, characterized in that, The thickness of the first sub-barrier layer or the third sub-barrier layer is 1.5 to 3.5 nm.
8. An epitaxial structure, characterized in that, include: Substrate, and an N-type semiconductor layer disposed on the substrate; A multi-quantum-well structure is disposed on the N-type semiconductor layer; wherein the multi-quantum-well structure includes periodically alternating quantum well layers and quantum barrier layers, and the quantum barrier layer includes a first sub-barrier layer, a second sub-barrier layer with N-type doping, and a third sub-barrier layer; A P-type semiconductor layer is disposed on the side of the multi-quantum well structure facing away from the substrate.
9. The epitaxial structure as described in claim 8, characterized in that, The doping concentration of the second sub-barrier layer is 6E17 to 1E18 / cm3.
10. The epitaxial structure as described in claim 8, characterized in that, The thickness of the two-sub-barrier layer is 2–4 nm.
11. The epitaxial structure as described in claim 8, characterized in that, The thickness of the first sub-barrier layer or the third sub-barrier layer is less than the thickness of the second sub-barrier layer.
12. A light-emitting chip, characterized in that, include: The first electrode, the second electrode, and the epitaxial structure as described in any one of claims 7-11, wherein the first electrode is electrically connected to the N-type semiconductor layer, and the second electrode is electrically connected to the P-type semiconductor layer.
13. A display panel, characterized in that, include: The driving substrate and a plurality of light-emitting chips as described in claim 12, wherein the plurality of light-emitting chips are disposed on the driving substrate and electrically connected to the driving substrate, and the driving substrate is used to transmit electrical signals to the plurality of light-emitting chips to control the plurality of light-emitting chips to emit light.