Semiconductor structure and method of forming the same

Abstract

The application provides a semiconductor structure and a forming method thereof, wherein a first through silicon via structure is formed through two processes of front side processing and back side processing, and a second through silicon via structure is formed through one process of front side processing; since the first through silicon via structure is formed through two processes, the critical dimension and the depth adjustment range of the first through silicon via structure are large, so that the first through silicon via structure can be designed to have a small critical dimension, and the critical dimension is reduced; in addition, the first through silicon via structure and the second through silicon via structure are connected with back-end metal interconnections located on different planes, so that the process window of the back-end metal wiring is increased.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] The formation process of a logic product includes the following steps:

[0003] like Figure 1 As shown, a contact hole structure 11 is formed in the substrate, which is a substrate that has already undergone the front-end process. Figure 1 In this context, "Cell" refers to a device formed through front-end manufacturing processes.

[0004] like Figure 2 As shown, a through-silicon via (TSV) is formed using a photolithography process, and the TSV is filled to form a TSV structure 12; and,

[0005] like Figures 3-5 As shown, the first back-side metal redistribution (RDL) process, the first wafer bonding process, the BVR (backside via reveal) process, the second back-side metal redistribution process, and the second wafer bonding process are executed sequentially to achieve stacking.

[0006] When the depth of a through-silicon via (TSV) is greater than 50 μm, the critical dimension (CD) of the TSV is usually greater than 3.5 μm due to the limitation of filling capacity, and the distance between the TSV and the device (KOZ, keep out zone) is usually greater than 4 μm, occupying a large area, which restricts the subsequent metal wiring. Summary of the Invention

[0007] The purpose of this invention is to provide a semiconductor structure and a method for forming the same, in order to solve one or more problems in the prior art.

[0008] To solve the above-mentioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising:

[0009] A substrate is provided, and a first interlayer dielectric layer is formed on the front side of the substrate;

[0010] The first interlayer dielectric layer is etched to form a contact hole, and the contact hole is filled with a conductive material;

[0011] The first interlayer dielectric layer and the substrate are etched sequentially and stopped within the substrate to form a first through-silicon via, and the first through-silicon via is filled with conductive material.

[0012] A first rear-end metal redistribution layer is formed on the first interlayer dielectric layer;

[0013] The first back-end metal redistribution layer, the first interlayer dielectric layer, and the substrate are etched sequentially and stopped within the substrate to form a second through-silicon via (TSV). The TSV is filled with conductive material. The critical dimension of the second TSV is larger than that of the first TSV, and the depth of the second TSV within the substrate is greater than that of the first TSV within the substrate.

[0014] A second rear-end metal redistribution layer is formed on the first rear-end metal redistribution layer;

[0015] Thin the substrate on the back side to expose a portion of the conductive material filling the second through-silicon via;

[0016] A second interlayer dielectric layer is formed on the back side of the thinned substrate. The second interlayer dielectric layer and the substrate are etched and stopped within the substrate to form a third through-silicon via (TSV). The third TSV communicates with the first TSV, and a conductive material is filled within the third TSV.

[0017] A third downstream metal redistribution layer is formed on the second interlayer dielectric layer.

[0018] Optionally, in the method for forming the semiconductor structure, the metal material filling the first through-silicon via and the contact hole is the same.

[0019] Optionally, in the method for forming the semiconductor structure, the metal material filled in the first through-silicon via and the contact hole includes tungsten.

[0020] Optionally, in the method for forming the semiconductor structure, the metal material filling the third through-silicon via may be the same as or different from the metal material filling the first through-silicon via.

[0021] Optionally, in the method for forming the semiconductor structure, the metal material filling the second through-silicon via includes copper.

[0022] Optionally, in the method for forming the semiconductor structure, the critical size of the first through-silicon via is less than or equal to 3.5 μm, and the critical size of the second through-silicon via is greater than 3.5 μm.

[0023] Optionally, in the method for forming the semiconductor structure, the sum of the depths of the first through-silicon via and the third through-silicon via is greater than 50 μm.

[0024] Optionally, in the method for forming the semiconductor structure, the first through-silicon via and the third through-silicon via are formed using the same photomask.

[0025] Optionally, in the method for forming the semiconductor structure, the method further includes:

[0026] After forming the second back-end metal redistribution layer, a first wafer bonding process is performed on the surface of the second back-end metal redistribution layer; and,

[0027] After the third back-end metal redistribution layer is formed, a second wafer bonding process is performed on the surface of the third back-end metal redistribution layer.

[0028] The present invention also provides a semiconductor structure formed using the method described in any of the preceding claims, wherein a metal material filled in the first through-silicon via (TSV) and the third TSV constitutes a first TSV structure, and a metal material filled in the second TSV constitutes a second TSV structure, wherein the first TSV structure is used as a signal line, and the second TSV structure is used as a power line.

[0029] In summary, the semiconductor structure and its formation method provided by this invention are as follows: the first through-silicon via (TSV) structure is completed through two processes, a front-side process and a back-side process, while the second TSV structure is completed through a single front-side process. Since the first TSV structure is completed through two processes, its critical dimensions and depth can be adjusted within a larger range. As a result, the first TSV structure can be designed to have a smaller critical dimension, thus reducing the critical dimension. In addition, the ends of the first and second TSV structures are located at different heights, which increases the process window during subsequent metal wiring. Attached Figure Description

[0030] Figures 1-5 This is a schematic diagram of the device structure corresponding to each step in the formation of an existing logic product;

[0031] Figure 6 A flowchart of a method for forming a semiconductor structure provided in an embodiment of the present invention;

[0032] Figures 7-13 for Figure 6 Schematic diagrams of the device structures corresponding to each step in the process;

[0033] The labels in the accompanying drawings are explained as follows:

[0034] 11-Contact hole structure; 12-Through silicon via structure;

[0035] 21-Substrate; 22-First interlayer dielectric layer; 23-Contact hole structure; 241-First portion; 242-Second via structure; 243-Second portion;

[0036] 251 - First dielectric layer; 252 - First metal layer; 253 - Second metal layer;

[0037] 261 - Second dielectric layer; 262 - Third metal layer;

[0038] 27 - Second interlayer dielectric layer;

[0039] 281 - Third dielectric layer; 282 - Third metal layer; 283 - Fourth metal layer. Detailed Implementation

[0040] To make the objectives, advantages, and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention. Furthermore, the structures shown in the drawings are often part of the actual structure. In particular, different figures need to show different emphases, and sometimes different proportions are used. It should be understood that relative terms such as "above," "below," "top," "bottom," and "upper" shown in the drawings can be used to describe the relationships between various elements. These relative terms are intended to cover different orientations of elements other than those depicted in the drawings. For example, if the device is inverted relative to the view in the drawings, an element described as "above" another element will now be below that element. It should also be understood that, unless specifically stated or indicated, the terms "first," "second," "third," etc., in the specification are only used to distinguish the various components, elements, steps, etc., in the specification, and are not used to indicate logical or sequential relationships between the various components, elements, steps, etc.

[0041] Please see Figure 6 This invention provides a method for forming a semiconductor structure, comprising the following steps:

[0042] S1, providing a substrate, and forming a first interlayer dielectric layer on the front side of the substrate;

[0043] S2, etch the first interlayer dielectric layer to form a contact hole, and fill the contact hole with conductive material;

[0044] S3, sequentially etch the first interlayer dielectric layer and the substrate and stop in the substrate to form a first through-silicon via, and fill the first through-silicon via with conductive material;

[0045] S4, a first rear metal redistribution layer is formed on the first interlayer dielectric layer;

[0046] S5, the first rear metal redistribution layer, the first interlayer dielectric layer and the substrate are etched sequentially and the etching stops in the substrate to form a second through-silicon via (TSV). The TSV is filled with conductive material. The critical dimension of the second TSV is larger than that of the first TSV, and the depth of the second TSV in the substrate is greater than that of the first TSV in the substrate.

[0047] S6, a second rear metal redistribution layer is formed on the first rear metal redistribution layer;

[0048] S7, thin the substrate on the back side to expose a portion of the conductive material filling the second through-silicon via;

[0049] S8, a second interlayer dielectric layer is formed on the back side of the thinned substrate; the second interlayer dielectric layer and the substrate are etched and stopped within the substrate to form a third through-silicon via (TSV), the third TSV communicating with the first TSV, and the third TSV filled with a conductive material; and...

[0050] S9, a third downstream metal redistribution layer is formed on the second interlayer dielectric layer.

[0051] The semiconductor structure formation method provided by this invention involves filling a first through-silicon via (TSV) with conductive material to form a first part of the TSV structure, filling a second TSV with conductive material to form a second TSV structure, and filling a third TSV with conductive material to form a second part of the TSV structure. Thus, the first TSV structure is completed through two processes: a front-side process and a back-side process. When forming the first TSV structure through these two processes, its critical dimensions and depth can be adjusted within a large range. Therefore, both the first and third TSVs can be designed to have smaller critical dimensions. Reducing the critical dimensions can, to a certain extent, increase the process window for subsequent metal wiring. Furthermore, when forming the first part and the second TSV through the front-side process, it is also done through two processes, causing the ends of the second TSV and the first part to be located at different heights, thereby increasing the process window for subsequent metal wiring.

[0052] The following combination Figures 7-13 The steps described above will be described in further detail.

[0053] First, perform step S1, please refer to [link / reference]. Figure 7 A substrate 21 is provided, and a first interlayer dielectric layer 22 is formed on the front side of the substrate 21.

[0054] The substrate 21 may be a substrate that has completed the front-end process, that is, the substrate 21 includes a device structure formed by the front-end process. For example, an active region and a drain region are formed in the substrate 21 by ion implantation, a gate is formed on the surface of the substrate 21, and the source region and the drain region are formed on both sides of the gate. Figure 7 The device is referred to as "Cell" in Chinese, and the distance between the through-silicon via and the device is usually greater than 4 μm.

[0055] The substrate 21 can be made of any suitable substrate material known to those skilled in the art. For example, the substrate 21 can be made of silicon, which will not be elaborated here.

[0056] The first interlayer dielectric layer 22 can be made of any suitable insulating material known to those skilled in the art, such as Figure 7 As illustrated in this embodiment, the first interlayer dielectric layer 22 adopts an ONO multilayer structure, that is, the first interlayer dielectric layer 22 includes a silicon oxide layer, a silicon nitride layer and a silicon oxide layer stacked sequentially.

[0057] Next, proceed to step S2. Please see [link / reference] for further instructions. Figure 7 The first interlayer dielectric layer 22 is etched to form a contact hole (CT), and the contact hole is filled with a conductive material to form a contact hole structure 23. Figure 7 The illustration shows an example with two contact holes, but it should be understood that the number of contact holes does not constitute a limitation of this application. When the substrate 21 is formed with the logic device as described above, the gate, source region, and drain region are electrically connected to the subsequent metal layer through different contact hole structures 23.

[0058] The contact hole is formed using a photolithography process well known to those skilled in the art, which generally includes: forming a patterned hard mask layer that defines the location of the contact hole, and then etching the substrate 21 using the patterned hard mask layer as a mask to form the contact hole, the contact hole being formed above the device fabricated using the front-end process.

[0059] When the contact hole is filled with conductive material, the conductive material will also be deposited on the surface of the first interlayer dielectric layer 22. Therefore, after the contact hole is filled with conductive material, the method provided in this embodiment of the invention further includes the step of performing a chemical mechanical polishing process to remove the conductive material on the surface of the first interlayer dielectric layer 22.

[0060] Then, proceed to step S3, please refer to [link / reference]. Figure 8The first interlayer dielectric layer 22 and the substrate 21 are etched to form a first through-silicon via (TSV1), and a conductive material is filled in the first through-silicon via to form a first portion 241 of the first through-silicon via structure.

[0061] That is, this step is to form the first part 241 of the first through-silicon via structure through the front-side process. Compared with the prior art, since the depth is reduced, the first part 241 can be designed to have a smaller critical size. The reduction of the critical size can increase the process window for subsequent metal wiring to a certain extent.

[0062] Preferably, the conductive material filling the first through-silicon via and the contact hole is the same. Since the conductive material filling the contact hole generally includes tungsten, the conductive material filling the first through-silicon via also includes tungsten.

[0063] Optionally, before filling the first through-silicon via with conductive material, the method provided in this embodiment of the invention further includes the step of depositing an interlayer buffer layer on the sidewall and bottom wall of the first through-silicon via. Further optionally, the interlayer buffer layer includes a titanium layer and a titanium nitride layer, wherein the titanium layer serves as an adhesion layer and the titanium nitride layer serves as a barrier layer.

[0064] Similarly, when the conductive material is filled into the first through-silicon via, the conductive material will also be deposited on the surface of the first interlayer dielectric layer 22. Therefore, after the conductive material is filled into the first through-silicon via, the method provided in this embodiment of the invention further includes a chemical mechanical polishing step to remove the conductive material on the surface of the first interlayer dielectric layer 22 again.

[0065] In the prior art, the contact holes and through-silicon vias are filled with different conductive materials, resulting in a narrow polishing window during the chemical mechanical polishing process. In this embodiment, the contact holes and the first through-silicon via are filled with the same conductive material, thus widening the polishing window during the chemical mechanical polishing process.

[0066] Next, proceed to step S4, see [link to relevant documentation]. Figure 9 A first rear metal redistribution layer is formed on the surface of the first interlayer dielectric layer 22.

[0067] Those skilled in the art will understand that a typical back-end metal redistribution layer consists of a dielectric layer and a metal layer formed within the dielectric layer. Each back-end metal redistribution layer may include one or more metal layers to be electrically connected to different device structures. In this step, the first back-end metal redistribution layer includes a first dielectric layer 251 and a first metal layer 252 and a second metal layer 253 formed within the first dielectric layer 251. The first dielectric layer 251 covers the first interlayer dielectric layer 22. The first metal layer 252 and the second metal layer 253 are located within the first dielectric layer 251. The first metal layer 252 is located above the contact hole structure 23 and is electrically connected to the contact hole structure 23. The second metal layer 253 is located above the first portion 241 and is electrically connected to the first portion 241.

[0068] Since the first portion 241 can be designed to have a smaller critical size than current technology in step S3, the process window for the second metal layer 253 during arrangement is increased in step S4.

[0069] Next, proceed to step S5. Please continue reading... Figure 9 The first back-end metal redistribution layer, the first interlayer dielectric layer 22, and the substrate 21 are etched sequentially and stopped within the substrate 21 to form a second through-silicon via (TSV2). The second through-silicon via is filled with conductive material to form a second through-silicon via structure 242. The critical dimension of the second through-silicon via is larger than that of the first through-silicon via, and the depth of the second through-silicon via within the substrate is greater than that of the first through-silicon via within the substrate.

[0070] Understandably, since the first metal layer 252 and the second metal layer 253 in the first rear metal redistribution layer are located above the contact hole structure 23 and the first portion 241 respectively, when the first rear metal redistribution layer is etched to form the second through-silicon via, only the first dielectric layer 251 will be etched, and the first metal layer 252 and the second metal layer 253 will not be etched.

[0071] Since the depth of the second through-silicon via (TSV) within the substrate 21 is greater than the depth of the first TSV within the substrate 21, the bottom of the second TSV structure 242 is lower than the bottom of the first portion 241. Furthermore, since the first TSV is etched from the first interlayer dielectric layer 22, while the second TSV is etched from the first dielectric layer 251 located above the first interlayer dielectric layer 22, the top of the second TSV structure 242 is higher than the top of the first portion 241.

[0072] Understandably, the terms "top" and "bottom" used here are as follows: Figure 9 As shown, when the front side of the substrate 21 is facing up, relative to the front side of the substrate 21, "top" refers to the end of the second through-silicon via structure 242 / first portion 241 located above the front side of the substrate 21, and "bottom" refers to the end of the second through-silicon via structure 242 / first portion 241 located below the front side of the substrate 21.

[0073] Optionally, before filling the second through-silicon via with conductive material, the method provided in this embodiment of the invention further includes the step of depositing an interlayer buffer layer on the sidewall and bottom wall of the second through-silicon via. Further optionally, the interlayer buffer layer includes a titanium layer and a titanium nitride layer, wherein the titanium layer serves as an adhesion layer and the titanium nitride layer serves as a barrier layer.

[0074] Similarly, when the conductive material is filled into the second through-silicon via, the conductive material will also be deposited on the surface of the first downstream metal redistribution layer. Therefore, after the conductive material is filled into the second through-silicon via, the method provided in this embodiment of the invention further includes a chemical mechanical polishing step to remove the conductive material on the surface of the first downstream metal redistribution layer again.

[0075] Next, proceed to step S6, see [link to relevant documentation]. Figure 10 A second rear metal redistribution layer is formed on the first rear metal redistribution layer. The second rear metal redistribution layer includes a second dielectric layer 261 and a third metal layer 262. The second dielectric layer 261 covers the first dielectric layer 251. The third metal layer 262 is located above the second through-silicon via structure 242 and is electrically connected to the second through-silicon via structure 242.

[0076] Since the top of the second through-silicon via structure 242 is higher than the top of the first portion 241, the second metal layer 253 and the third metal layer 262, which are electrically connected to the first portion 241 and the second through-silicon via structure 242 respectively, are arranged on planes at different heights. As a result, the process window for the second metal layer 253 and the third metal layer 262 during arrangement is increased.

[0077] Please see Figure 11 Optionally, after step S6 is completed, the method provided in this embodiment of the invention may further include: performing a first wafer bonding process on the surface of the second back-end metal redistribution layer. That is, bonding the structure formed by the above steps to other wafers. Wafer bonding processes are well known to those skilled in the art and will not be described in detail here.

[0078] Next, proceed to step S7. Please continue reading... Figure 11Thinning the substrate 21 on its back side to expose a portion of the metal material filling the second through-silicon via (TSV), i.e., exposing a portion of the second TSV structure 242; and performing step S8, see [link to step S8]. Figure 12 A second interlayer dielectric layer 27 is formed on the back side of the substrate 21. The second interlayer dielectric layer 27 and the substrate 21 are etched and stopped within the substrate 21 to form a third through silicon via (TSV3). The third through silicon via communicates with the first through silicon via. The third through silicon via is filled with conductive material to form a second portion 243 of the first through silicon via structure. Since the third through silicon via communicates with the first through silicon via, the second portion 243 is electrically connected to the first portion 241.

[0079] The second interlayer dielectric layer 27 can be made of any suitable dielectric material well known to those skilled in the art. For example, in this embodiment, the material of the second interlayer dielectric layer 27 is silicon oxide. The conductive material filling the third through-silicon via (TSV) can be the same as or different from the conductive material filling the first TSV. That is, the conductive material filling the third TSV may include tungsten or copper. Since the first TSV structure is used as a signal line, its normal function is not affected even if the conductive material filling the third TSV is not copper.

[0080] If the deposition thickness of the second interlayer dielectric layer 27 is greater than the height of the portion of the second through-silicon via structure 242 exposed on the substrate 21, the following step may be included: thinning the second interlayer dielectric layer 27 until the height of the portion of the second through-silicon via structure 242 exposed on the substrate 21 is equal to the thickness of the second interlayer dielectric layer 27, so that the end of the second through-silicon via structure 242 is flush with the surface of the second interlayer dielectric layer 27. Specifically, the thinning can be performed by chemical mechanical polishing.

[0081] Combining steps S3 and S8, it can be seen that in the method provided in this embodiment, the first through-silicon via (TSV) structure is completed through two processes: a front-side process and a back-side process. Compared to forming a TSV structure through a single process, the critical dimensions and depths of the first and third TSVs have a larger adjustment range. Therefore, during design, the sum of the depths of the first and third TSVs only needs to be greater than 50 μm, while the individual depths of the first and third TSVs can be less than 50 μm. Since the depth is less than 50 μm, their respective critical dimensions can also be designed to be less than or equal to 3.5 μm. Thus, the method provided in this embodiment can solve the problems of large critical dimensions and narrow process windows for TSVs.

[0082] In this embodiment, preferably, the first and third through-silicon vias (TSVs) are formed using the same photomask; that is, the first and third TSVs are designed to have the same critical dimensions. This reduces the number of photomasks required, thus saving costs. In other embodiments, the third TSV may have a different critical dimension than the first TSV. The critical dimensions and depth of the third TSV can be adjusted as needed. In particular, the depth of the third TSV can be adjusted based on the depth of the first TSV, as long as the sum of their depths is greater than 50 μm.

[0083] Optionally, before filling the third through-silicon via with conductive material, the method provided in this embodiment of the invention further includes a step of depositing an interlayer buffer layer on the sidewalls and bottom wall of the third through-silicon via. The interlayer buffer layer may also include a titanium layer and a titanium nitride layer, wherein the titanium layer serves as an adhesion layer and the titanium nitride layer serves as a barrier layer. Similarly, when filling the third through-silicon via with conductive material, the conductive material is also deposited on the surface of the second interlayer dielectric layer 27. Therefore, after filling the third through-silicon via with the second conductive material, the method provided in this embodiment of the invention further includes a chemical mechanical polishing step to remove the conductive material from the surface of the second interlayer dielectric layer 27.

[0084] Finally, perform step S9, please refer to [link / reference]. Figure 13 A third post-metal redistribution layer is formed on the second interlayer dielectric layer 27. The third post-metal redistribution layer includes a third dielectric layer 281 and a fourth metal layer 282 and a fifth metal layer 283 located within the third dielectric layer 281. The fourth metal layer 282 is located above the second through-silicon via structure 242 and is electrically connected to the second through-silicon via structure 242. The fifth metal layer 283 is located above the second portion 243 and is electrically connected to the second portion 243.

[0085] The first dielectric layer 251, the second dielectric layer 261 and the third dielectric layer 281 can all be made of any suitable dielectric material known to those skilled in the art. As an example, in this embodiment, the first dielectric layer 251, the second dielectric layer 261 and the third dielectric layer 281 are made of silicon oxide.

[0086] Optional, please continue to see Figure 13 After performing step S8, the method provided in this embodiment of the invention further includes performing a second wafer bonding process on the surface of the third rear-end metal redistribution layer. That is, bonding the structure formed by the above steps to other wafers. Wafer bonding processes are well known to those skilled in the art and will not be described in detail here.

[0087] It should be noted that although "above" is not restrictive, it can be understood that in the above description, "above" refers to the area above the operating surface. However, the operating surface will change for different process steps. For example, when steps S1 to S6 are performed, the front side of the substrate 21 faces upward, and the operating surface is the front side of the substrate 21 or the side of each film layer on the front side of the substrate 21 that is away from the substrate 21. When steps S7 to S9 are performed, the back side of the substrate 21 faces upward, and the operating surface is the back side of the substrate 21 or the side of each film layer on the back side of the substrate 21 that is away from the substrate 21.

[0088] Furthermore, embodiments of the present invention also provide a semiconductor structure formed by the method described in this embodiment. The first through-silicon via (TSV) structure, composed of a first portion 241 and a second portion 243, serves as a signal line, and the second TSV structure 242 serves as a power line.

[0089] In summary, the semiconductor structure and its fabrication method provided by the embodiments of the present invention include: providing a substrate and forming a first interlayer dielectric layer on the front side of the substrate; etching the first interlayer dielectric layer to form a contact hole and filling the contact hole with a conductive material; sequentially etching the first interlayer dielectric layer and the substrate and stopping within the substrate to form a first through-silicon via (TSV), and filling the TSV with a conductive material; forming a first back-end metal redistribution layer on the first interlayer dielectric layer; sequentially etching the first back-end metal redistribution layer, the first interlayer dielectric layer, and the substrate and stopping within the substrate to form a second TSV, and filling the second TSV with a conductive material. The critical dimension of the second through-silicon via (TSV) is larger than that of the first TSV, and the depth of the second TSV within the substrate is greater than that of the first TSV within the substrate; a second back-end metal redistribution layer is formed on the first back-end metal redistribution layer; the substrate is thinned on the back side to expose a portion of the conductive material filled within the second TSV; a second interlayer dielectric layer is formed on the thinned back side of the substrate; the second interlayer dielectric layer and the substrate are etched and stopped within the substrate to form a third TSV, the third TSV communicating with the first TSV and filled with conductive material; and a third back-end metal redistribution layer is formed on the second interlayer dielectric layer. The semiconductor structure and its fabrication method provided by this invention have the following advantages compared to the prior art:

[0090] (1) TSV1 uses a small size and occupies a small area, which allows the distance (KOZ) between the through silicon via and the device (cell) to be increased, thereby increasing the process window for subsequent metal wiring;

[0091] (2) The first part 241 of the first through-silicon via structure and the ends of the second through-silicon via structure 242 are located at different heights, which increases the process window during subsequent metal wiring.

[0092] (3) TSV1 and CT use the same metal filler material, thus the process window can be increased when grinding them at the same time;

[0093] (4) The key dimensions and depth of TSV1 and TSV3 have a large adjustable range.

[0094] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments with equivalent changes, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, and a first interlayer dielectric layer is formed on the front side of the substrate; The first interlayer dielectric layer is etched to form a contact hole, and the contact hole is filled with a conductive material; The first interlayer dielectric layer and the substrate are etched sequentially and stopped within the substrate to form a first through-silicon via, and the first through-silicon via is filled with conductive material. A first rear-end metal redistribution layer is formed on the first interlayer dielectric layer; The first back-end metal redistribution layer, the first interlayer dielectric layer, and the substrate are etched sequentially and stopped within the substrate to form a second through-silicon via (TSV). The TSV is filled with conductive material. The critical dimension of the second TSV is larger than that of the first TSV, and the depth of the second TSV within the substrate is greater than that of the first TSV within the substrate. A second rear-end metal redistribution layer is formed on the first rear-end metal redistribution layer; Thin the substrate on the back side to expose a portion of the conductive material filling the second through-silicon via; A second interlayer dielectric layer is formed on the back side of the thinned substrate. The second interlayer dielectric layer and the substrate are etched and stopped in the substrate to form a third through-silicon via. The third through-silicon via communicates with the first through-silicon via and is filled with conductive material. as well as, A third downstream metal redistribution layer is formed on the second interlayer dielectric layer.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first through-silicon via and the contact hole are filled with the same metal material.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The metallic material filling the first through-silicon via and the contact hole includes tungsten.

4. The method for forming a semiconductor structure as described in claim 2, characterized in that, The metal material filling the third through-silicon via may be the same as or different from the metal material filling the first through-silicon via.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The metallic material filling the second through-silicon via includes copper.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The critical size of the first through-silicon via is less than or equal to 3.5 μm, and the critical size of the second through-silicon via is greater than 3.5 μm.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The sum of the depths of the first and third through-silicon vias is greater than 50 μm.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first through-silicon via and the third through-silicon via are formed using the same photomask.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The forming method further includes: After forming the second back-end metal redistribution layer, a first wafer bonding process is performed on the surface of the second back-end metal redistribution layer; and, After the third back-end metal redistribution layer is formed, a second wafer bonding process is performed on the surface of the third back-end metal redistribution layer.

10. A semiconductor structure, characterized in that, The semiconductor structure is formed using the method described in any one of claims 1 to 9, wherein the metal material filled in the first through-silicon via and the third through-silicon via constitutes a first through-silicon via structure, the metal material filled in the second through-silicon via constitutes a second through-silicon via structure, the first through-silicon via structure is used as a signal line, and the second through-silicon via structure is used as a power line.

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