Semiconductor device

Abstract

A semiconductor device includes a substrate including a first surface and a second surface opposite each other, a cell region, and an exclusion region; an active pattern; a dummy pattern; a source / drain pattern; a dummy source / drain pattern; a gate electrode; a dummy gate; an upper wiring connected to at least one first source / drain pattern of the source / drain pattern; a lower wiring connected to at least one second source / drain pattern of the source / drain pattern; and a dummy wiring extending from one of the upper wiring or the lower wiring, wherein the dummy gate and the dummy source / drain pattern are insulated from the upper wiring and the lower wiring, and wherein an end portion of the dummy wiring is on the exclusion region.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0174072, filed with the Korean Intellectual Property Office on November 28, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to semiconductor devices. Background Technology

[0004] In recent years, with the rapid integration and miniaturization of semiconductor devices, there is an increasing desire to improve device performance and ensure stability. Although various process and design technologies have been introduced for this purpose, semiconductor devices may still contain defects due to physical and chemical stresses or process deviations. Therefore, it is desirable to analyze the causes of defects in semiconductor devices, optimize processes and designs, and ensure product quality and reliability.

[0005] Fault analysis (FA) is an analytical process performed to identify the cause of such defects, and it can be performed through electrical characteristic analysis, observation using scanning electron microscopy (SEM), and layer removal processes (e.g., delamination). Delamination is a method of observing the internal structure by removing layers one by one from the top to the bottom of the device, and it is widely used as a method for accurately analyzing defects in each layer.

[0006] However, the process of connecting electrodes such as source, drain, and gate to a single analytical circuit network can require highly precise techniques, and it is particularly desirable to maintain the connections during the removal of each layer. Against this backdrop, research is actively underway on connecting the source, drain, and gate and maintaining their electrical properties even after the layer removal process (delamination). Summary of the Invention

[0007] The embodiments of this disclosure retain electrical properties even after a layer removal process (de-lamination) used for defect analysis.

[0008] A semiconductor device according to some embodiments includes: a substrate including a first surface and a second surface, a cell region and an exclusion region, the first surface and the second surface being opposite to each other; an active pattern and a dummy pattern, spaced apart from each other in a first direction and on the first surface of the substrate; a source / drain pattern and a dummy source / drain pattern, respectively connected to the active pattern and the dummy pattern; a gate electrode and a dummy gate electrode, respectively extending around the active pattern and the dummy pattern and extending along a second direction intersecting the first direction; an upper wiring on the first surface of the substrate, the upper wiring being on the cell region and connected to at least one first source / drain pattern in the source / drain patterns; a lower wiring on the second surface of the substrate, the lower wiring being on the cell region and connected to at least one second source / drain pattern in the source / drain patterns; and a dummy wiring extending from one of the upper wiring or the lower wiring, wherein the dummy gate electrode and the dummy source / drain pattern are insulated from the upper wiring and the lower wiring, and wherein the end of the dummy wiring is on the exclusion region.

[0009] A semiconductor device according to some embodiments includes: a substrate including a first surface and a second surface, a cell region and an exclusion region, the first surface and the second surface being opposite to each other; an active pattern and a dummy pattern, spaced apart from each other in a first direction and on the first surface of the substrate; a source / drain pattern and a dummy source / drain pattern, respectively connected to the active pattern and the dummy pattern; a gate electrode and a dummy gate electrode, respectively extending around the active pattern and the dummy pattern and extending along a second direction intersecting the first direction; an upper wiring on the first surface of the substrate, the upper wiring being on the cell region and connected to at least one first source / drain pattern in the source / drain patterns; a lower wiring on the second surface of the substrate, the lower wiring being on the cell region and connected to at least one second source / drain pattern in the source / drain patterns; and a dummy wiring extending from one of the upper wiring or the lower wiring, wherein the dummy gate electrode and the dummy source / drain pattern are insulated from the upper wiring and the lower wiring, and wherein the dummy wiring extends into the exclusion region.

[0010] A semiconductor device according to some embodiments includes: a substrate including a first surface and a second surface, a first element region, a second element region, and a dummy region between the first element region and the second element region, the first surface and the second surface being opposite to each other; a first active pattern, a second active pattern, and a dummy pattern, spaced apart from each other in a first direction and respectively on the first surface of the first element region, the second element region, and the dummy region of the substrate; a first source / drain pattern, a second source / drain pattern, and a dummy source / drain pattern, respectively connected to the first active pattern, the second active pattern, and the dummy pattern; a first gate electrode, a second gate electrode, and a dummy gate electrode, respectively surrounding the first active pattern, the second active pattern, and the dummy region. A dummy pattern extends and extends in a second direction intersecting the first direction; an upper wiring is on a first surface of the substrate and connected to a first set of first source / drain patterns and a first set of second source / drain patterns; a lower wiring is on a second surface of the substrate and connected to a second set of first source / drain patterns and a second set of second source / drain patterns; and a dummy wiring extends from either the upper or lower wiring, wherein the dummy gate electrode and the dummy source / drain pattern are insulated from the upper and lower wirings on a portion of the dummy region, and wherein the dummy wiring crosses the portion of the dummy region in the first direction and is connected to at least one of the first source / drain patterns and at least one of the second source / drain patterns.

[0011] According to an embodiment, a layer removal process (de-layering) for fault analysis can be performed while maintaining the electrical characteristics of the semiconductor device. Attached Figure Description

[0012] Figure 1 This is a top view of a semiconductor wafer on which semiconductor devices are formed, according to some embodiments.

[0013] Figure 2 yes Figure 1 A magnified view of region M.

[0014] Figure 3 According to some embodiments Figure 2 A cross-sectional view taken from line A-A'.

[0015] Figure 4 According to some embodiments Figure 2 The cross-sectional view taken by line B-B'.

[0016] Figures 5 to 7 This is a cross-sectional view showing a method for performing fault analysis according to some embodiments.

[0017] Figure 8 According to some embodiments Figure 2 A cross-sectional view taken from line A-A'.

[0018] Figure 9According to some embodiments Figure 2 The cross-sectional view taken by line B-B'.

[0019] Figure 10 According to some embodiments Figure 2 A cross-sectional view taken from line A-A'.

[0020] Figure 11 According to some embodiments Figure 2 The cross-sectional view taken by line B-B'.

[0021] Figure 12 According to some embodiments Figure 2 A cross-sectional view taken from line A-A'.

[0022] Figure 13 According to some embodiments Figure 2 The cross-sectional view taken by line B-B'.

[0023] Figure 14 This is a top view of a semiconductor device according to some embodiments.

[0024] Figure 15 According to some embodiments Figure 14 A magnified view of region N.

[0025] Figure 16 According to some embodiments Figure 15 A cross-sectional view taken from line A-A'.

[0026] Figure 17 According to some embodiments Figure 2 A cross-sectional view taken from line A-A'.

[0027] Figure 18 According to some embodiments Figure 2 The cross-sectional view taken by line B-B'.

[0028] Figure 19 According to some embodiments Figure 14 A magnified view of region N.

[0029] Figure 20 According to some embodiments Figure 15 A cross-sectional view taken from line A-A'.

[0030] Figure 21 According to some embodiments Figure 15 The cross-sectional view taken by line B-B'. Detailed Implementation

[0031] In the following description, the present disclosure will be made more fully with reference to the accompanying drawings, which illustrate exemplary embodiments of the present disclosure. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of the present disclosure.

[0032] Descriptions of parts not related to this disclosure have been omitted, and similar reference numerals denote similar elements throughout this specification.

[0033] Furthermore, since the dimensions and thicknesses of the constituent components shown in the accompanying drawings are arbitrarily given for better understanding and ease of description, this disclosure is not limited to the dimensions and thicknesses shown. In the drawings, the thicknesses of layers, films, panels, regions, etc., have been enlarged for clarity. In the drawings, the thicknesses of some layers and regions have been enlarged for better understanding and ease of description.

[0034] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on that other element or there may be intermediate elements present. In contrast, when an element is referred to as being "directly on" another element, there are no intermediate elements present. Furthermore, in this specification, the terms "on" or "above" mean located above or below the object portion and do not necessarily mean on the upper side of the object portion based on the direction of gravity.

[0035] Furthermore, unless explicitly stated otherwise, the word “comprising” and its variants such as “containing” or “including” will be understood to mean including the described element, but not excluding any other element. The singular forms “a,” “an,” and “the” used herein are also intended to include the plural forms, unless the context explicitly indicates otherwise. The term “and / or” includes any and all combinations relating to one or more of the listed items. The term “connection” may be used herein to refer to physical and / or electrical connections, and may refer to direct or indirect physical and / or electrical connections. Components or layers described with reference to “overlapping” in a particular direction may at least partially obscure each other when viewed along a line extending in a particular direction or in a plane perpendicular to that direction. The terms “first,” “second,” etc., used herein may be used only to distinguish one component, element, etc., from another component, element region, etc.

[0036] Furthermore, throughout this specification, the phrase "in a plane" means the target portion as viewed from above, and the phrase "in a cross section" means the cross section formed by vertically cutting the target portion as viewed from the side.

[0037] Furthermore, throughout this specification, two directions parallel to and intersecting the upper surface of the substrate are defined as the first direction D1 and the second direction D2, respectively, and the direction perpendicular to the upper surface of the substrate is described as the third direction D3. For example, the first direction D1 and the second direction D2 may be orthogonal to each other.

[0038] The accompanying drawings of semiconductor devices according to some embodiments include GAA (gate all around) and MBCFETs, which include nanowires or nanosheets. TM (Multi-bridge channel field-effect transistor) is shown as an example, but is not limited thereto. According to some embodiments, the semiconductor device may include: a fin transistor (FinFET) including a channel region with a fin pattern shape; a tunneling transistor (tunneling FET); a 3D-SFET (3D stacked field-effect transistor) structure; and a CFET (complementary field-effect transistor) structure.

[0039] Below, the semiconductor device according to some embodiments of this disclosure can be used in various memory devices and systems including wiring structures. For example, the semiconductor device can be applied to wiring structures included in logic devices such as central processing units (CPUs, MPUs), application processors (APs). In some embodiments, the semiconductor device can be applied to wiring structures used in memory peripheral circuit regions or cell regions of volatile memory devices such as DRAM devices or SRAM devices, or non-volatile memory devices such as flash memory devices, PRAM devices, MRAM devices, or RRAM devices.

[0040] Hereinafter, a semiconductor device according to some embodiments will be described with reference to the accompanying drawings.

[0041] Figure 1 This is a top view of a semiconductor wafer on which semiconductor devices are formed, according to some embodiments.

[0042] refer to Figure 1 A semiconductor wafer may include semiconductor chip regions and scribe lines (SLs) between semiconductor chip regions. Additionally, a semiconductor chip region may include cell regions (CRs) and peripheral regions (PRs). In other words, one or more cell regions (CRs) and peripheral regions (PRs) may form a semiconductor chip region, and the scribe lines (SLs) may be arranged to surround or extend around the semiconductor chip region. Logic circuits constituting a semiconductor device, or logic transistors included in logic circuits within a semiconductor device, may be placed in or on cell regions (CRs). I / O terminals constituting a processor core or cell regions (CRs), or transistors included in I / O terminals of a processor core or cell regions (CRs), may be placed in or on peripheral regions (PRs).

[0043] although Figure 1The illustration shows a peripheral region PR extending around or around a cell region CR, but this disclosure is not limited to this arrangement, and the cell region CR and the peripheral region PR can have any suitable arrangement. According to some embodiments, a portion of the peripheral region PR may be placed within or on the cell region CR. Furthermore, the number of cell regions CR forming a semiconductor chip region is not limited to the number shown.

[0044] The scribe line (SL) corresponds to the region used for a dicing process after the formation of semiconductor devices in the semiconductor chip area, which separates the semiconductor wafer into individual semiconductor chips. Although not shown, the scribe line (SL) may include a bonding region. The bonding region may include alignment bonds or overlay bonds used in the exposure process performed to form semiconductor devices on the semiconductor chip area.

[0045] Figure 2 yes Figure 1 A magnified view of region M. Figure 3 According to some embodiments Figure 2 A cross-sectional view taken from line A-A'. Figure 4 According to some embodiments Figure 2 The cross-sectional view taken by line B-B'.

[0046] refer to Figures 2 to 4 A substrate 110 may be provided, including a first region R1 and a second region R2. According to some embodiments, the first region R1 may be... Figure 1 Any region within the cell region CR, and the second region R2 can be Figure 1 Any region within the peripheral region PR. In this disclosure, the first region R1 may correspond to a region including an electrically active transistor, and the second region R2 may correspond to a region including an electrically passive transistor.

[0047] In this disclosure, the second region R2 may be referred to as an exclusion region or exclusion area. An exclusion region may refer to a region designed so that wiring is not intentionally connected to a transistor.

[0048] According to some embodiments, substrate 110 may be an insulating substrate comprising an insulating material. Substrate 110 may comprise oxides, nitrides, oxynitrides, or combinations thereof. For example, substrate 110 may comprise silicon nitride (SiNx). In some embodiments, substrate 110 may be a semiconductor substrate comprising a semiconductor material. For example, substrate 110 may comprise silicon, germanium, or silicon-germanium. Therefore, the lower contact pattern BCA and the first lower wiring pattern BM1 may contact the substrate 110 comprising the insulating material. In other words, substrate 110 extending around or around the lower contact pattern BCA may be an insulating material. If substrate 110 comprises a semiconductor material, it will not contact the lower contact pattern BCA and the first lower wiring pattern BM1. Therefore, separate insulating layers may be disposed between substrate 110 and the lower contact pattern BCA and between substrate 110 and the first lower wiring pattern BM1. Although substrate 110 is depicted as a single film, this is only for better understanding and ease of illustration and is not a limitation thereof.

[0049] According to some embodiments, the first and second surfaces of the substrate 110 can be formed as planes parallel to the first direction D1 and the second direction D2, with the second direction D2 intersecting the first direction D1. For example, the first surface of the substrate 110 can be the upper surface, and the second surface can be the lower surface. The upper surface of the substrate 110 is the surface opposite to the lower surface of the substrate 110 in a third direction D3. The third direction D3 can be a direction perpendicular to the first direction D1 and the second direction D2. The lower surface of the substrate 110 can be referred to as the rear side of the substrate 110. In some embodiments, the logic circuitry of the cell region can be implemented on the upper surface of the substrate 110. In some embodiments, the upper wiring region FS can be located on the upper surface of the substrate 110. In some embodiments, the lower wiring region BS can be located on the lower surface of the substrate 110.

[0050] According to some embodiments, the semiconductor device may include: an activation pattern AP, spaced apart in a first region R1 and on a first surface of a substrate 110 along a first direction D1; a source / drain pattern SD, connected to both sides of the activation pattern AP; and a gate structure GE, extending around or around the activation pattern AP and extending in a second direction D2.

[0051] According to some embodiments, the semiconductor device may include: a dummy pattern DP, spaced apart in a second region R2 and on a first surface of substrate 110 along a first direction D1; a dummy source / drain pattern DSD, connected to both sides of the dummy pattern DP; and a dummy gate structure DGE, extending in a second direction D2 and extending around or around the dummy pattern DP.

[0052] According to some embodiments, activation patterns AP can be arranged to be spaced apart along a first direction D1 on a first region R1 of substrate 110. According to some embodiments, a plurality of activation patterns AP can be arranged to be spaced apart from each other on a third direction D3.

[0053] For example, each of the multiple activation patterns AP can have a sheet shape. Each of the multiple activation patterns AP can be a nanosheet with a thickness of a few nanometers along the third direction D3.

[0054] According to some embodiments, the activation pattern AP can provide a path for current flowing between the source / drain patterns SD. For example, the activation pattern AP can be placed between and connected to the source / drain patterns SD.

[0055] According to some embodiments, the activation pattern AP may penetrate or extend into a portion of the gate structure GE (described later) in a direction intersecting the direction in which the gate structure GE extends (e.g., a first direction D1). Figure 3 In the diagram, three active pattern APs are shown arranged spaced apart on a third-direction D3, but this arrangement is not limited to and the number of active pattern APs stacked can be varied in various ways.

[0056] refer to Figure 3 and Figure 4 The dummy pattern DP can be arranged to be spaced apart along a first direction D1 on a second region R2 of the substrate 110. According to some embodiments, a plurality of dummy patterns DP can be arranged to be spaced apart from each other on a third direction D3.

[0057] For example, multiple dummy patterns DP can have a sheet shape. Multiple dummy patterns DP can be nanosheets with a thickness of a few nanometers along a third direction D3.

[0058] According to some embodiments, the dummy pattern DP may penetrate or extend into a portion of the dummy gate structure DGE, described later, in a direction intersecting with the direction in which the dummy gate structure DGE extends (e.g., a first direction D1). Figure 3 and Figure 4 In the diagram, three dummy patterns DP are shown arranged spaced apart on a third direction D3, but this arrangement is not limited to and the number of dummy pattern DP stacks can be varied in various ways.

[0059] According to some embodiments, the active pattern AP and the dummy pattern DP may include semiconductor materials. For example, the active pattern AP and the dummy pattern DP may include group IV semiconductors, such as Si, Ge, group III-V compound semiconductors, group II-VI compound semiconductors, etc.

[0060] According to some embodiments, the gate structure GE and the dummy gate structure DGE may be located on a first region R1 and a second region R2 of the substrate 110, respectively. According to some embodiments, the gate structure GE and the dummy gate structure DGE may extend along a second direction D2 on the first region R1 and the second region R2 of the substrate 110, respectively. The gate structure GE and the dummy gate structure DGE may be arranged to be spaced apart from each other in a first direction D1.

[0061] According to some embodiments, the gate structure GE may include multiple sub-gate structures MG_S and GI_S, and main gate structures MG_M and GI_M. The sub-gate structures MG_S and GI_S may be located on a first region R1 of the substrate 110, and the main gate structures MG_M and GI_M may be located on the sub-gate structures MG_S and GI_S.

[0062] Each of the sub-gate structures MG_S and GI_S can be composed of multiple layers. For example, each of the sub-gate structures MG_S and GI_S may include a sub-gate electrode MG_S and a sub-gate insulating layer GI_S.

[0063] According to some embodiments, the dummy gate structure DGE may include multiple dummy sub-gate structures DMG_S and DGI_S, and dummy main gate structures DMG_M and DGI_M. The dummy sub-gate structures DMG_S and DGI_S may be located on the second region R2 of the substrate 110, and the dummy main gate structures DMG_M and DGI_M may be located on the dummy sub-gate structures DMG_S and DGI_S.

[0064] Each of the dummy subgate structures DMG_S and DGI_S can be composed of multiple layers. For example, each of the dummy subgate structures DMG_S and DGI_S may include a dummy subgate electrode DMG_S and a dummy subgate insulating layer DGI_S.

[0065] According to some embodiments, in the first region R1, sub-gate structures MG_S and GI_S, as well as the activation pattern AP, may be alternately stacked on the third-direction D3. According to some embodiments, in or on the second region R2, dummy sub-gate structures DMG_S and DGI_S, as well as the dummy pattern DP, may be alternately stacked on the third-direction D3.

[0066] exist Figure 3 In the diagram, the three sub-gate structures MG_S and GI_S are depicted as being spaced apart on the third direction D3, but the number of spaced sub-gate structures MG_S and GI_S is not limited to this. For example, the gate structure GE may include four sub-gate structures MG_S and GI_S. Figure 3 and Figure 4In the diagram, three dummy sub-gate structures DMG_S and DGI_S are shown arranged at intervals on the third-direction D3, but the number of dummy sub-gate structures DMG_S and DGI_S arranged at intervals is not limited thereto. For example, the dummy gate structure DGE may include four dummy sub-gate structures DMG_S and DGI_S.

[0067] According to some embodiments, the sub-gate electrode MG_S and the dummy sub-gate electrode DMG_S can be located on a first region R1 and a second region R2 of the substrate 110, respectively. According to some embodiments, the sub-gate electrode MG_S in the first region R1 can extend around or around the active pattern AP. In the second region R2, the dummy sub-gate electrode DMG_S can extend around or around the dummy pattern DP.

[0068] The sub-gate electrode MG_S and the dummy sub-gate electrode DMG_S can include at least one of the following: metal, metal alloy, conductive metal nitride, metal silicide, doped semiconductor material, conductive metal oxide, and conductive metal oxide nitride. For example, the sub-gate electrode MG_S and the dummy sub-gate electrode DMG_S can include titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), and tantalum carbonitride (Ta... The materials are selected from at least one of the following: CN, tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or combinations thereof, but are not limited thereto. Conductive metal oxides and conductive metal nitrides may include, but are not limited to, the oxidation forms of the materials described above.

[0069] The sub-gate insulating layer GI_S and the dummy sub-gate insulating layer DGI_S can extend along the upper surfaces of the first region R1 and the second region R2 of the substrate 110, respectively. The sub-gate insulating layer GI_S and the dummy sub-gate insulating layer DGI_S can be positioned along the perimeters of the plurality of sub-gate electrodes MG_S and the plurality of dummy sub-gate electrodes DMG_S, respectively. The sub-gate insulating layer GI_S can contact the plurality of active patterns AP and the upper surface of the substrate 110. The dummy sub-gate insulating layer DGI_S can contact the plurality of dummy patterns DP and the upper surface of the substrate 110. The sub-gate insulating layer GI_S can be located between the plurality of active patterns AP and the plurality of sub-gate electrodes MG_S. The dummy sub-gate insulating layer DGI_S can be located between the plurality of dummy patterns DP and the plurality of dummy sub-gate electrodes DMG_S. According to some embodiments, the sub-gate insulating layer GI_S and the dummy sub-gate insulating layer DGI_S can each comprise various insulating materials.

[0070] although Figure 3 and Figure 4 Not shown, but according to some embodiments, the semiconductor device may also include the internal gate spacer described below located between the sub-gate insulating layer GI_S and the source / drain pattern SD. Additionally, although... Figure 3 and Figure 4 The semiconductor device, though not shown, may also include, according to some embodiments, an internal gate spacer located between the dummy sub-gate insulating layer DGI_S and the dummy source / drain pattern DSD.

[0071] In some embodiments, the sub-gate insulating layer GI_S and the dummy sub-gate insulating layer DGI_S may be depicted as a single film, but are not limited thereto. For example, the sub-gate insulating layer GI_S and the dummy sub-gate insulating layer DGI_S may comprise silicon oxide, silicon oxynitride, or silicon nitride. In some embodiments, for example, the sub-gate insulating layer GI_S and the dummy sub-gate insulating layer DGI_S may comprise a high dielectric constant material. In some embodiments, for example, the sub-gate insulating layer GI_S and the dummy sub-gate insulating layer DGI_S may comprise both silicon oxide and a high dielectric constant material. The high dielectric constant material may comprise a material with a dielectric constant higher than silicon oxide (SiO2), such as hafnium oxide (HfO), aluminum oxide (AlO), or tantalum oxide (TaO).

[0072] According to some embodiments, the main gate structures MG_M and GI_M may be located on the sub-gate structures MG_S and GI_S and a plurality of activation patterns AP. The main gate structures MG_M and GI_M may be located on the upper surface of the activation pattern AP, which is located at the top of the plurality of activation pattern APs.

[0073] According to some embodiments, dummy main gate structures DMG_M and DGI_M may be located on dummy sub-gate structures DMG_S and DGI_S and multiple dummy patterns DP. The dummy main gate structures DMG_M and DGI_M may be located on the upper surface of the dummy pattern DP, which is located at the top of the multiple dummy patterns DP.

[0074] refer to Figure 4 At least a portion of the dummy gate electrode DMG can be located on a structure in which dummy sub-gate electrodes DMG_S and dummy patterns DP are alternately stacked. Another portion of the dummy gate electrode DMG can be formed to cover or at least partially overlap the two sides of the structure in which dummy sub-gate electrodes DMG_S and dummy patterns DP are alternately stacked. Therefore, the four surfaces of the plurality of dummy patterns DP can be at least partially surrounded by the dummy gate electrode DMG. Although not shown, the four surfaces of AP can be at least partially surrounded by the gate electrodes MG_M and MG_S in the first region R1.

[0075] According to some embodiments, the main gate structures MG_M and GI_M may include a main gate electrode MG_M and a main gate insulating layer GI_M. According to some embodiments, the dummy main gate structures DMG_M and DGI_M may include a dummy main gate electrode DMG_M and a dummy main gate insulating layer DGI_M.

[0076] According to some embodiments, the main gate electrode MG_M may be located on the sub-gate structures MG_S and GI_S and multiple active patterns AP. According to some embodiments, the dummy main gate electrode DMG_M may be located on the dummy sub-gate structures DMG_S and DGI_S and multiple dummy patterns DP. The main gate electrode MG_M and the dummy main gate electrode DMG_M may each comprise the same material as the sub-gate electrode MG_S and the dummy sub-gate electrode DMG_S. For example, the main gate electrode MG_M and the dummy main gate electrode DMG_M may comprise at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal oxynitride.

[0077] According to some embodiments, the main gate insulating layer GI_M and the dummy main gate insulating layer DGI_M may extend along the side surface and lower surface of the main gate electrode MG_M and the dummy main gate electrode DMG_M, respectively. The main gate insulating layer GI_M and the dummy main gate insulating layer DGI_M may extend along the side surface of the gate spacer GS and the dummy gate spacer DGS, respectively, as described below. The main gate insulating layer GI_M and the dummy main gate insulating layer DGI_M may each comprise various insulating materials.

[0078] In some embodiments, the main gate insulating layer GI_M and the dummy main gate insulating layer DGI_M are each depicted as a single film, but are not limited thereto. For example, the main gate insulating layer GI_M and the dummy main gate insulating layer DGI_M may be formed from multiple layers, including silicon oxide (SiO2) and a high dielectric constant material, respectively. Thus, the high dielectric constant material may include materials with a higher dielectric constant than silicon oxide (SiO2), such as hafnium oxide (HfO), aluminum oxide (AlO), or tantalum oxide (TaO).

[0079] According to some embodiments, the semiconductor device may further include a gate spacer GS and a dummy gate spacer DGS located in a first region R1 and a second region R2, respectively.

[0080] According to some embodiments, the gate spacer GS and the dummy gate spacer DGS can be located on opposite sides of the main gate electrode MG_M and the dummy main gate electrode DMG_M, respectively. The gate spacer GS and the dummy gate spacer DGS may not be placed between the substrate 110 and the active pattern AP, or between the substrate 110 and the dummy pattern DP, respectively. According to some embodiments, the gate spacer GS and the dummy gate spacer DGS may not be placed between multiple active patterns AP and multiple dummy patterns DP adjacent along the third direction D3, respectively.

[0081] The gate spacer GS and the dummy gate spacer DGS may each include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon carbon oxynitride (SiOC), or combinations thereof. The gate spacer layer GS is depicted as a single layer, but this is for better understanding and ease of description, and is not a limitation thereof.

[0082] refer to Figure 3 The source / drain pattern SD and the dummy source / drain pattern DSD can be located on the first region R1 and the second region R2 of the substrate 110, respectively. According to some embodiments, the source / drain pattern SD and the dummy source / drain pattern DSD can be arranged to be spaced apart along a first direction D1 on the first region R1 and the second region R2 of the substrate 110, respectively. The active pattern AP and the gate structure GE can be located between the source / drain patterns SD. The dummy pattern DP and the dummy gate structure DGE can be located between the dummy source / drain patterns DSD. In other words, multiple source / drain patterns SD and multiple active patterns AP can be alternately arranged on the first region R1 of the substrate 110 along the first direction D1, and multiple dummy source / drain patterns DSD and multiple dummy patterns DP can be alternately arranged on the second region R2 of the substrate 110 along the first direction D1.

[0083] Although not shown, the source / drain pattern SD and the dummy source / drain pattern DSD can also be arranged along the second direction D2, respectively. The source / drain pattern SD and the dummy source / drain pattern DSD can be arranged to be spaced apart along the second direction D2 on the first region R1 and the second region R2 of the substrate 110, respectively.

[0084] According to some embodiments, in the first region R1, the source / drain pattern SD can be located on both sides of the active pattern AP and / or the sub-gate structures MG_S and GI_S. Specifically, two source / drain patterns SD can be arranged along a direction intersecting the direction of the gate structure GE (e.g., the first direction D1), with the active pattern AP or the sub-gate structures MG_S and GI_S located between them. The upper surface of the source / drain pattern SD can be located at substantially the same level as the upper surface of the active pattern AP relative to the lower surface of the substrate 110, and the upper surface of the active pattern AP is located at the uppermost position among the active patterns AP, but is not limited thereto. The source / drain pattern SD can contact the active pattern AP and the sub-gate structures MG_S and GI_S.

[0085] According to some embodiments, in the second region R2, the dummy source / drain pattern DSD can be located on both sides of the dummy pattern DP and / or the dummy sub-gate structures DMG_S and DGI_S. Specifically, two dummy source / drain pattern DSDs can be arranged along a direction intersecting the direction of the dummy gate structure DGE (e.g., a first direction D1), with the dummy pattern DP or the dummy sub-gate structures DMG_S and DGI_S located between them. The upper surface of the dummy source / drain pattern DSD can be located at substantially the same height as the upper surface of the dummy pattern DP relative to the lower surface of the substrate 110, which is located at the highest point of the dummy pattern DP, but is not limited thereto. The dummy source / drain pattern DSD can contact the dummy pattern DP and the dummy sub-gate structures DMG_S and DGI_S.

[0086] According to some embodiments, the side surfaces of the source / drain pattern SD and the dummy source / drain pattern DSD may have nonlinear shapes (e.g., uneven embossed shapes). In some embodiments, the sides of the source / drain pattern SD and the dummy source / drain pattern DSD may have wavy profiles. For example, the side of the source / drain pattern SD adjacent to the sub-gate structures MG_S and GI_S may have a convex shape toward the sub-gate structures MG_S and GI_S, and the side of the source / drain pattern SD adjacent to the active pattern AP may have a concave shape toward the active pattern AP. Additionally, for example, the side of the dummy source / drain pattern DSD adjacent to the dummy sub-gate structures DMG_S and DGI_S may have a convex shape toward the dummy sub-gate structures DMG_S and DGI_S, and the side of the dummy source / drain pattern DSD adjacent to the dummy pattern DP may have a concave shape toward the dummy pattern DP.

[0087] According to some embodiments, the source / drain pattern SD and the dummy source / drain pattern DSD can be epitaxial patterns formed respectively by selective epitaxial growth processes using an active pattern AP and a dummy pattern DP as seeds. According to some embodiments, the source / drain pattern SD and the dummy source / drain pattern DSD can comprise Si or SiGe. However, the materials of the source / drain pattern SD and the dummy source / drain pattern DSD are not limited thereto and can be varied in various ways. The source / drain pattern SD and the dummy source / drain pattern DSD can each serve as the source / drain of a transistor using the active pattern AP and the dummy pattern DP as the channel region.

[0088] According to some embodiments, the source / drain pattern SD and the dummy source / drain pattern DSD may each include multiple layers. However, they are not limited to the above, and the source / drain pattern SD and the dummy source / drain pattern DSD may each be formed as a single layer.

[0089] According to some embodiments, the lower surfaces of the source / drain pattern SD and the dummy source / drain pattern DSD can be located at a lower level relative to the lower surface of the substrate 110 than the lower surfaces of the sub-gate structures MG_S and GI_S and the dummy sub-gate structures DMG_S and DGI_S. For example, as Figure 3 As shown, the lower surfaces of the source / drain pattern SD and the dummy source / drain pattern DSD can be closer to the bottom surface of the substrate 110 than the lower surfaces of the sub-gate structures MG_S and GI_S and the dummy sub-gate structures DMG_S and DGI_S located at the bottommost part, respectively.

[0090] According to some embodiments, the semiconductor device may further include a first interlayer insulating layer 120, a second interlayer insulating layer 130, a third interlayer insulating layer 140, and a fourth interlayer insulating layer 150. According to some embodiments, the semiconductor device may further include a contact pattern CA, a contact via CAV, and a gate contact pattern CB on a first region R1, and a dummy contact pattern DCA on a second region R2.

[0091] According to some embodiments, the first interlayer insulating layer 120 may be located on the first region R1 and the second region R2 of the substrate 110. According to some embodiments, the first interlayer insulating layer 120 may cover or at least partially overlap the source / drain pattern SD and the dummy source / drain pattern DSD. Additionally, the first interlayer insulating layer 120 may be located between the main gate electrode MG_M and the contact pattern CA, and between the dummy main gate electrode DMG_M and the dummy contact pattern DCA. For example, the first interlayer insulating layer 120 may be located between the gate spacer GS and the contact pattern CA, and between the dummy gate spacer DGS and the dummy contact pattern DCA.

[0092] For example, the first interlayer insulating layer 120 may include silicon oxide. Although the first interlayer insulating layer 120 is shown as a single film, it is not limited thereto, and the first interlayer insulating layer 120 may be formed of a multilayer film with multiple layers stacked on top of each other.

[0093] According to some embodiments, the second interlayer insulating layer 130 may be located on the first interlayer insulating layer 120. For example, the second interlayer insulating layer 130 may be located on the main gate electrode MG_M and the dummy main gate electrode DMG_M, and cover or at least partially overlap the main gate electrode MG_M and the dummy main gate electrode DMG_M. In other words, the second interlayer insulating layer 130 may replace the gate cap pattern and the upper insulating pattern.

[0094] For example, the second interlayer insulating layer 130 may include silicon nitride. Although the second interlayer insulating layer 130 is shown as a single film, it is not limited thereto, and the second interlayer insulating layer 130 may be formed of a multilayer film with multiple layers stacked.

[0095] According to some embodiments, the third interlayer insulating layer 140 may be located on the second interlayer insulating layer 130. Additionally, the third interlayer insulating layer 140 may be located between the contact pattern CA and the gate contact pattern CB, and between the dummy contact pattern DCA. For example, the third interlayer insulating layer 140 may comprise silicon oxide. Although the third interlayer insulating layer 140 is shown as a single film, it is not limited thereto, and the third interlayer insulating layer 140 may be formed of a multilayer film with multiple layers stacked.

[0096] According to some embodiments, the fourth interlayer insulation layer 150 may be located on the third interlayer insulation layer 140. For example, the fourth interlayer insulation layer 150 may be located on the contact pattern CA and the dummy contact pattern DCA, and cover or at least partially overlap the contact pattern CA and the dummy contact pattern DCA.

[0097] According to some embodiments, the fourth interlayer insulating layer 150 may have upper and lower portions facing each other in the third direction D3. The lower portion of the fourth interlayer insulating layer 150 is closer to the substrate 110 than the upper portion. With reference to the substrate 110, the lower level of the fourth interlayer insulating layer 150 may be substantially the same as the upper level of the contact pattern CA and the dummy contact pattern DCA. In other words, the lower portion of the fourth interlayer insulating layer 150 and the upper portions of the contact pattern CA and the dummy contact pattern DCA may be located at the same level on the third direction D3, at or relative to the substrate 110.

[0098] According to some embodiments, the fourth interlayer insulating layer 150 may have a predetermined thickness along the third direction D3 from the upper portion of the contact pattern CA to the lower portion of the upper wiring region FS. According to some embodiments, the fourth interlayer insulating layer 150 on the first region R1 of the substrate 110 may have a through-hole that opens or extends in the third direction D3. In other words, the through-hole on the first region R1 of the substrate 110 may penetrate the fourth interlayer insulating layer 150 from bottom to top in the third direction D3 or extend into the fourth interlayer insulating layer 150. According to some embodiments, the fourth interlayer insulating layer 150 on the second region R2 of the substrate 110 may not have a through-hole that opens or extends in the third direction D3.

[0099] According to some embodiments, the contact via CAV and the gate contact pattern CB can be inserted into the through-hole of the fourth interlayer insulating layer 150. In other words, the through-hole of the fourth interlayer insulating layer 150 can be arranged at a position where the contact via CAV and the gate contact pattern CB at least partially overlap along the third direction D3.

[0100] According to some embodiments, the width of the through-hole into which the contact via CAV is inserted in the first direction D1 can be substantially the same as the maximum width of the contact pattern CA in the first direction D1. However, this is not a limitation, and the width of the through-hole into which the contact via CAV is inserted in the first direction D1 can be less than the maximum width of the contact pattern CA in the first direction D1. Additionally, the width of the through-hole into which the gate contact pattern CB is inserted in the first direction D1 can be substantially the same as the maximum width of the main gate electrode MG_M in the first direction D1. However, this is not a limitation, and the width of the through-hole into which the gate contact pattern CB is inserted in the first direction D1 can be less than the maximum width of the main gate electrode MG_M in the first direction D1.

[0101] For example, the fourth interlayer insulating layer 150 may include silicon nitride. Although the fourth interlayer insulating layer 150 is shown as a single film, it is not limited thereto, and the fourth interlayer insulating layer 150 may be formed of a multilayer film with multiple layers stacked.

[0102] According to some embodiments, the contact pattern CA may be located on at least one of the source / drain patterns SD on the first region R1 of the substrate 110. According to some embodiments, the dummy contact pattern DCA may be located on at least one of the dummy source / drain patterns DSD on the second region R2 of the substrate 110.

[0103] According to some embodiments, a contact pattern CA may penetrate or extend into the first interlayer insulating layer 120, the second interlayer insulating layer 130, and the third interlayer insulating layer 140, and be connected to at least one of the source / drain patterns SD. According to some embodiments, a dummy contact pattern DCA may penetrate the first interlayer insulating layer 120, the second interlayer insulating layer 130, and the third interlayer insulating layer 140 and be connected to at least one of the dummy source / drain patterns DSD.

[0104] According to some embodiments, the contact pattern CA and the dummy contact pattern DCA can be positioned adjacent to the main gate electrode MG_M and the dummy main gate electrode DMG_M, respectively, along the first direction D1. According to some embodiments, the contact pattern CA can electrically connect at least some of the upper wirings FM1, FM2, FM3, FM4, FM5, FM6, FM7, FM8, FM9, FM10, FM11, FM12, FM13, FM14, and FM15 located in the upper wiring region FS to at least one of the source / drain patterns SD. According to some embodiments, the dummy contact pattern DCA may not electrically connect the upper wirings FM1 to FM15 located in the upper wiring region FS to the dummy source / drain pattern DSD. In other words, the dummy source / drain pattern DSD can be electrically isolated from the upper wirings FM1 to FM15.

[0105] For example, the contact pattern CA and the dummy contact pattern DCA may include at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, or a two-dimensional material (2D material). The metal may include at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), or platinum (Pt). The conductive metal nitride may include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), or platinum nitride (PtN).

[0106] According to some embodiments, the gate contact pattern CB may be located on at least one of the main gate structures MG_M and GI_M on the first region R1 of the substrate 110. According to some embodiments, the gate contact pattern CB may not be located on the dummy main gate structures DMG_M and DGI_M on the second region R2 of the substrate 110.

[0107] According to some embodiments, the gate contact pattern CB can be connected to at least one of the main gate electrodes MG_M through the second interlayer insulating layer 130, the third interlayer insulating layer 140 and the fourth interlayer insulating layer 150.

[0108] According to some embodiments, the gate contact pattern CB can electrically connect at least some of the upper wirings FM1 to FM15 located in the upper wiring regions FS below to at least one of the main gate electrodes MG_M. For example, the gate contact pattern CB can include aluminum, copper, tungsten, molybdenum, cobalt, or combinations thereof.

[0109] According to some embodiments, the semiconductor device may also include an upper wiring region FS located above the fourth interlayer insulating layer 150.

[0110] According to some embodiments, the upper wirings FM1 to FM15, the upper vias, and the upper insulating layer 310 may be located in the upper wiring area FS. The upper wirings FM1 to FM15 and the upper vias may include metal (copper in some embodiments).

[0111] A semiconductor device according to some embodiments may include at least one of the top wirings FM1 to FM15 extending onto a second region R2. For example, the first dummy wiring 210 may extend from a fifth top wiring FM5 and be located on the second region R2. Unlike the figures, a plurality of first dummy wirings 210 may be located on the second region R2, and for example, some of the plurality of first dummy wirings 210 may be located on the same layer as the fifth top wiring FM5, while others may be located on a different layer than the fifth top wiring FM5.

[0112] According to some embodiments, the first dummy wiring 210 may extend from at least one of the upper wirings FM1 to FM15 and protrude into or extend into the second region R2. In other words, the endpoints or ends of the first dummy wiring 210 may be located within or on the second region R2.

[0113] According to some embodiments, the first dummy wiring 210 may be integrally formed with at least one of the upper wirings FM1 to FM15. In other words, the boundary between the first dummy wiring 210 and the upper wiring connected to the first dummy wiring 210 may not be identifiable or distinguishable.

[0114] According to some embodiments, one side of the first dummy wiring 210 may be connected to at least one of the upper wirings FM1 to FM15, and the other side of the first dummy wiring 210 may be located within or on the second region R2. Therefore, the other side of the first dummy wiring 210 may be at least partially surrounded by the upper insulating layer 310 and may not be connected to other conductive layers. The endpoints or ends of wirings connected to and not connected to the first dummy wiring 210 may be located within or on the first region R1.

[0115] The upper insulating layer 310 may be located between the upper wirings FM1 to FM15 and the upper vias to insulate them. The upper insulating layer 310 may cover the fourth interlayer insulating layer 150. The upper wirings FM1 to FM15 and the upper vias may be located within the upper insulating layer 310.

[0116] For example, the upper insulating layer 310 may include at least one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), or a low dielectric layer.

[0117] According to some embodiments, at least a portion of the upper wirings FM1 to FM15 may be electrically connected to at least one of the source / drain patterns SD and the main gate electrode MG_M. According to some embodiments, the upper wirings FM1 to FM15 may not be electrically connected to the dummy main gate electrode DMG_M and the dummy source / drain pattern DSD. In other words, the dummy main gate electrode DMG_M and the dummy source / drain pattern DSD may be electrically isolated from the upper wirings FM1 to FM15.

[0118] According to some embodiments, an externally supplied electrical signal or power supply voltage can be provided to the source / drain pattern SD through the upper wirings FM1 to FM15 and the contact pattern CA connected thereto. According to some embodiments, an externally supplied electrical signal or power supply voltage can be provided to the main gate electrode MG_M through the upper wirings FM1 to FM15 and the gate contact pattern CB connected thereto. According to some embodiments, an externally supplied electrical signal or power supply voltage may not be provided to the dummy source / drain pattern DSD and the dummy main gate electrode DMG_M.

[0119] The semiconductor device according to some embodiments may further include a lower contact pattern BCA located below at least one of the source / drain patterns SD and a lower wiring region BS located on the lower surface of the substrate 110.

[0120] According to some embodiments, the lower contact pattern BCA may penetrate or extend into the substrate 110 and be electrically connected to at least one of the source / drain patterns SD on the first region R1. According to some embodiments, the lower contact pattern BCA may not be electrically connected to the dummy source / drain pattern DSD on the second region R2.

[0121] According to some embodiments, the lower contact pattern BCA may be positioned adjacent to the sub-gate electrode MG_S along the first direction D1. According to some embodiments, the lower contact pattern BCA may electrically connect at least some of the lower wirings BM1 to BM8 to at least one of the source / drain patterns SD. According to some embodiments, the lower contact pattern BCA may not electrically connect at least some of the lower wirings BM1, BM2, BM3, BM4, BM5, BM6, BM7, and BM8 to the dummy source / drain pattern DSD.

[0122] For example, the lower contact pattern BCA may include at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, or a two-dimensional material (2D material). The metal may include at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), or platinum (Pt). The conductive metal nitride may include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), or platinum nitride (PtN).

[0123] According to some embodiments, the lower wirings BM1 to BM8, the lower vias, and the lower insulating layer 320 may be located in the lower wiring area BS. The lower wirings BM1 to BM8 and the lower vias may include metal (copper in some embodiments).

[0124] The semiconductor device according to some embodiments may include a second dummy wiring 220 extending from at least one of the lower wirings BM1 to BM8 and located on a second region R2. For example, the second dummy wiring 220 may extend from a third lower wiring BM3 and be located on the second region R2. Unlike what is shown, the second dummy wiring 220 may be connected to any one of the lower wirings BM1 to BM8, and may also be connected to multiple wirings.

[0125] According to some embodiments, the second dummy wiring 220 may extend from at least one of the lower wirings BM1 to BM8 and protrude or extend into the second region R2. In other words, the endpoints or ends of the second dummy wiring 220 may be located within or on the second region R2.

[0126] According to some embodiments, the second dummy wiring 220 may be integrally formed with at least one of the lower wirings BM1 to BM8. In other words, the boundary between the second dummy wiring 220 and the lower wiring connected to the second dummy wiring 220 may not be identifiable or distinguishable.

[0127] According to some embodiments, one side of the second dummy wiring 220 may be connected to at least one of the lower wirings BM1 to BM8, and the other side of the second dummy wiring 220 may be located within or on the second region R2. Therefore, the other side of the second dummy wiring 220 may be at least partially surrounded by the lower insulating layer 320 and may not be connected to any other conductive layer. The ends of wirings connected to and not connected to the second dummy wiring 220 may be located within or on the first region R1.

[0128] According to some embodiments, the lower insulating layer 320 may be located between the lower wirings BM1 to BM8 and the lower vias to insulate them. The lower insulating layer 320 may cover or at least partially overlap the substrate 110. The lower wirings BM1 to BM8 and the lower vias may be located within the lower insulating layer 320.

[0129] For example, the lower insulating layer 320 may include at least one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), or a low dielectric layer.

[0130] According to some embodiments, at least some of the bottom wirings BM1 to BM8 may be electrically connected to at least one of the source / drain patterns SD. According to some embodiments, the bottom wirings BM1 to BM8 may not be electrically connected to the dummy source / drain pattern DSD. In other words, the dummy source / drain pattern DSD may be isolated from the bottom wirings BM1 to BM8.

[0131] According to some embodiments, an externally supplied electrical signal or power supply voltage can be provided to the source / drain pattern SD through the lower wirings BM1 to BM8 and the lower contact pattern BCA connected thereto.

[0132] Figures 5 to 7 This is a cross-sectional view showing a method for performing fault analysis according to some embodiments.

[0133] refer to Figure 5 Semiconductor devices can be provided as objects of fault analysis according to some embodiments. As a method for fault analysis, a method can be used by electrically connecting the source, drain, and gate of the semiconductor device using tungsten pads W and then performing a layer removal process (de-lamination).

[0134] The following describes in detail a method for analyzing defects in a semiconductor device according to the present disclosure through a layer removal process (de-de-lamination).

[0135] According to some embodiments, tungsten pads W can be formed on the second region R2 of the substrate 110. According to some embodiments, the tungsten pads W can be formed to penetrate from the upper portion of the upper insulating layer 310 to the lower portion of the lower insulating layer 320 or to extend into the lower portion of the lower insulating layer 320. However, the formation location of the tungsten pads W is not limited to this and can be changed in various ways as needed. The tungsten pads W can be made of a highly conductive metal and can still provide stable electrical connections even after a layer removal process (delamination).

[0136] According to some embodiments, the tungsten pad W can be connected to at least one of the upper wirings FM1 to FM15 extending onto the second region R2, and to at least one of the lower wirings BM1 to BM8 extending onto the second region R2, and to a second dummy wiring 220. Figure 5 As shown, the tungsten pad W can be connected to either the first dummy wiring 210 or the second dummy wiring 220.

[0137] According to some embodiments, the electrical characteristics of a semiconductor device can be initially measured when the tungsten pad W is connected to the first dummy wiring 210 and / or the second dummy wiring 220. The electrical characteristics of the semiconductor device can also be initially measured by connecting the semiconductor device to an external test device via probes or wiring connections electrically connected to the tungsten pad W.

[0138] According to some embodiments, the initial measurement targets may include the current between the source and drain, the gate leakage current, and the resistance value between each electrode. For example, by measuring the drain current, the presence of a short circuit or leakage can be determined. For example, the gate leakage current can be measured to detect insulation defects. For example, the resistance value between each electrode can be measured to check for defective connections.

[0139] Next, the upper layers of the device can be sequentially removed using chemical etching or mechanical polishing. After each layer removal, the electrical signals of the device are repeatedly measured through the tungsten pads W. This allows determination of whether an electrical anomaly has occurred in a particular layer.

[0140] refer to Figure 6 When the tungsten pad W is connected to the first dummy wiring 210, the layer removal process in the lower wiring area BS can be used.

[0141] although Figure 6 Not explicitly shown, but the first dummy wiring 210 can extend from the upper wiring connected to the source / drain pattern SD and / or the main gate electrode MG_M. Therefore, the tungsten pad W can be connected to the first dummy wiring 210, which is connected to the source / drain pattern SD. In some embodiments, the tungsten pad W can be connected to the first dummy wiring 210, which is connected to the main gate electrode MG_M. In some embodiments, the tungsten pad W can be connected to both the first dummy wiring 210 connected to the source / drain pattern SD and the first dummy wiring 210 connected to the main gate electrode MG_M. In other words, the tungsten pad W can be connected separately or together (or simultaneously) to both the first dummy wiring 210 connected to the source / drain pattern SD and the first dummy wiring 210 connected to the main gate electrode MG_M.

[0142] In addition, although Figure 6Not explicitly shown, but according to some embodiments, the semiconductor device may include a lower gate contact pattern (not shown) connected to the sub-gate electrode MG_S. Therefore, when the tungsten pad W is connected to the first dummy wiring 210, even if the layer is sequentially removed from the lower wiring region BS, the electrical characteristics of the semiconductor device can still be maintained due to the source, drain, and gate connections.

[0143] As described above, since the semiconductor device according to some embodiments of this disclosure includes at least one extension from the upper wiring FM1 to FM15 and is located in the exclusion region (e.g., Figure 3 The first dummy wiring 210 in the second region R2) thus facilitates defect analysis by the layer removal process (de-layering) even if the layer is removed sequentially from the lower wiring region BS, by connecting the source, drain and gate via the tungsten pad W.

[0144] refer to Figure 7 When the tungsten pad W is connected to the second dummy wiring 220, the layer removal process in the upper wiring area FS can be utilized.

[0145] According to some embodiments, when the tungsten pad W is connected to the second dummy wiring 220, even if the layer is sequentially removed from the top of the upper wiring region FS, the electrical characteristics of the semiconductor device can still be maintained due to the source, drain and gate connections.

[0146] As described above, since the semiconductor device according to some embodiments of this disclosure includes at least one of the lower wirings BM1 to BM8 extending and located in the exclusion region (e.g., Figure 3 The second dummy wiring 220 in the second region R2) therefore facilitates defect analysis by the layer removal process (de-layering) even if the layer is removed sequentially from the top of the upper wiring region FS, by connecting the source, drain and gate via the tungsten pad W.

[0147] Figure 8 According to some embodiments Figure 2 A cross-sectional view taken from line A-A'. Figure 9 According to some embodiments Figure 2 The cross-sectional view taken by line B-B'.

[0148] Figure 8 and Figure 9 The semiconductor device shown may include reference Figures 1 to 7 The semiconductor devices described are similar to or identical to the components described. However, with Figures 1 to 7 The structure shown is different. The semiconductor device in this embodiment has a first dummy wiring 210 that is connected to at least one of the upper wirings FM1 to FM15, but does not include a dummy wiring that is connected to at least one of the lower wirings BM1 to BM8 (e.g., Figure 3The structure of the second dummy wiring (220). Here, the content that is repeated above will be briefly explained or omitted, and the differences will be mainly explained.

[0149] A semiconductor device according to some embodiments may include at least one of the top wirings FM1 to FM15 extending onto a second region R2. For example, the first dummy wiring 210 may extend from a fifth top wiring FM5 and be located on the second region R2. Unlike what is shown in the figures, multiple first dummy wirings 210 may be located on the second region R2, and for example, some of the multiple first dummy wirings 210 may be located on the same layer as the fifth top wiring FM5, while others may be located on different layers from the fifth top wiring FM5.

[0150] According to some embodiments, the first dummy wiring 210 may extend from at least one of the upper wirings FM1 to FM15 and protrude into or extend into the second region R2. In other words, the endpoints or ends of the first dummy wiring 210 may be located within or on the second region R2.

[0151] According to some embodiments, the first dummy wiring 210 may be integrally formed with at least one of the upper wirings FM1 to FM15. In other words, the boundary between the first dummy wiring 210 and the upper wiring connected to the first dummy wiring 210 may not be identifiable or distinguishable.

[0152] According to some embodiments, one side of the first dummy wiring 210 may be connected to at least one of the upper wirings FM1 to FM15, and the other side of the first dummy wiring 210 may be located within or on the second region R2. Therefore, the other side of the first dummy wiring 210 may be at least partially surrounded by the upper insulating layer 310 and may not be connected to other conductive layers. The ends of wirings connected to and not connected to the first dummy wiring 210 may be located within or on the first region R1.

[0153] According to some embodiments, the first dummy wiring 210 may be connected to the upper wiring FM1 to FM15 located at the shortest distance from the second region R2 along the first direction D1. For example, the first dummy wiring 210 may be connected to the fifth upper wiring FM5 located at the shortest end of the upper wiring FM1 to FM15 located from the second region R2.

[0154] As described above, the semiconductor device according to some embodiments of this disclosure includes a first dummy wiring 210 connected to one of the upper wirings FM1 to FM15 located at the shortest distance from the second region R2 along the first direction D1, thereby minimizing the length of the first dummy wiring 210. Therefore, performance degradation of the semiconductor device due to the first dummy wiring 210 can be minimized or suppressed.

[0155] According to some embodiments, although not explicitly shown, the first dummy wiring 210 may be connected to the upper wiring FM1 to FM15 that is connected to most of the source / drain patterns SD and / or the main gate electrode MG_M (e.g., the first dummy wiring 210 is electrically connected to most (e.g., more than half) of the source / drain patterns SD and / or the main gate electrode MG_M).

[0156] As described above, a semiconductor device according to some embodiments of the present disclosure may include a first dummy wiring 210 connected to one of the upper wirings FM1 to FM15 connected to the maximum number of source / drain patterns SD and / or main gate electrodes MG_M, thereby improving the accuracy of analysis in defect analysis using a layer removal process (de-layering).

[0157] According to some embodiments, a semiconductor device may not include at least one dummy wiring extending from the lower wiring BM1 to BM8 and located on the second region R2 (e.g., Figure 3 The second dummy wiring 220).

[0158] According to some embodiments, the ends of the lower wirings BM1 to BM8 may not be located within or on the second region R2. In other words, the lower wirings BM1 to BM8 may not protrude into or extend into the second region R2.

[0159] In some embodiments, when the semiconductor device includes a first dummy wiring 210 and does not include at least one dummy wiring extending from the lower wiring BM1 to BM8 and located on the second region R2, reference is made to... Figure 6 As described above, a layer removal process (layer removal) can be used to sequentially remove layers from the bottom of the lower wiring area BS.

[0160] Figure 10 According to some embodiments Figure 2 A cross-sectional view taken from line A-A'. Figure 11 According to some embodiments Figure 2 The cross-sectional view taken by line B-B'.

[0161] Figure 10 and Figure 11 The semiconductor device shown may include reference Figures 1 to 7The semiconductor devices described are similar to or identical to the components described. However, with Figures 1 to 7 The structure shown is different. The semiconductor device in this embodiment has a second dummy wiring 220 that is connected to at least one of the lower wirings BM1 to BM8, but does not include a dummy wiring that is connected to at least one of the upper wirings FM1 to FM15 (e.g., Figure 3 The structure of the first dummy wiring 210).

[0162] Here, we will briefly explain or omit the content that is repeated above, and mainly explain the differences.

[0163] The semiconductor device according to some embodiments may include a second dummy wiring 220 extending from at least one of the lower wirings BM1 to BM8 and located on a second region R2. For example, the second dummy wiring 220 may extend from a third lower wiring BM3 and be located on the second region R2. As shown, the second dummy wiring 220 may be connected to any one of the lower wirings BM1 to BM8, and may also be connected to multiple wirings.

[0164] According to some embodiments, the second dummy wiring 220 may extend from at least one of the lower wirings BM1 to BM8 and protrude or extend into the second region R2. In other words, the endpoints or ends of the second dummy wiring 220 may be located within or on the second region R2.

[0165] According to some embodiments, the second dummy wiring 220 may be integrally formed with at least one of the lower wirings BM1 to BM8. In other words, the boundary between the second dummy wiring 220 and the lower wiring connected to the second dummy wiring 220 may not be identifiable or distinguishable.

[0166] According to some embodiments, one side of the second dummy wiring 220 may be connected to at least one of the lower wirings BM1 to BM8, and the other side of the second dummy wiring 220 may be located within or on the second region R2. Therefore, the other side of the second dummy wiring 220 may be at least partially surrounded by the lower insulating layer 320 and may not be connected to any other conductive layer. The ends of wirings connected to and not connected to the second dummy wiring 220 may be located within or on the first region R1.

[0167] According to some embodiments, the second dummy wiring 220 may be connected to one of the lower wirings BM1 to BM8 located at the shortest distance from the second region R2 along the first direction D1. For example, the second dummy wiring 220 may be connected to a third lower wiring BM3 located at the shortest distance from the second region R2 among the lower wirings BM1 to BM8.

[0168] As described above, the length of the semiconductor device according to some embodiments of this disclosure can be minimized or reduced by connecting the second dummy wiring 220 to one of the lower wirings BM1 to BM8 located at the shortest distance from the second region R2 along the first direction D1. Therefore, the performance degradation of the semiconductor device due to the second dummy wiring 220 can be minimized or suppressed.

[0169] According to some embodiments, although not explicitly shown, the second dummy wiring 220 may be connected to the lower wiring BM1 to BM8 that is connected to the majority of the source / drain pattern SD (e.g., the second dummy wiring 220 is electrically connected to the majority of the source / drain pattern SD).

[0170] As described above, the semiconductor device according to some embodiments of the present disclosure includes a second dummy wiring 220 connected to the lower wirings BM1 to BM8 that are connected to the maximum number of source / drain patterns SD, thereby improving the accuracy of analysis during defect analysis using a layer removal process (de-layering).

[0171] According to some embodiments, a semiconductor device may not include at least one dummy wiring extending from the top wiring FM1 to FM15 and located on the second region R2 (e.g., Figure 3 The first dummy wiring 210).

[0172] According to some embodiments, the ends of the upper wirings FM1 to FM15 may not be located within or on the second region R2. In other words, the upper wirings FM1 to FM15 may not protrude into or extend into the second region R2.

[0173] When a semiconductor device according to some embodiments includes a second dummy wiring 220 and does not include at least one dummy wiring extending from the upper wiring FM1 to FM15 and located on the second region R2, the above reference can be used. Figure 7 The described layer removal process (layer removal) involves sequentially removing layers from the upper part of the upper wiring area FS.

[0174] Figure 12 According to some embodiments Figure 2 A cross-sectional view taken from line A-A'. Figure 13 According to some embodiments Figure 2 The cross-sectional view taken by line B-B'.

[0175] Figure 12 and Figure 13 The semiconductor device shown may include reference Figures 1 to 7 The semiconductor devices described are similar to or identical to the components described. However, with Figures 1 to 7The structure shown is different. The semiconductor device in this embodiment has a structure including a first dummy wiring 210 connected to multiple wirings among the upper wirings FM1 to FM15 and a second dummy wiring 220 connected to multiple wirings among the lower wirings BM1 to BM8. Here, the content repeated above will be briefly described or omitted, and the differences will be mainly explained.

[0176] A semiconductor device according to some embodiments may include a first dummy line 210 extending from multiple lines among upper wirings FM1 to FM15 and located on a second region R2. According to some embodiments, the first dummy line 210 may include eleventh to sixteenth dummy lines 210a, 210b, 210c, 210d, 210e, and 210f. For example, the eleventh to sixteenth dummy lines 210a, 210b, 210c, 210d, 210e, and 210f may be located on the second region R2 by extending from the first upper wiring FM1, the third upper wiring FM3, the fifth upper wiring FM5, the seventh upper wiring FM7, the thirteenth upper wiring FM13, and the fifteenth upper wiring FM15, respectively. However, Figure 12 and Figure 13 The following are not limited to this, and the connection relationship of the first dummy wiring 210 can be changed in various ways.

[0177] According to some embodiments, the eleventh to sixteenth dummy wires 210a, 210b, 210c, 210d, 210e, and 210f can extend from the first upper wire FM1, the third upper wire FM3, the fifth upper wire FM5, the seventh upper wire FM7, the thirteenth upper wire FM13, and the fifteenth upper wire FM15, respectively, and protrude into or extend into the second region R2. In other words, the endpoints or ends of the eleventh to sixteenth dummy wires 210a, 210b, 210c, 210d, 210e, and 210f can be located within or on the second region R2.

[0178] According to some embodiments, the eleventh to sixteenth dummy wirings 210a, 210b, 210c, 210d, 210e and 210f can be integrally formed with the first upper wiring FM1, the third upper wiring FM3, the fifth upper wiring FM5, the seventh upper wiring FM7, the thirteenth upper wiring FM13 and the fifteenth upper wiring FM15, respectively.

[0179] According to some embodiments, the first sides of the eleventh to sixteenth dummy wirings 210a, 210b, 210c, 210d, 210e and 210f can be connected to the first upper wiring FM1, the third upper wiring FM3, the fifth upper wiring FM5, the seventh upper wiring FM7, the thirteenth upper wiring FM13 and the fifteenth upper wiring FM15 respectively, and the second sides of the eleventh to sixteenth dummy wirings 210a, 210b, 210c, 210d, 210e and 210f can be located within or on the second region R2.

[0180] Figure 14 This is a top view of a semiconductor device according to some embodiments. Figure 15 According to some embodiments Figure 14 A magnified view of region N. Figure 16 According to some embodiments Figure 15 A cross-sectional view taken from line A-A'. Figure 17 According to some embodiments Figure 15 A cross-sectional view taken from line A-A'. Figure 18 According to some embodiments Figure 15 The cross-sectional view taken by line B-B'.

[0181] Figures 14 to 18 The semiconductor device shown may include reference Figures 1 to 13 The semiconductor devices described are similar to or identical to the components described. However, the semiconductor devices in this embodiment are... Figures 1 to 13 The semiconductor device shown differs in that it has a structure in which the exclusion region is located within or between multiple cell regions of the substrate. Here, content repeated above will be briefly described or omitted, and the main focus will be on the differences.

[0182] refer to Figure 14 A semiconductor wafer may include semiconductor chip regions and scribe lines (SLs) situated between the semiconductor chip regions. Additionally, the semiconductor chip regions may include cell regions (CRs) and peripheral regions (PRs). (See above reference.) Figure 1 Specific descriptions related to each region are provided, so these specific descriptions can be simplified or omitted.

[0183] According to some embodiments, the semiconductor chip region CHIP may include multiple cell regions CR. According to some embodiments, each of the multiple cell regions CR may include: a component region AR, in which an activation pattern AP, gate electrodes MG_M1, MG_S1, MG_M2 and MG_S2, and source / drain patterns SD1 and SD2 are located; and a dummy region DR, in which a dummy pattern DP, dummy gate electrodes DMG_M and DMG_S, and a dummy source / drain pattern DSD are located.

[0184] refer to Figures 15 to 17 A substrate 110 may be provided, comprising an eleventh region R11, a twelfth region R12, and a second region R2. According to some embodiments, the eleventh region R11 and the twelfth region R12 may be... Figure 14 Any region within the component area AR, and the second region R2 can be Figure 14 Any region within the dummy region DR. In this disclosure, for better understanding and ease of description, the eleventh region R11 and the twelfth region R12 are depicted and described separately, but the eleventh region R11 and the twelfth region R12 are any regions within the element region AR, and their boundaries may not be explicitly defined. In this disclosure, the eleventh region R11 and the twelfth region R12 may correspond to regions including electrically active transistors, and the second region R2 may correspond to regions including electrically passive transistors.

[0185] In this disclosure, the second region R2 may be referred to as an exclusion region. An exclusion region may refer to a region designed so that wiring is not intentionally connected to a transistor.

[0186] According to some embodiments, the eleventh region R11 and the twelfth region R12 may be located on both sides of the second region R2. According to some embodiments, the dummy gate structure DGE, described later, on the second region R2 may be arranged sequentially and spaced apart from each other in the first direction D1. Therefore, the dummy gate structure DGE may be located on the two edges of the second region R2.

[0187] According to some embodiments, the semiconductor device may include: a first activation pattern AP1, spaced apart along a first direction D1 in an eleventh region R11 and on a first surface of a substrate 110; a first source / drain pattern SD1, connected to both sides of the first activation pattern AP1; and a first gate structure GE1, extending around or around the first activation pattern AP1 and extending in a second direction D2. According to some embodiments, the first gate structure GE1 may include a plurality of first sub-gate structures MG_S1 and GI_S1 and a first main gate structure MG_M1 and GI_M1. According to some embodiments, the first sub-gate structures MG_S1 and GI_S1 may include a first sub-gate electrode MG_S1 and a first sub-gate insulating layer GI_S1. According to some embodiments, the first main gate structures MG_M1 and GI_M1 may include a first main gate electrode MG_M1 and a first main gate insulating layer GI_M1.

[0188] According to some embodiments, the semiconductor device may include: a second activation pattern AP2, spaced apart along a first direction D1 in or on a twelfth region R12 and on a first surface of substrate 110; a second source / drain pattern SD2, connected to both sides of the second activation pattern AP2; and a second gate structure GE2, extending in a second direction D2 and surrounding or around the second activation pattern AP2. According to some embodiments, the second gate structure GE2 may include a plurality of second sub-gate structures MG_S2 and GI_S2 and a second main gate structure MG_M2 and GI_M2. According to some embodiments, the second sub-gate structures MG_S2 and GI_S2 may include a second sub-gate electrode MG_S2 and a second sub-gate insulating layer GI_S2. According to some embodiments, the second main gate structures MG_M2 and GI_M2 may include a second main gate electrode MG_M2 and a second main gate insulating layer GI_M2.

[0189] According to some embodiments, the semiconductor device may further include a via TSV located in or on the twelfth region R12. According to some embodiments, the via TSV may extend on the third direction D3 and electrically connect the lower wirings BM1 to BM8 to the upper wirings FM1 to FM15. The number and arrangement of the via TSVs may vary.

[0190] According to some embodiments, the semiconductor device may include: a dummy pattern DP, spaced apart along a first direction D1 in or on a second region R2 and on a first surface of substrate 110; a dummy source / drain pattern DSD, connected to both sides of the dummy pattern DP; and a dummy gate structure DGE, extending around or around the dummy pattern DP and extending along a second direction D2. According to some embodiments, the dummy gate structure DGE may include a plurality of dummy sub-gate structures DMG_S and DGI_S, and dummy main gate structures DMG_M and DGI_M. According to some embodiments, the dummy sub-gate structures DMG_S and DGI_S may include a dummy sub-gate electrode DMG_S and a dummy sub-gate insulating layer DGI_S. According to some embodiments, the dummy main gate structures DMG_M and DGI_M may include a dummy main gate electrode DMG_M and a dummy main gate insulating layer DGI_M.

[0191] The semiconductor device according to some embodiments may further include a first gate spacer GS1, a second gate spacer GS2, and a dummy gate spacer DGS, respectively, in or on the eleventh region R11, the twelfth region R12, and the second region R2. According to some embodiments, the semiconductor device may further include a first interlayer insulating layer 120, a second interlayer insulating layer 130, a third interlayer insulating layer 140, and a fourth interlayer insulating layer 150. According to some embodiments, the semiconductor device may include a first contact pattern CA1, a first contact via CAV1, and a first gate contact pattern CB1 on the eleventh region R11; a second contact pattern CA2 and a second contact via CAV2 on the twelfth region R12; and a dummy contact pattern DCA on the second region R2. Although not shown, the semiconductor device according to some embodiments may further include a second gate contact pattern on at least one of the second main gate structures MG_M2 and GI_M2 located on the twelfth region R12.

[0192] Above Figures 2 to 13 Specific descriptions related to the above components are provided, therefore these descriptions may be simplified or omitted. For example, the components located in eleventh region R11 and twelfth region R12 can correspond to the above reference. Figures 2 to 13 The component described is located in the first region R1. Additionally, for example, a component located in the second region R2 may correspond to the component mentioned above. Figures 2 to 13 The components on the second region R2 as described.

[0193] refer to Figure 16 and Figure 17 According to some embodiments, the semiconductor device may also include an upper wiring region FS located above the fourth interlayer insulating layer 150.

[0194] According to some embodiments, the upper wiring FM1 to FM15, the upper via, and the upper insulating layer 310 may be located in the upper wiring area FS.

[0195] refer to Figure 16 According to some embodiments, a semiconductor device may include at least one of the upper wirings FM1 to FM15 extending from the eleventh region R11 and located on the second region R2. For example, the eleventh dummy wiring 211a may extend from the fifth upper wiring FM5 on the eleventh region R11 and located on the second region R2.

[0196] The semiconductor device according to some embodiments may include a twelfth dummy wiring 211b extending from at least one of the upper wirings FM1 to FM15 on the twelfth region R12 and located on the second region R2. For example, the twelfth dummy wiring 211b may extend from the fifth upper wiring FM5 on the twelfth region R12 and located on the second region R2.

[0197] According to some embodiments, the eleventh dummy wiring 211a and the twelfth dummy wiring 211b may extend from at least one of the upper wirings FM1 to FM15 on the eleventh region R11 and the twelfth region R12, respectively, and protrude into or extend into the second region R2. In other words, the endpoints of the eleventh dummy wiring 211a and the twelfth dummy wiring 211b may be located within or on the second region R2.

[0198] According to some embodiments, the eleventh dummy wiring 211a and the twelfth dummy wiring 211b can be integrally formed with at least one of the upper wirings FM1 to FM15 on the eleventh region R11 and the twelfth region R12, respectively. In other words, the boundary between the eleventh dummy wiring 211a and the wiring on the eleventh region R11 connected to the eleventh dummy wiring 211a may not be identifiable or distinguishable. In other words, the boundary between the twelfth dummy wiring 211b and the wiring on the twelfth region R12 connected to the twelfth dummy wiring 211b may not be identifiable or distinguishable.

[0199] According to some embodiments, one side of each of the eleventh dummy wiring 211a and the twelfth dummy wiring 211b may be connected to at least one of the upper wirings FM1 to FM15 on the eleventh region R11 and the twelfth region R12, and the other side of each of the eleventh dummy wiring 211a and the twelfth dummy wiring 211b may be located in or on the second region R2.

[0200] The semiconductor device according to some embodiments may further include a first lower contact pattern BCA1 located below at least one of the first source / drain patterns SD1, a second lower contact pattern BCA2 located below at least one of the second source / drain patterns SD2, and a lower wiring region BS located on the lower surface of the substrate 110.

[0201] The above reference Figures 2 to 13 Specific descriptions related to the above components are provided, therefore these descriptions may be simplified or omitted. For example, components located in eleventh region R11 and twelfth region R12 can correspond to references. Figures 2 to 13 The component described is located in the first region R1. Additionally, for example, a component located in the second region R2 may correspond to the component mentioned above. Figures 2 to 13 The components on the second region R2 as described.

[0202] According to some embodiments, the lower wiring BM1 to BM8, the lower via, and the lower insulating layer 320 may be located in the lower wiring area BS.

[0203] refer to Figure 16According to some embodiments, a semiconductor device may include at least one of the lower wirings BM1 to BM8 on an eleventh region R11, extending onto a second region R2, and a second dummy wiring 221a. For example, the second dummy wiring 221a may extend from a third lower wiring BM3 on an eleventh region R11 and be located on the second region R2.

[0204] According to some embodiments, a semiconductor device may include a second dummy wiring 221b extending from at least one of the lower wirings BM1 to BM8 on a twelfth region R12 and located on a second region R2. For example, the second dummy wiring 221b may extend from a third lower wiring BM3 on a twelfth region R12 and located on the second region R2.

[0205] According to some embodiments, the twenty-first dummy wiring 221a and the twenty-second dummy wiring 221b may extend from at least one of the lower wirings BM1 to BM8 on the eleventh region R11 and the twelfth region R12, respectively, and protrude into or extend into the second region R2. In other words, the endpoint of each of the twenty-first dummy wiring 221a and the twenty-second dummy wiring 221b may be located within or on the second region R2.

[0206] According to some embodiments, the twenty-first dummy wiring 221a and the twenty-second dummy wiring 221b can be integrally formed with at least one of the lower wirings BM1 to BM8 on the eleventh region R11 and the twelfth region R12, respectively. In other words, the boundary between the twenty-first dummy wiring 221a and the lower wiring on the eleventh region R11 connected to the twenty-first dummy wiring 221a may not be identifiable or distinguishable. In other words, the boundary between the twenty-second dummy wiring 221b and the lower wiring on the twelfth region R12 connected to the twenty-second dummy wiring 221b may not be identifiable or distinguishable.

[0207] According to some embodiments, one side of each of the twenty-first dummy wiring 221a and the twenty-second dummy wiring 221b may be connected to at least one of the lower wirings BM1 to BM8 on the eleventh region R11 and the twelfth region R12, and the other side of each of the twenty-first dummy wiring 221a and the twenty-second dummy wiring 221b may be located in or on the second region R2.

[0208] refer to Figure 17According to some embodiments, the semiconductor device may include a first dummy wiring 210 and / or a second dummy wiring 220, which extend along a first direction D1 across a second region R2 and are connected to at least one of a first source / drain pattern SD1 and at least one of a second source / drain pattern SD2. Unlike the figures, the first dummy wiring 210 may be connected to any of the upper wirings FM1 to FM15, and may also be connected to multiple wirings. Additionally, unlike the figures shown, the second dummy wiring 220 may be connected to any of the lower wirings BM1 to BM8, and may also be connected to multiple wirings.

[0209] According to some embodiments, the first dummy wiring 210 may extend from at least one of the upper wirings FM1 to FM15 on the eleventh region R11 and cross the second region R2 along the first direction D1 to connect to at least one of the upper wirings FM1 to FM15 on the twelfth region R12. For example, the first dummy wiring 210 may extend from the fifth upper wiring FM5 on the eleventh region R11 and cross the second region R2 along the first direction D1 to connect to the fifth upper wiring FM5 on the twelfth region R12.

[0210] According to some embodiments, the second dummy wiring 220 may extend from at least one of the lower wirings BM1 to BM8 on the eleventh region R11 and cross the second region R2 along the first direction D1 to connect to at least one of the lower wirings BM1 to BM8 on the twelfth region R12. For example, the second dummy wiring 220 may extend from a third lower wiring BM3 on the eleventh region R11 and cross the second region R2 along the first direction D1 to connect to a third lower wiring BM3 on the twelfth region R12.

[0211] According to some embodiments, the first dummy wiring 210 may be integrally formed with at least one of the upper wirings FM1 to FM15. The boundary between the first dummy wiring 210 and the upper wiring connected thereto may be invisible or indistinguishable. For example, one side of the first dummy wiring 210 may be connected to the fifth upper wiring FM5 on the eleventh region R11, and the other side of the first dummy wiring 210 may be connected to the fifth upper wiring FM5 on the twelfth region R12.

[0212] According to some embodiments, the second dummy wiring 220 may be integrally formed with at least one of the lower wirings BM1 to BM8. The boundary between the second dummy wiring 220 and the lower wiring connected thereto may be invisible or indistinguishable. For example, one side of the second dummy wiring 220 may be connected to the third lower wiring BM3 on the eleventh region R11, and the other side of the second dummy wiring 220 may be connected to the third lower wiring BM3 on the twelfth region R12.

[0213] refer to Figure 18 At least a portion of the dummy gate electrode DMG can be located on a structure in which dummy sub-gate electrodes DMG_S and dummy patterns DP are alternately stacked. Another portion of the dummy gate electrode DMG can be formed to cover or at least partially overlap the two sides of the structure in which dummy sub-gate electrodes DMG_S and dummy patterns DP are alternately stacked. Therefore, the four sides of the plurality of dummy patterns DP can be surrounded by the dummy gate electrode DMG. Although not shown, in the eleventh region R11, the four sides of the plurality of first activation patterns AP1 can be at least partially surrounded by the first gate electrode MG_M1, and in the twelfth region R12, the four sides of the plurality of second activation patterns AP2 can be surrounded by the second gate electrode MG_M2.

[0214] Figure 19 According to some embodiments Figure 14 A magnified view of region N. Figure 20 According to some embodiments Figure 15 A cross-sectional view taken from line A-A'. Figure 21 According to some embodiments Figure 15 The cross-sectional view taken by line B-B'.

[0215] Figures 19 to 21 The semiconductor device shown may include reference Figures 14 to 18 The semiconductor devices described are similar to or identical to the components described. However, the semiconductor devices in this embodiment are... Figures 14 to 18 The semiconductor device shown differs in that, according to some embodiments, it has an element isolation layer SDB that penetrates or extends into the dummy gate structure DGE located at the two edges of the second region R2. Here, content repeated above will be briefly described or omitted, and the main focus will be on the differences.

[0216] According to some embodiments, the semiconductor device may include a device isolation layer (SDB) that physically separates adjacent cells. According to some embodiments, the activation pattern AP1 of the eleventh region R11 and the activation pattern AP2 of the twelfth region R12 may be terminated by the device isolation layer SDB. Additionally, the dummy pattern DP of the second region R2 may be terminated by the device isolation layer SDB. The device isolation layer SDB can be inserted to reduce the influence between adjacent cells, such as local layout effects (LLE), and to isolate impurity-doped regions between adjacent cells. According to some embodiments, the device isolation layer SDB may be made of an insulating material.

[0217] According to some embodiments, the component isolation layer SDB can be positioned adjacent to the edge (or boundary) of the cell. In this disclosure, the component isolation layer SDB is shown as a single diffusion break, but is not limited thereto, and the component isolation layer SDB can also be a double diffusion break.

[0218] According to some embodiments, the element isolation layer SDB may penetrate or extend into the dummy gate structure DGE located at the two edges of the second region R2 along a third direction D3. The width of the element isolation layer SDB (e.g., its length along the first direction D1) may be less than or substantially the same as the width of the dummy gate structure DGE. For example, if the width of the element isolation layer SDB (e.g., its length along the first direction D1) is less than the width of the dummy gate structure DGE, the dummy gate structure DGE, which has not yet been removed, may be located around the element isolation layer SDB. For example, the same material as the dummy gate structure DGE may be positioned to contact the outer side of the element isolation layer SDB. For example, if the width of the element isolation layer SDB (i.e., its length along the first direction D1) is substantially the same as the width of the dummy gate structure DGE, the element isolation layer SDB may be in direct contact with the first interlayer insulating layer 120.

[0219] According to some embodiments, the component isolation layer SDB can physically isolate the two sides of the second region R2 from the regions of other adjacent cells. Therefore, the dummy pattern DP can be removed from the portion where it intersects with the component isolation layer SDB. For example, the component isolation layer SDB may not overlap with (or be in a position to overlap with) the dummy pattern DP.

[0220] For example, a device isolation layer SDB can be formed by removing the dummy gate structure DGE and at least partially filling the removed site with an insulating material. Therefore, for reference, the device isolation layer SDB can be configured such that there is substantially no current flow between the components located on either side of it.

[0221] refer to Figure 19 and Figure 21 According to some embodiments, the semiconductor device may further include a gate isolation structure CT that penetrates or extends into the first gate structure GE1 and the dummy gate electrode DMG. Although not shown, the semiconductor device may also include a gate isolation structure CT that penetrates or extends into the second gate structure GE2. According to some embodiments, the gate isolation structure CT may penetrate or extend into the dummy gate electrode DMG on a third-direction D3.

[0222] According to some embodiments, the gate isolation structure CT can be separated by cutting dummy gate electrodes DMG extending along a second direction (direction D2) with the gate isolation structure (CT) as the center to space them apart. For example, the gate isolation structure CT can be formed of silicon nitride.

[0223] While this disclosure has been described in conjunction with what is now considered to be actual exemplary embodiments, it should be understood that this disclosure is not limited to the disclosed embodiments, but rather is intended to cover various modifications and equivalent arrangements included within the scope of the appended claims.

Claims

1. A semiconductor device, comprising: The substrate includes a first surface and a second surface, a cell region and an exclusion region, wherein the first surface and the second surface are opposite to each other; The active pattern and the dummy pattern are spaced apart from each other in a first direction and are on the first surface of the substrate; The source / drain pattern and the dummy source / drain pattern are respectively connected to the active pattern and the dummy pattern; The gate electrode and the dummy gate electrode extend around the activation pattern and the dummy pattern, respectively, and extend along a second direction intersecting the first direction; On the first surface of the substrate, the upper wiring is on the cell region and connected to at least one first source / drain pattern in the source / drain patterns; The lower wiring is on the second surface of the substrate, on the cell region and connected to at least one second source / drain / pattern in the source / drain pattern; as well as A dummy wiring extends from either the upper wiring or the lower wiring. The dummy gate electrode and the dummy source / drain pattern are insulated from the upper wiring and the lower wiring, and the end of the dummy wiring is on the exclusion region.

2. The semiconductor device according to claim 1, wherein: The substrate also includes a peripheral region extending around the cell region. The activation pattern, the gate electrode, and the source / drain pattern are on the cell region. The dummy pattern, the dummy gate electrode, and the dummy source / drain pattern are on the peripheral region, and The exclusion zone is located in the outer perimeter area.

3. The semiconductor device according to claim 1, wherein: The substrate includes a plurality of unit regions, and the plurality of unit regions include the unit regions, and Each of the plurality of unit regions includes: The component region includes the activation pattern, the gate electrode, and the source / drain pattern; and A dummy region, comprising the dummy pattern, the dummy gate electrode, and the dummy source / drain pattern, and The exclusion zone at least partially overlaps with the dummy zone in a third direction perpendicular to the first and second directions.

4. The semiconductor device of claim 3, further comprising an element isolation layer extending into a set of dummy gate electrodes located at the edges of the exclusion region.

5. The semiconductor device according to claim 3, wherein, A set of the dummy gate electrodes is located at the edge of the exclusion region.

6. The semiconductor device according to claim 1, further comprising: The system includes multiple upper wirings, the multiple upper wirings including the upper wirings; and multiple lower wirings, the multiple lower wirings including the lower wirings, wherein the distance between the upper wirings and the exclusion area in the first direction is less than the distance between the second upper wiring in the multiple upper wirings and the exclusion area in the first direction, and wherein the distance between the lower wirings and the exclusion area in the first direction is less than the distance between the second lower wiring in the multiple lower wirings and the exclusion area in the first direction.

7. The semiconductor device according to claim 1, wherein, At least one of the gate electrodes is connected to the upper wiring.

8. The semiconductor device according to claim 7, wherein, The dummy wiring is connected to most of the source / drain patterns in the source / drain pattern.

9. A semiconductor device, comprising: The substrate includes a first surface and a second surface, a cell region and an exclusion region, wherein the first surface and the second surface are opposite to each other; The active pattern and the dummy pattern are spaced apart from each other in a first direction and are on the first surface of the substrate; The source / drain pattern and the dummy source / drain pattern are respectively connected to the active pattern and the dummy pattern; The gate electrode and the dummy gate electrode extend around the activation pattern and the dummy pattern, respectively, and extend along a second direction intersecting the first direction; On the first surface of the substrate, the upper wiring is on the cell region and connected to at least one first source / drain pattern in the source / drain patterns; The lower wiring is on the second surface of the substrate, on the cell region and connected to at least one second source / drain / pattern in the source / drain pattern; as well as A dummy wiring extends from either the upper wiring or the lower wiring. The dummy gate electrode and the dummy source / drain pattern are insulated from the upper wiring and the lower wiring, and the dummy wiring extends into the exclusion region.

10. The semiconductor device according to claim 9, wherein: The substrate includes a peripheral region extending around the cell region. The activation pattern, the gate electrode, and the source / drain pattern are on the cell region. The dummy pattern, the dummy gate electrode, and the dummy source / drain pattern are on the peripheral region, and The exclusion zone is located in the outer perimeter area.

11. The semiconductor device according to claim 9, wherein: The substrate includes a plurality of unit regions, and the plurality of unit regions include the unit regions, and Each of the plurality of unit regions includes: The component area includes the activation pattern, the gate electrode, and the source / drain pattern. A dummy region, comprising the dummy pattern, the dummy gate electrode, and the dummy source / drain pattern, and The exclusion zone at least partially overlaps with the dummy zone in a third direction perpendicular to the first and second directions.

12. The semiconductor device of claim 11, further comprising an element isolation layer extending into a set of dummy gate electrodes located at the edges of the exclusion region.

13. The semiconductor device according to claim 11, wherein, A set of the dummy gate electrodes is located at the edge of the exclusion region.

14. The semiconductor device according to claim 9, further comprising: The system includes multiple upper wirings, the multiple upper wirings including the upper wirings; and multiple lower wirings, the multiple lower wirings including the lower wirings, wherein the distance between the upper wirings and the exclusion area in the first direction is less than the distance between the second upper wiring in the multiple upper wirings and the exclusion area in the first direction, and wherein the distance between the lower wirings and the exclusion area in the first direction is less than the distance between the second lower wiring in the multiple lower wirings and the exclusion area in the first direction.

15. The semiconductor device according to claim 9, wherein, At least one of the gate electrodes is connected to the upper wiring.

16. The semiconductor device according to claim 15, wherein, The dummy wiring is connected to most of the source / drain patterns in the source / drain pattern.

17. A semiconductor device, comprising: The substrate includes a first surface and a second surface, a first element region, a second element region, and a dummy region between the first element region and the second element region, wherein the first surface and the second surface are opposite to each other. The first active pattern, the second active pattern, and the dummy pattern are spaced apart from each other in a first direction and are on the first surface of the first element region, the second element region, and the dummy region of the substrate; The first source / drain pattern, the second source / drain pattern, and the dummy source / drain pattern are respectively connected to the first active pattern, the second active pattern, and the dummy pattern; The first gate electrode, the second gate electrode, and the dummy gate electrode extend around the first activation pattern, the second activation pattern, and the dummy pattern, respectively, and extend along a second direction intersecting the first direction; On the first surface of the substrate, wiring is provided and connected to the first set of the first source / drain patterns and the first set of the second source / drain patterns; The lower wiring is on the second surface of the substrate and connected to the second set of the first source / drain patterns and the second set of the second source / drain patterns; as well as A dummy wiring extends from either the upper wiring or the lower wiring. Wherein, the dummy gate electrode and the dummy source / drain pattern are insulated from the upper wiring and the lower wiring on a portion of the dummy region, and The dummy wiring crosses the portion of the dummy region in the first direction and is connected to at least one of the first source / drain patterns and at least one of the second source / drain patterns.

18. The semiconductor device according to claim 17, wherein, At least one of the first gate electrodes and at least one of the second gate electrodes are connected to the upper wiring.

19. The semiconductor device according to claim 18, wherein, The dummy wiring is connected to most of the first source / drain patterns in the first source / drain pattern and most of the second source / drain patterns in the second source / drain pattern.

20. The semiconductor device of claim 17, further comprising an element isolation layer extending into a set of the dummy gate electrodes.

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