Semiconductor device and method of manufacture, power module, power conversion circuit and vehicle

Abstract

The application discloses a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle, and belongs to the technical field of semiconductors. The semiconductor device comprises a cell region and a pad region located on one side of the cell region; the cell region comprises a device structure, and the device structure comprises a gate structure; the pad region comprises: a sensor structure comprising a thermistor; and gate pads connected with the gate structure and the thermistor respectively. The application can reduce the volume of the semiconductor device and improve the detection accuracy of the sensor.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and particularly relates to a semiconductor device and its preparation method, a power module, a power conversion circuit, and a vehicle. Background Technology

[0002] To ensure semiconductor devices operate within safe limits and guarantee reliability and safety, temperature monitoring of power devices is necessary. To monitor this temperature, related technologies mount temperature sensors on a substrate, liner, or near the device's package. However, temperature sensors occupy a large area, leading to a larger semiconductor device size. Furthermore, the long thermal conduction path between the temperature sensor and the power device results in thermal conduction delays and lower detection accuracy. Summary of the Invention

[0003] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a semiconductor device and its fabrication method, a power module, a power conversion circuit, and a vehicle, which can reduce the size of the semiconductor device and improve the detection accuracy of the sensor.

[0004] In a first aspect, this application provides a semiconductor device, including a cell region and a pad region located on one side of the cell region; The cell region includes a device structure, and the device structure includes a gate structure; The pad area includes: Sensor structure, including thermistors; The gate pads are connected to the gate structure and the thermistor, respectively.

[0005] According to the semiconductor device of this application, by setting a sensor structure in the pad area, the sensor structure includes a thermistor, and the gate pad is connected to the gate structure and the thermistor of the device structure respectively, that is, the gate structure and the thermistor share a pad, the area occupied by the sensor structure is reduced, thereby reducing the volume of the semiconductor device. Moreover, the sensor structure and the device structure are integrated, which shortens the heat conduction path between the device structure and the sensor structure, reduces the heat conduction delay time, and improves the detection accuracy of the sensor.

[0006] According to one embodiment of this application, the orthogonal projection of the gate pad in the thickness direction at least partially overlaps with the orthogonal projection of the thermistor in the thickness direction.

[0007] According to one embodiment of this application, the pad area further includes: A first dielectric layer covers the thermistor; the gate pad is located on the side of the first dielectric layer away from the thermistor and extends through the first dielectric layer to connect with the thermistor.

[0008] According to one embodiment of this application, the thermistor includes a first end, a second end, and a main body portion connected between the first end and the second end; the gate pad penetrates the first dielectric layer and is connected to the first end; The pad area further includes a third pad, located on the side of the first dielectric layer away from the thermistor, and extending through the first dielectric layer to connect with the second end.

[0009] According to one embodiment of this application, the orthographic projection of the gate pad in the thickness direction covers the orthographic projection of the first end portion in the thickness direction and at least partially overlaps with the orthographic projection of the main body portion in the thickness direction.

[0010] According to one embodiment of this application, the thermistor further includes an extension portion, which is disposed around an integral structure formed by the first end portion, the second end portion, and the main body portion. The extension portion is connected to the first end portion and spaced apart from the second end portion; the gate pad is also connected to the extension portion.

[0011] According to one embodiment of this application, the gate pad is disposed around the third pad, and the orthographic projection of the gate pad in the thickness direction covers the orthographic projection of the extension in the thickness direction.

[0012] According to one embodiment of this application, the material of the thermistor includes polycrystalline silicon.

[0013] According to one embodiment of this application, the gate pad includes a first pad and a second pad, the first pad being connected to the gate structure and the second pad being connected to the thermistor.

[0014] According to one embodiment of this application, the cell region further includes: A semiconductor body includes a first surface and a second surface disposed opposite each other in the thickness direction; the gate structure is located on the side of the semiconductor body closer to the first surface, or the gate structure extends from the first surface into the semiconductor body; An insulating layer is located between the semiconductor body and the gate structure; The pad area also includes: The semiconductor body, wherein the thermistor is located on the side of the semiconductor body closer to the first surface; The second dielectric layer is located between the semiconductor body and the thermistor.

[0015] According to one embodiment of this application, the pad area further includes: The device structure is located between the semiconductor body and the second dielectric layer.

[0016] According to one embodiment of this application, the cell region further includes: A gate resistor is located on the side of the semiconductor body near the first surface. The gate resistor is connected to the gate structure and extends from the gate structure to the pad area, where it is connected to the gate pad. The insulating layer is also located between the semiconductor body and the gate resistor.

[0017] According to one embodiment of this application, the device structure is a power device, and the sensor structure is a temperature sensor.

[0018] Secondly, this application provides a method for fabricating a semiconductor device, the semiconductor device comprising a cell region and a pad region located on one side of the cell region; the method includes: A device structure is formed in the cell region, the device structure including a gate structure; A sensor structure is formed in the pad area, the sensor structure including a thermistor; A gate pad is formed in the pad area, and the gate pad is connected to the gate structure and the thermistor respectively.

[0019] According to one embodiment of this application, the thermistor includes a first end, a second end, and a main body portion connected between the first end and the second end; The process of forming a gate pad in the pad area includes: A first dielectric layer is formed covering the thermistor; A first contact hole and a second contact hole are formed that penetrate the first dielectric layer, with the first contact hole exposing the first end and the second contact hole exposing the second end; A gate pad and a third pad are formed on the side of the first dielectric layer away from the thermistor. The gate pad also fills the first contact hole and is connected to the first end. The third pad also fills the second contact hole and is connected to the second end.

[0020] Thirdly, this application provides a power module including a substrate and a semiconductor device as described in the first aspect above, wherein the substrate is used to support the semiconductor device.

[0021] Fourthly, this application provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and a semiconductor device as described in the first aspect above, the semiconductor device being electrically connected to the circuit board.

[0022] Fifthly, this application provides a vehicle including a load and a power conversion circuit as described in the fourth aspect above, the power conversion circuit being used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input the converted direct current to the load.

[0023] The above-described one or more technical solutions in the embodiments of this application have at least one of the following technical effects: The sensor structure includes a thermistor, and the gate pad is connected to the gate structure and the thermistor of the device structure respectively. That is, the gate structure and the thermistor share a single pad, which reduces the area occupied by the sensor structure and thus reduces the size of the semiconductor device. Moreover, the sensor structure and the device structure are integrated, which shortens the heat conduction path between the device structure and the sensor structure, reduces the heat conduction delay time, and improves the detection accuracy of the sensor.

[0024] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0025] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is one of the schematic diagrams of the semiconductor device provided in the embodiments of this application; Figure 2 This is a second schematic diagram of the structure of the semiconductor device provided in the embodiments of this application; Figure 3 This is a top view of the sensor structure in the semiconductor device provided in the embodiments of this application; Figure 4 This is a top view of the first dielectric layer in the semiconductor device provided in the embodiments of this application; Figure 5 This is a top view of the pads in the semiconductor device provided in the embodiments of this application; Figure 6 This is a schematic flowchart of the method for fabricating a semiconductor device provided in an embodiment of this application; Figure 7 This is one of the structural schematic diagrams in the method for fabricating a semiconductor device provided in the embodiments of this application; Figure 8 This is a second schematic diagram of the structure in the method for fabricating a semiconductor device provided in the embodiments of this application; Figure 9 This is the third schematic diagram of the structure in the method for fabricating the semiconductor device provided in the embodiments of this application; Figure 10This is the fourth schematic diagram of the structure in the method for fabricating a semiconductor device provided in the embodiments of this application. Detailed Implementation

[0026] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0027] The following description, with reference to the accompanying drawings, describes the semiconductor device and its fabrication method, power module, power conversion circuit, and vehicle provided in embodiments of this application.

[0028] Figure 1 and Figure 2 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application.

[0029] like Figure 1 and Figure 2 As shown, the semiconductor device provided in this embodiment includes a cell region A1 and a pad region A2, with the pad region A2 located on one side of the cell region A1. The cell region A1 is the working area of ​​the device structure, and the pad region A2 is used to set the electrode pads of the device structure.

[0030] Cell region A1 includes device structure 1, which includes gate structure 11. In some embodiments, device structure 1 can be a power device, which can include a power field-effect transistor. Power field-effect transistors have various structures, such as planar gate structure or trench gate structure.

[0031] The pad area A2 includes a sensor structure and a gate pad 40. In some embodiments, the sensor structure can be a temperature sensor for detecting the temperature of the device structure 1. By detecting the temperature of the device structure 1, it can be ensured that the device structure operates within a safe range, guaranteeing reliability and safety. The sensor structure can also be other types of sensors for other detections of the device structure 1, which are not specifically limited here.

[0032] The sensor structure includes a thermistor 2. The resistance of thermistor 2 changes significantly with temperature. By detecting the resistance of thermistor 2, temperature detection, temperature compensation, and over-temperature protection can be achieved, making thermistor 2 applicable to various types of sensor structures.

[0033] Gate pad 40 is connected to gate structure 11 and thermistor 2 respectively, to bring out gate structure 11 and thermistor 2. Gate pad 40 can be directly connected to gate structure 11 or connected through other conductive structures, which is not specifically limited here. Gate pad 40 can be directly connected to thermistor 2 or connected through other conductive structures, which is not specifically limited here.

[0034] The material of the gate structure 11 may include polysilicon, etc., and the material of the gate pad 40 may include metals such as aluminum, copper, and nickel.

[0035] In this embodiment, the gate structure 11 and the thermistor 2 share a single pad, namely the gate pad 30, which reduces the area occupied by the sensor structure 2, thereby reducing the size of the semiconductor device and making it more widely applicable. Furthermore, the integrated design of the sensor structure and the device structure 1 shortens the heat conduction path between them, reduces the heat conduction delay time, and improves the sensor's detection accuracy.

[0036] Furthermore, related technologies also employ a body diode as the sensor structure. However, this structure relies on a trench structure, lacks universality, and is susceptible to interference from the main circuit and switching oscillations. This embodiment, however, uses a thermistor 2 located in the pad area A2, achieving detection without affecting the area of ​​cell A1 or the device's structural performance. Sensor structure 2 is compatible with device structure 1, offering wider applicability. Moreover, sensor structure 2 does not participate in the main circuit current, effectively shielding against interference and further improving sensor detection accuracy.

[0037] In some embodiments, the orthogonal projection of the gate pad 40 in the thickness direction X at least partially overlaps with the orthogonal projection of the thermistor 2 in the thickness direction X.

[0038] It should be noted that the position of the gate pad 40 can be the same as the position of the gate pad in the device structure of related technologies. The thermistor 2 can be located below the gate pad 40.

[0039] The overlap area between the orthogonal projection of the gate pad 40 in the thickness direction X and the orthogonal projection of the thermistor 2 in the thickness direction X can be as large as possible to minimize the area occupied by the thermistor 2. As an example, the orthogonal projection of the gate pad 40 in the thickness direction X covers the orthogonal projection of the thermistor 2 in the thickness direction X.

[0040] In this embodiment, the orthogonal projection of the gate pad 40 in the thickness direction X at least partially overlaps with the orthogonal projection of the thermistor 2 in the thickness direction X, further reducing the area occupied by the thermistor 2 and further reducing the volume of the semiconductor device, making it more widely applicable.

[0041] In some embodiments, the pad area A2 further includes a first dielectric layer 3, which covers the thermistor 2. The gate pad 40 is located on the side of the first dielectric layer 3 away from the thermistor 2 and extends through the first dielectric layer 3 to connect with the thermistor 2.

[0042] The first dielectric layer 3 is used to space the thermistor 2 from the gate pad 40. The material of the first dielectric layer 3 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0043] In some embodiments, combined with Figure 3 As shown, the thermistor 2 includes a first end 21, a second end 22, and a main body 23 connecting the first end 21 and the second end 22. The main body 23 can be a bent structure, such as a serpentine structure, to increase the effective length of the thermistor within a limited space and achieve a larger resistance value. The widths of the first end 21 and the second end 22 are respectively greater than the width of the main body 23 to increase the connection window of the first end 21 and the second end 22 and improve the reliability of the electrical connection.

[0044] The orthographic projection of the gate pad 40 in the thickness direction X at least partially overlaps with the orthographic projection of the main body 23 in the thickness direction X. The main body 23 is the primary structure of the thermistor 2. The overlap area between the orthographic projection of the gate pad 40 in the thickness direction X and the orthographic projection of the main body 23 in the thickness direction X is maximized to minimize the area occupied by the thermistor 2, thereby reducing the area occupied by the sensor structure. As an example, the orthographic projection of the gate pad 40 in the thickness direction X covers the orthographic projection of the main body 23 in the thickness direction X.

[0045] In some embodiments, the material of the thermistor 2 may include semiconductor materials such as polycrystalline silicon, or metal oxides (such as manganese oxide, nickel oxide), ceramic materials (such as barium titanate, lead zirconate) or polymer materials (polyethylene, polypropylene), etc., without specific limitations.

[0046] In this embodiment, the thermistor 2 is made of polycrystalline silicon material, which has a simple structure, stable performance, and good process compatibility.

[0047] In some embodiments, the gate pad 40 is located on the side of the first dielectric layer 3 opposite to the thermistor 2, and extends through the first dielectric layer 3 to connect with the first end 21. Figure 4 As shown, a first contact hole 31 is provided in the first dielectric layer 3, which penetrates the first dielectric layer 3. The first contact hole 31 corresponds to the position of the first end 21. The gate pad 40 fills the first contact hole 31 and is connected to the first end 21. The orthographic projection of the gate pad 40 in the thickness direction X at least partially overlaps with the orthographic projection of the first end 21 in the thickness direction X.

[0048] In some embodiments, pad area A2 further includes a third pad 43. The third pad 43 is located on the side of the first dielectric layer 3 opposite to the thermistor 2 and extends through the first dielectric layer 3 to connect with the second end 22. Figure 4 As shown, a second contact hole 32 penetrating the first dielectric layer 3 is provided in the first dielectric layer 3. The second contact hole 32 corresponds to the position of the second end 22. A third pad 43 fills the second contact hole 32 and is connected to the second end 22. The orthographic projection of the third pad 43 in the thickness direction X at least partially overlaps with the orthographic projection of the second end 22 in the thickness direction X.

[0049] The gate pad 40 and the third pad 43 can be arranged on the same layer, that is, formed in the same process. The gate pad 40 and the third pad 43 are arranged alternately.

[0050] In some embodiments, the orthographic projection of the gate pad 40 in the thickness direction X covers the orthographic projection of the first end portion 21 in the thickness direction X and at least partially overlaps with the orthographic projection of the main body portion 23 in the thickness direction X. The overlap area between the orthographic projection of the gate pad 40 in the thickness direction X and the orthographic projections of the first end portion 21 and the main body portion 23 in the thickness direction X is as large as possible. As an example, the orthographic projection of the gate pad 40 in the thickness direction X covers the orthographic projections of the first end portion 21 and the main body portion 23 in the thickness direction X.

[0051] In some embodiments, combined with Figure 3 As shown, the thermistor 2 also includes an extension 24, which is disposed around the integral structure 20 formed by the extension, the first end portion 21, the second end portion 22, and the main body portion 23. The extension 24 is connected to the first end portion 21, and the extension 24 is spaced apart from the second end portion 22. Figure 3 As shown, the extension 24 can extend along the edge of the pad area A2 to form a ring structure, and the overall structure 20 formed by the first end 21, the second end 22, and the main body 23 is located in the ring structure. The orthographic projection of the ring structure in the thickness direction X can be rectangular or other shapes.

[0052] The gate pad 40 is also connected to the extension 24. That is, the gate pad 40 is located on the side of the first dielectric layer 3 away from the thermistor 2, and is connected to the first end 21 of the thermistor 20 and the extension 24 through the first dielectric layer 3 respectively.

[0053] As an example, the extension 24 can be rectangular, with the first end 21 located at the first corner of the extension 24 and connected to it. The second end 22 can be positioned near the second corner of the extension 24 and spaced apart from it. The first and second corners of the extension 24 are positioned opposite each other.

[0054] Combination Figure 4 As shown, the first dielectric layer 3 also has a third contact hole 33, which corresponds to the position of the extension 24. The third contact hole 33 is connected to the first contact hole 31, and the third contact hole 33 is spaced apart from the second contact hole 32. The gate pad 40 fills the first contact hole 31 and the third contact hole 33, and is connected to the first end 21 of the thermistor 2 and the extension 24, respectively.

[0055] In this embodiment, an extension portion 24 is provided, and the extension portion 24 is connected to the gate pad 40, thereby increasing the connection window between the gate pad 40 and the thermistor 2.

[0056] In some embodiments, combined with Figure 5 As shown, the gate pad 40 is disposed around the third pad 43, and the orthogonal projection of the gate pad 40 in the thickness direction X covers the orthogonal projection of the extension 24 in the thickness direction X.

[0057] The third contact hole 33 can extend along the edge of the pad area A2 to form a closed contact hole, such as a rectangle. The third contact hole 33 is arranged around the first contact hole 31 and the second contact hole 32. The first contact hole 31 can be located at the first corner of the third contact hole 33 and communicate with the third contact hole 33. The second contact hole 32 can be arranged close to the second corner of the third contact hole 33, and the second corner of the third contact hole 33 is opposite to the first corner.

[0058] Gate pad 40 fills the first contact hole 31 and the third contact hole 32, and is connected to the first end 21 and the extension 24 of the thermistor 20, respectively. Second pad 42 fills the second contact hole 32 and is connected to the second end 22, such that the common pad 40 is arranged around the third pad 43.

[0059] The orthographic projection of the gate pad 40 in the thickness direction X can cover the orthographic projections of the first end portion 21 and the extension portion 24 in the thickness direction X, and at least partially overlap with the orthographic projection of the main body portion 23 in the thickness direction X. The orthographic projection of the third pad 43 in the thickness direction X at least partially overlaps with the orthographic projection of the second end portion 22 in the thickness direction X.

[0060] As an example, the orthographic projection of the gate pad 40 in the thickness direction X covers the orthographic projections of the first end portion 21 and the extension portion 24 in the thickness direction X, and overlaps with the orthographic projection portion of the main body portion 23 in the thickness direction X. The orthographic projection of the third pad 43 in the thickness direction X covers the orthographic projection of the second end portion 22 in the thickness direction X, and overlaps with the orthographic projection portion of the main body portion 23 in the thickness direction X. The overlapping area between the gate pad 40 and the main body portion 23 can be larger than the overlapping area between the third pad 43 and the main body portion 23.

[0061] In this embodiment, the gate pad 40 is arranged around the third pad 43, which increases the connection window of the gate pad 40 and facilitates the connection of the gate pad 40 with the electrodes of the device structure at different locations.

[0062] In some embodiments, the gate pad 40 includes a first pad 41 and a second pad 42. The first pad 41 is connected to the gate structure 11, and the second pad 42 is connected to the thermistor 2. The second pad 42 may be located on the side of the first dielectric layer 3 away from the thermistor 2, and penetrate the first dielectric layer 3 to connect to the first end 21 of the thermistor 2.

[0063] In some embodiments, cell region A1 further includes a semiconductor body 12 and an insulating layer (i.e., a first insulating layer 13). The semiconductor body 12 includes a first surface S1 and a second surface S2 disposed opposite to each other in the thickness direction X. The semiconductor body 12 may include a substrate and a semiconductor epitaxial layer located on one side of the substrate in the thickness direction X. The second surface S2 is the surface of the substrate away from the semiconductor epitaxial layer, and the first surface S1 is the surface of the semiconductor epitaxial layer away from the substrate.

[0064] The substrate material and the semiconductor epitaxial layer material can be the same or different. In some embodiments, both the semiconductor epitaxial layer material and the substrate material can be SiC, and device structure 1 can be a planar SiC power device, a trench SiC power device, or other SiC semiconductor devices. SiC has excellent physical and electrical properties. Compared with silicon, SiC has a larger bandgap and advantages such as high breakdown electric field, high thermal conductivity, high electron saturation velocity, and strong radiation resistance. Therefore, semiconductor devices made of SiC can not only operate stably at higher temperatures, but are also suitable for high-voltage and high-frequency applications.

[0065] In cell region A1, a well region 123 and a first region 124 are provided in the semiconductor epitaxial layer. The well region 123 extends from the first surface S1 into the semiconductor epitaxial layer. The first region 124 extends from the first surface S1 into the well region 123.

[0066] The substrate, the semiconductor epitaxial layer, and the first region 124 are of the first conductivity type, while the well region 103 is of the second conductivity type. The first conductivity type and the second conductivity type are opposite. One of the first conductivity type and the second conductivity type is P-type, and the other is N-type.

[0067] As an example, the substrate is an N-type substrate, the semiconductor epitaxial layer is an N-type epitaxial layer, and the well region 123 is a P-type well region (PW). The first region 124 is an N-type doped region, also known as an N+ contact region, and is used as a source region.

[0068] The gate structure 11 is located on the side of the semiconductor body 12 near the first surface S1, and the first insulating layer 13 is located between the semiconductor body 12 and the gate structure 11. That is, the first insulating layer 13 is located on the first surface S1 of the semiconductor body 12, and the gate structure 11 is located on the side of the first insulating layer 13 away from the semiconductor body 12. The first insulating layer 13 covers a portion of the first surface S1, and the first insulating layer 13 partially overlaps with the first region 124.

[0069] Alternatively, the gate structure 11 extends from the first surface S1 into the semiconductor body 12, and the first insulating layer 13 is located between the semiconductor body 12 and the gate structure 11. That is, the semiconductor epitaxial layer is provided with a gate trench extending from the first surface S1 into the semiconductor epitaxial layer, the first insulating layer 13 covers the surface of the gate trench, and the gate structure 11 fills the gate trench.

[0070] The first insulating layer 13 is used to insulate the gate structure 11 from the semiconductor epitaxial layer. The material of the first insulating layer 13 may include silicon oxide, etc.

[0071] The semiconductor device further includes a second insulating layer 14, and the device structure 1 further includes a source 15. The source 15 is located on the side of the gate structure 11 opposite to the semiconductor body 12 and is connected to the first region 124 in the semiconductor body 12. The second insulating layer 14 is located between the gate structure 11 and the source 15. In some embodiments, the semiconductor device further includes a drain located on the second surface S2 of the semiconductor body 12.

[0072] The second insulating layer 14 is used to insulate the gate structure 11 from the source 15. The material of the second insulating layer 14 may include silicon oxide, etc. The materials of the source 15 and the drain may include metals such as aluminum, copper, and nickel, respectively. In some embodiments, the cell region A1 further includes a gate resistor 5. The gate resistor 5 is located on the side of the semiconductor body 12 near the first surface S1, the gate resistor 5 is connected to the gate structure 11, and extends from the gate structure 11 to the pad region A2, where it is connected to the gate pad 40. The first insulating layer 13 is also located between the semiconductor body 12 and the gate resistor 5, and is used to insulate the semiconductor body 12 from the gate resistor 5.

[0073] The gate resistor 5 and the gate structure 11 can be disposed in the same layer, that is, formed in the same manufacturing process. The material of the gate structure 5 may include polysilicon, etc.

[0074] It should be noted that semiconductor devices may also include other structures, such as Kelvin sources, etc., which are not specifically limited here. Sensor structure 2 can also be integrated with other types of device structures, which are not specifically limited here.

[0075] The structure of pad area A2 is described below through two optional embodiments.

[0076] In a first alternative embodiment, such as Figure 1 As shown, the pad area A2 also includes a semiconductor body 12, a thermistor 2 located on the side of the semiconductor body 12 closer to the first surface S1, and a first dielectric layer 3 located on the side of the thermistor 2 away from the semiconductor body 12. The pad area A2 also includes a second dielectric layer 6, which is located between the semiconductor body 12 and the thermistor 2.

[0077] As an example, the second dielectric layer 6 is located on the first surface S1 of the pad area A2 of the semiconductor body 12, the thermistor 2 is located on the side of the second dielectric layer 6 opposite to the semiconductor body 12, and the first dielectric layer 3 covers the sensor structure 2 and the second dielectric layer 6. The gate pad 40 is located on the side of the first dielectric layer 3 opposite to the semiconductor body 12, and extends through the first dielectric layer 3 to connect with the first end 21 and the extension 24. The gate resistor 5 extends from the gate structure 11 to the second dielectric layer 6, and the gate pad 40 also extends along the sidewalls of the first dielectric layer 3 and the second dielectric layer 6 to the gate resistor 5 and connects with the gate resistor 5. The third pad 43 is located on the layer of the first dielectric layer 3 opposite to the semiconductor body 12, and extends through the first dielectric layer 3 to connect with the second end 22.

[0078] In the second embodiment, such as Figure 2 As shown, the pad area A2 also includes a semiconductor body 12, a thermistor 2 located on the side of the semiconductor body 12 closer to the first surface S1, and a first dielectric layer 3 located on the side of the thermistor 2 away from the semiconductor body 12. The semiconductor device also includes a second dielectric layer 6, located in the pad area A2 and between the semiconductor body 12 and the thermistor 2. The pad area A2 also includes a device structure 1, located between the semiconductor body 12 and the second dielectric layer 6.

[0079] The device structure 1 of pad region A2 has the same structure as cell region A1 (including well region 123, first region 124, first insulating layer 13, gate structure 11, second insulating layer 14 and source 15), which will not be described in detail here.

[0080] As an example, the second dielectric layer 6 covers the source 15 of the pad region A2 and the first surface S1. The thermistor 2 is located on the side of the second dielectric layer 6 away from the semiconductor body 12. The first dielectric layer 3 covers the thermistor 2 and the second dielectric layer 6. The gate pad 40 is located on the side of the first dielectric layer 3 away from the semiconductor body 12 and extends through the first dielectric layer 3 to connect with the first end 21 and the extension 24. The gate resistor 5 extends from the gate structure 11 to the second dielectric layer 6. The gate pad 40 also extends along the sidewalls of the first dielectric layer 3 and the second dielectric layer 6 to the gate resistor 5 and connects with the gate resistor 5. The third pad 43 is located on the layer of the first dielectric layer 3 away from the semiconductor body 12 and extends through the first dielectric layer 3 to connect with the second end 22.

[0081] According to the semiconductor device provided in the embodiments of this application, a sensor structure is set in the pad area A2. The sensor structure includes a thermistor 2, and the gate pad 2 is connected to the gate structure 11 and the thermistor 2 of the device structure 1, respectively. That is, the gate structure 11 and the thermistor 2 share a single pad, reducing the area occupied by the sensor structure and thus reducing the volume of the semiconductor device. Moreover, the sensor structure is integrated with the device structure 1, shortening the heat conduction path between the device structure 1 and the sensor structure, reducing the heat conduction delay time, and improving the sensor detection accuracy. In addition, the sensor structure is set in the pad area A2 without affecting the area of ​​the cell area A1, so as to achieve detection without affecting the performance of the device structure. Furthermore, the sensor structure does not participate in the current of the main circuit, which can shield interference and further improve the sensor detection accuracy.

[0082] Accordingly, this application also provides a method for fabricating a semiconductor device.

[0083] Figure 6 This is a schematic flowchart illustrating the method for fabricating a semiconductor device provided in an embodiment of this application.

[0084] like Figure 6 As shown, the method for fabricating a semiconductor device provided in this application includes steps S110 to S130. The semiconductor device includes a cell region A1 and a pad region A2 located on one side of the cell region A1.

[0085] Step S110: Form a device structure in the cell region, the device structure including a gate structure.

[0086] As an example, combined Figure 7As shown, device structure 1 may include a gate structure 11 and a source 15. Before forming device structure 1, a semiconductor substrate 12 may be provided. The semiconductor body 12 includes a first surface S1 and a second surface S2 disposed opposite to each other in the thickness direction X. The semiconductor body 12 may include a substrate and a semiconductor epitaxial layer located on one side of the substrate in the thickness direction X. The second surface S2 is the surface of the substrate away from the semiconductor epitaxial layer, and the first surface S1 is the surface of the semiconductor epitaxial layer away from the substrate. In cell region A1, a well region 123 and a first region 124 are provided in the semiconductor epitaxial layer. The well region 123 extends from the first surface S1 into the semiconductor epitaxial layer. The first region 124 extends from the first surface S1 into the well region 123.

[0087] Then, a first insulating layer 13 and a gate structure 11 are formed. The gate structure 11 is located on the side of the semiconductor body 12 near the first surface S1, and the first insulating layer 13 is located between the semiconductor body 12 and the gate structure 11. Alternatively, the gate structure 11 extends from the first surface S1 into the semiconductor body 12, and the first insulating layer 13 is located between the semiconductor body 12 and the gate structure 11.

[0088] Then, a second insulating layer 14 and a source electrode 15 are formed. The source electrode 15 is located on the side of the gate structure 11 opposite to the semiconductor body 12 and is connected to the first region 124 in the semiconductor body 12. The second insulating layer 14 is located between the gate structure 11 and the source electrode 15.

[0089] In some embodiments, a gate resistor 5 is formed concurrently with the formation of the gate structure 11. The gate resistor 5 is located on a layer of the first insulating layer 13 opposite to the semiconductor body 12. The gate resistor 5 is connected to the gate structure 11 and extends from the gate structure 11 to the pad region A2.

[0090] In some embodiments, such as Figure 2 As shown, device structure 1 is also formed in pad region A2. Device structure 1 in pad region A2 has the same structure as cell region A1 (including well region 123, first region 124, first insulating layer 13, gate structure 11, second insulating layer 14 and source 15), which will not be described in detail here.

[0091] Step S120: Form a sensor structure in the pad area. The sensor structure includes a thermistor.

[0092] As an example, combined Figure 7 As shown, a thin film deposition process is first used to form a second dielectric layer 6 in the pad area A2. The second dielectric layer 6 is located on the first surface S1 of the pad area A2.

[0093] If pad area A2 also has device structure 1, such as Figure 2As shown, the second dielectric layer 6 covers the source electrode 15 of the pad area A2 and the first surface S1.

[0094] Then, combine Figure 8 As shown, a thermistor 2 is formed on the side of the second dielectric layer 6 away from the semiconductor body 12. For example, a sensor layer is first formed on the side of the second dielectric layer 6 away from the semiconductor body 12 using a thin film deposition process, and then the sensor layer is patterned to obtain the thermistor 2. The second dielectric layer 6 is used to insulate the thermistor 2 from the semiconductor body 10 / source 15.

[0095] Step S130: Form a gate pad in the pad area. The gate pad is connected to the gate structure and the thermistor respectively.

[0096] In some embodiments, combined with Figure 3 As shown, the thermistor 2 includes a first end 21, a second end 22, and a main body portion 23 connected between the first end 21 and the second end 22. The orthographic projection of the gate pad 40 in the thickness direction X at least partially overlaps with the orthographic projection of the main body portion 23 in the thickness direction X. In some embodiments, the material of the thermistor 2 may include semiconductor materials such as polycrystalline silicon, or materials whose resistance can change with temperature; no specific limitation is made here.

[0097] The method for fabricating this semiconductor device also includes: A first dielectric layer is formed to cover the thermistor; A first contact hole and a second contact hole are formed that penetrate the first dielectric layer, with the first contact hole exposing the first end and the second contact hole exposing the second end. A gate pad and a third pad are formed on the side of the first dielectric layer away from the thermistor. The gate pad also fills the first contact hole and is connected to the first end. The third pad also fills the second contact hole and is connected to the second end.

[0098] As an example, combined Figure 9 As shown, a first dielectric layer 3 is formed on the side of the thermistor 2 away from the semiconductor body 12 using a thin film deposition process. The first dielectric layer 3 covers the thermistor 2 and the second dielectric layer 6.

[0099] Combination Figure 10 and Figure 4 As shown, the first dielectric layer 3 is etched to form a first contact hole 31 and a second contact hole 32 penetrating the first dielectric layer 3. The first contact hole 31 corresponds to the position of the first end 21 to expose the first end 21. The second contact hole 32 corresponds to the position of the second end 22 to expose the second end 22.

[0100] Combination Figure 1As shown, a thin-film deposition process is used to form a gate pad 40 and a third pad 43 on the side of the first dielectric layer 3 opposite to the sensor structure 2. The gate pad 40 also fills the first contact hole 31 to connect with the first end 21. The gate pad 40 can also extend along the sidewalls of the first dielectric layer 3 and the second dielectric layer 6 to the gate resistor 5 and connect with the gate resistor 5, so that the gate structure 11 is connected to the gate pad 40 through the gate resistor 5. The third pad 43 also fills the second contact hole 32 to connect with the second end 22. The gate pad 40 and the third pad 43 are spaced apart.

[0101] Gate pad 2 is connected to both the gate structure 11 and the thermistor 2 of device structure 1, meaning that the gate structure 11 and the thermistor 2 share a single pad. This reduces the area occupied by the sensor structure, thereby reducing the size of the semiconductor device and broadening its applicability. Furthermore, the integrated design of the sensor structure and device structure 1 shortens the heat conduction path between them, reducing heat conduction delay time and improving sensor detection accuracy. Additionally, the sensor structure is located in pad area A2, without affecting the area of ​​cell area A1, enabling detection without compromising device structure performance. Moreover, the sensor structure does not participate in the main circuit current, effectively shielding against interference and further improving sensor detection accuracy.

[0102] In some embodiments, the gate pad 40 includes a first pad 41 and a second pad 42, the first pad 41 being connected to the gate structure 11 and the second pad 42 being connected to the thermistor 2. The first pad 41 and the second pad 42 may be an integrally formed structure.

[0103] In some embodiments, combined with Figure 3 As shown, the thermistor 2 also includes an extension 24, which is disposed around the integral structure 20 formed by the first end portion 21, the second end portion 22, and the main body portion 23. The extension 24 is connected to the first end portion 21 and is spaced apart from the second end portion 22. The gate pad 40 is also connected to the extension 24. The gate pad 40 is located on the side of the first dielectric layer 3 opposite to the thermistor 2 and penetrates the first dielectric layer 3 to be connected to the first end portion 21 and the extension 24 of the thermistor 2.

[0104] In some embodiments, combined with Figure 10 and Figure 4 As shown, the method for fabricating this semiconductor device further includes: A third contact hole 33 is formed that penetrates the first dielectric layer 3. The third contact hole 33 is disposed around the first contact hole 31 and the second contact hole 32, and the third contact hole 33 is connected to the first contact hole 31 and spaced apart from the second contact hole 32. The gate pad 40 is also filled in the third contact hole 33 to connect with the extension 24.

[0105] The third contact hole 33 can be formed simultaneously with the first contact hole 31 and the second contact hole 32.

[0106] In some embodiments, combined with Figure 5 As shown, the gate pad 40 is disposed around the third pad 43, and the orthogonal projection of the gate pad 40 in the thickness direction X also covers the orthogonal projection of the extension 24 in the thickness direction X.

[0107] In some embodiments, device structure 1 can be a power device, which may include a power field-effect transistor (FET). Power FETs have various structures, such as planar gate structures and trench gate structures. The sensor structure can be a temperature sensor used to detect the temperature of device structure 1. By detecting the temperature of device structure 1, it can be ensured that the device structure operates within a safe range, guaranteeing reliability and safety. The sensor structure can also be other types of sensors used for other detections of device structure 1; no specific limitations are made here.

[0108] According to the semiconductor device fabrication method provided in this application embodiment, a sensor structure 2 is set in the pad area A2. The sensor structure includes a thermistor 2, and the gate pad 2 is connected to the gate structure 11 and the thermistor 2 of the device structure 1, respectively. That is, the gate structure 11 and the thermistor 2 share a single pad, reducing the area occupied by the sensor structure and thus reducing the volume of the semiconductor device. Moreover, the sensor structure is integrated with the device structure 1, shortening the heat conduction path between the device structure 1 and the sensor structure, reducing the heat conduction delay time, and improving the sensor detection accuracy. In addition, the sensor structure is set in the pad area A2 without affecting the area of ​​the cell area A1, so as to achieve detection without affecting the performance of the device structure. Furthermore, the sensor structure does not participate in the current of the main circuit, which can shield interference and further improve the sensor detection accuracy.

[0109] Accordingly, this application also provides a power module. The power module includes a substrate and the semiconductor device from any of the above embodiments, wherein the substrate is used to support the semiconductor device.

[0110] For example, a power module can be used as one of a power amplifier, power converter, power controller, power management module, or power regulator. A power amplifier amplifies the power of an electrical signal. A power converter converts electrical energy from one form to another; for example, a power converter can be an AC / DC converter or a DC / DC converter. A power controller is a device for controlling the flow of power. A power management module manages the power supply, ensuring that power is stably and efficiently distributed to different parts of an electronic device. A power regulator adjusts the power output to meet the needs of a specific application.

[0111] On the other hand, embodiments of this application also provide a power conversion circuit. The power conversion circuit includes a circuit board and the semiconductor device in any of the above embodiments. The semiconductor device is electrically connected to the circuit board, and the power conversion circuit can be used for current conversion, voltage conversion, or power factor correction.

[0112] For example, the power conversion circuit can be used as one of an AC / DC converter, an AC / AC converter, a DC / DC converter, a DC / AC inverter, or a power factor correction (PFC) circuit, wherein the AC / DC converter is used to convert alternating current to direct current, the AC / AC converter is used to convert alternating current to alternating current, the DC / DC converter is used to convert direct current to direct current, the DC / AC inverter is used to convert direct current to alternating current, and the power factor correction circuit is used to improve the power factor of the power supply and reduce harmonic pollution of the power grid.

[0113] On the other hand, embodiments of this application also provide a vehicle. The vehicle includes a load and the power conversion circuit described in the above embodiments. The power conversion circuit is used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input the converted direct current to the load to supply power to the load.

[0114] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and are not limited in number; for example, a first object can be one or more.

[0115] In the description of this application, "multiple" means two or more.

[0116] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0117] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that, It includes a cell region and a pad region located on one side of the cell region; The cell region includes a device structure, and the device structure includes a gate structure; The pad area includes: Sensor structure, including thermistors; The gate pads are connected to the gate structure and the thermistor, respectively.

2. The semiconductor device according to claim 1, characterized in that, The orthographic projection of the gate pad in the thickness direction at least partially overlaps with the orthographic projection of the thermistor in the thickness direction.

3. The semiconductor device according to claim 1, characterized in that, The pad area also includes: A first dielectric layer covers the thermistor; the gate pad is located on the side of the first dielectric layer away from the thermistor and extends through the first dielectric layer to connect with the thermistor.

4. The semiconductor device according to claim 3, characterized in that, The thermistor includes a first end, a second end, and a main body portion connected between the first end and the second end; the gate pad penetrates the first dielectric layer and is connected to the first end; The pad area also includes: The third pad is located on the side of the first dielectric layer away from the thermistor and extends through the first dielectric layer to connect with the second end.

5. The semiconductor device according to claim 4, characterized in that, The orthographic projection of the gate pad in the thickness direction covers the orthographic projection of the first end portion in the thickness direction and at least partially overlaps with the orthographic projection of the main body portion in the thickness direction.

6. The semiconductor device according to claim 4, characterized in that, The thermistor further includes an extension portion, which is arranged around the integral structure formed by the first end portion, the second end portion and the main body portion. The extension portion is connected to the first end portion and spaced apart from the second end portion. The gate pad is also connected to the extension portion.

7. The semiconductor device according to claim 6, characterized in that, The gate pad is disposed around the third pad, and the orthographic projection of the gate pad in the thickness direction covers the orthographic projection of the extension in the thickness direction.

8. The semiconductor device according to claim 1, characterized in that, The thermistor is made of polycrystalline silicon.

9. The semiconductor device according to claim 1, characterized in that, The gate pad includes a first pad and a second pad, the first pad being connected to the gate structure and the second pad being connected to the thermistor.

10. The semiconductor device according to claim 1, characterized in that, The cell region also includes: A semiconductor body includes a first surface and a second surface disposed opposite each other in the thickness direction; the gate structure is located on the side of the semiconductor body closer to the first surface, or the gate structure extends from the first surface into the semiconductor body; An insulating layer is located between the semiconductor body and the gate structure; The pad area also includes: The semiconductor body, wherein the thermistor is located on the side of the semiconductor body closer to the first surface; The second dielectric layer is located between the semiconductor body and the thermistor.

11. The semiconductor device according to claim 10, characterized in that, The pad area also includes: The device structure is located between the semiconductor body and the second dielectric layer.

12. The semiconductor device according to claim 10, characterized in that, The cell region also includes: A gate resistor is located on the side of the semiconductor body near the first surface. The gate resistor is connected to the gate structure and extends from the gate structure to the pad area, where it is connected to the gate pad. The insulating layer is also located between the semiconductor body and the gate resistor.

13. The semiconductor device according to any one of claims 1-11, characterized in that, The device structure is a power device, and the sensor structure is a temperature sensor.

14. A method for fabricating a semiconductor device, characterized in that, The semiconductor device includes a cell region and a pad region located on one side of the cell region; the method includes: A device structure is formed in the cell region, the device structure including a gate structure; A sensor structure is formed in the pad area, the sensor structure including a thermistor; A gate pad is formed in the pad area, and the gate pad is connected to the gate structure and the thermistor respectively.

15. The method for fabricating a semiconductor device according to claim 14, characterized in that, The thermistor includes a first end, a second end, and a main body portion connected between the first end and the second end; The process of forming a gate pad in the pad area includes: A first dielectric layer is formed covering the thermistor; A first contact hole and a second contact hole are formed that penetrate the first dielectric layer, with the first contact hole exposing the first end and the second contact hole exposing the second end; A gate pad and a third pad are formed on the side of the first dielectric layer away from the thermistor. The gate pad also fills the first contact hole and is connected to the first end. The third pad also fills the second contact hole and is connected to the second end.

16. A power module, characterized in that, Including a substrate and as claimed in claim 1 13. The semiconductor device described in any of the above, wherein the substrate is used to support the semiconductor device.

17. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and as claimed in claim 1. The semiconductor device of the 13th embodiment is electrically connected to the circuit board.

18. A vehicle, characterized in that, The device includes a load and a power conversion circuit as described in claim 17, the power conversion circuit being used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

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