Test structure and test system, test method
By splitting the test pads into matrix-arranged test sub-pads, the number of structures under test is increased, solving the problem of excessively large test area occupied by the test structures, thereby expanding the effective chip area and improving test efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SEMICON MFG SOUTH CHINA CORP
- Filing Date
- 2024-12-19
- Publication Date
- 2026-06-26
AI Technical Summary
The test pads in the existing test structure are difficult to meet the requirements of advanced processes, resulting in the test structure occupying too large an area and affecting the area of the effective chip area.
The test pads are divided into multiple test sub-pads arranged in a matrix along the first and second directions, and the number of structures under test is increased, while the use of test cell areas is reduced, thereby reducing the area occupied by the test structures.
While testing the same number of structures under test, the use of test cell areas was reduced, the effective chip area was increased, and test efficiency and accuracy were improved.
Smart Images
Figure CN122294907A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a test structure, test system, and test method. Background Technology
[0002] In the semiconductor manufacturing industry, Wafer Acceptance Test (WAT) is a crucial process control and monitoring step. WAT is defined as the process of measuring the electrical parameters of a specific test structure after wafer fabrication and before quality inspection. The purpose of this test is to evaluate the process condition of each wafer, ensure the quality and stability of the semiconductor manufacturing process, and determine whether the wafer meets the electrical specifications of the process technology platform.
[0003] WAT testing is performed on specific test keys on the wafer, which are typically placed in dicing slots and tested by test probes that contact the test pads.
[0004] Currently, the test pads (pads) in the test structure are insufficient to meet the requirements of advanced processes. Summary of the Invention
[0005] The problem solved by the embodiments of the present invention is to provide a test structure, test system and test method, which is beneficial to reduce the area occupied by the test structure and increase the area of the effective chip area.
[0006] To address the aforementioned problems, embodiments of the present invention provide a test structure, comprising: a substrate, the substrate including one or more test unit regions; test pads located on the substrate of the test unit regions, the test pads including multiple test sub-pads arranged in a matrix at intervals along a first direction and a second direction, the first direction being perpendicular to the second direction; and multiple structures under test located on the substrate of the test unit regions, the structures under test being adjacent to the test pads, and the test structures being electrically connected to the test sub-pads.
[0007] Optionally, the test structure further includes: an insulating layer located on a substrate between adjacent test sub-pads, on a substrate between adjacent test pads, and on a substrate between the test pads and the structure under test.
[0008] Optionally, the insulating layer has a dimension of 1 micrometer to 5 micrometers in the first direction; the insulating layer has a dimension of 1 micrometer to 5 micrometers in the second direction.
[0009] Optionally, the insulating layer may be made of one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.
[0010] Optionally, adjacent test sub-pads are spaced at the same distance in the first direction; adjacent test sub-pads are spaced at the same distance in the second direction.
[0011] Optionally, the multiple test sub-pads may have the same shape and size.
[0012] Optionally, two of the test sub-pads constitute a test group, and the structure under test (DUT) is adjacent to the test group; the test structure further includes: a first connection located between the DUT and one of the test sub-pads in the test group, and the DUT is electrically connected to one of the test sub-pads in the test group through the first connection; and a second connection located between the DUT and another test sub-pad in the test group, and the DUT is electrically connected to the other test pad in the test group through the second connection.
[0013] Optionally, the number of test sub-pads is an even number.
[0014] Optionally, the material of the test sub-pad includes one or both of aluminum and copper.
[0015] Optionally, the test structure further includes alignment marks located on the substrate between adjacent test sub-pads.
[0016] Accordingly, embodiments of the present invention also provide a testing system, including: the testing structure provided by the present invention; a probe card device including a plurality of probes, wherein the probes are used to contact the test sub-pads to realize electrical testing of the structure under test.
[0017] Optionally, the distance between adjacent probes in the first direction is equal to the distance between the center points of adjacent test sub-pads in the first direction; the distance between adjacent probes in the second direction is equal to the distance between the center points of adjacent test sub-pads in the second direction.
[0018] Optionally, adjacent test sub-pads are spaced at the same distance in the first direction, and adjacent test sub-pads are spaced at the same distance in the second direction; the distance D1 between the center points of adjacent test sub-pads in the first direction is D1 = a1 + b1, where a1 refers to the size of the test sub-pad in the first direction; b1 refers to the spacing between adjacent test sub-pads in the first direction; the distance D2 between the center points of adjacent test sub-pads in the second direction is D2 = a2 + b2, where a2 refers to the size of the test sub-pad in the second direction; b2 refers to the spacing between adjacent test sub-pads in the second direction.
[0019] Accordingly, embodiments of the present invention also provide a testing method, comprising: providing the test structure provided by the present invention; applying a test electrical signal to the test pad for performing electrical testing on the structure under test.
[0020] Optionally, two of the test sub-pads constitute a test group, and the structure under test is adjacent to the test group; the step of applying a test electrical signal to the test pads to perform electrical testing on the structure under test includes: sequentially applying a test electrical signal to each of the test groups to perform electrical testing on the structure under test.
[0021] Optionally, the step of sequentially applying test electrical signals to each of the test groups includes: sequentially applying test electrical signals to each of the test groups through a probe.
[0022] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:
[0023] This invention provides a test structure. The substrate includes one or more test unit areas, test pads located on the substrate of the test unit areas, and multiple test sub-pads arranged in a matrix along a first direction and a second direction, the first direction being perpendicular to the second direction. Multiple structures under test (DUTs) are located on the substrate of the test unit areas, adjacent to the test pads and electrically connected to the test sub-pads. Compared to existing solutions where only one DUT and two test pads are provided in a test unit area, this invention increases the number of test sub-pads in the test unit area by dividing the test pads into multiple test sub-pads arranged in a matrix along the first and second directions. Correspondingly, this also increases the number of DUTs in the test unit area. This means that, when testing the same number of DUTs, the test unit area used in this invention is reduced, resulting in a smaller area occupied by the test structure and thus increasing the area of the effective chip region. Attached Figure Description
[0024] Figure 1 This is a schematic diagram of an embodiment of the test structure of the present invention;
[0025] Figure 2 This is a schematic diagram corresponding to an embodiment of the testing system of the present invention;
[0026] Figure 3 This is a flowchart of the steps corresponding to one embodiment of the testing method of the present invention. Detailed Implementation
[0027] As the background technology indicates, the test pads (soldering pads) in the test structure are insufficient to meet the requirements of advanced manufacturing processes. Specifically, in WAT testing, the structure under test (TSK) is placed in the test cell area. The TSK needs to be connected to test pads to form electrical signals through external circuitry for data collection and analysis. However, the test pads in the test cell area are dedicated pads, meaning that two test pads can only be used for the connection testing of a single TSK. This results in an excessively large area occupied by the test structure, which in turn affects the effective chip area.
[0028] To address the technical problem, embodiments of the present invention provide a test structure, comprising: a substrate, the substrate including one or more test unit areas; test pads located on the substrate of the test unit areas, the test pads including multiple test sub-pads arranged in a matrix at intervals along a first direction and a second direction, the first direction being perpendicular to the second direction; and multiple structures under test located on the substrate of the test unit areas, the structures under test being adjacent to the test pads, and the test structures being electrically connected to the test sub-pads.
[0029] In the test structure provided by this embodiment of the invention, the substrate includes one or more test unit areas, test pads located on the substrate of the test unit areas, and test pads including multiple test sub-pads arranged in a matrix at intervals along a first direction and a second direction, the first direction being perpendicular to the second direction. Multiple structures under test (SUTs) are located on the substrate of the test unit areas, the SUTs being adjacent to the test pads and electrically connected to the test sub-pads. Compared to the existing scheme where only one SUT and two test pads are set in one test unit area, this embodiment of the invention increases the number of test sub-pads in the test unit area by dividing the test pads into multiple test sub-pads arranged in a matrix at intervals along the first and second directions. Correspondingly, the number of SUTs in the test unit area is also increased. This means that when testing the same number of SUTs, the test unit area used in this embodiment of the invention is reduced, resulting in a smaller area occupied by the test structure and thus increasing the area of the effective chip area.
[0030] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0031] Figure 1 This is a schematic diagram of an embodiment of the test structure of the present invention.
[0032] The test structure includes: a substrate (not shown), the substrate including one or more test cell regions 130; and test pads 100 located on the substrate of the test cell regions 130, the test pads 100 including multiple pads along a first direction (e.g., Figure 1 (as shown in the X direction) and the second direction (as shown in the X direction) Figure 1 Test sub-pads 101 are arranged in a matrix at intervals (as shown in the Y direction), with the first direction perpendicular to the second direction; multiple structures under test 190 are located on the substrate of the test unit area 130, the structures under test 190 are adjacent to the test pads 100, and the test structures are electrically connected to the test sub-pads 101.
[0033] Specifically, compared to the existing test unit area 130 which only has one structure under test 190 and two test pads 100, this embodiment increases the number of test sub-pads 101 in the test unit area 130 by dividing the test pads 100 into multiple test sub-pads 101 arranged in a matrix along the first and second directions. Correspondingly, the number of structures under test 190 in the test unit area 130 is also increased. This means that when testing the same number of structures under test 190, the test unit area 130 used in this embodiment is reduced, resulting in a smaller area occupied by the test structures and thus increasing the area of the effective chip area.
[0034] The substrate provides a process platform for setting up test structures.
[0035] In this embodiment, the substrate includes a silicon substrate. The substrate material can also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate. The substrate can also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The substrate material can be suitable for process requirements or easy to integrate.
[0036] Specifically, the test unit area 130 is the area where the test pads 100 and the structure under test 190 are set.
[0037] It should be noted that the substrate also includes a chip area adjacent to the test cell area 130.
[0038] Specifically, the chip area is used as a region for setting up valid chips. By setting up test pads 100 and structure under test 190 in the test unit area 130, electrical tests are performed on the test structure, thereby enabling the monitoring of valid chips in the chip area.
[0039] It should be noted that the test pad 100 is used as the loading terminal of the test signal. The test pad 100 is electrically connected to the structure under test 190. By applying a test signal to the test pad 100, the test signal can enter the structure under test 190 through the test pad 100 to complete the electrical test of the structure under test 190.
[0040] In this embodiment, the test pad 100 includes a plurality of test sub-pads 101 arranged in a matrix at intervals along the first direction and the second direction.
[0041] Specifically, compared to the scheme where the test unit area 130 only has one structure under test 190 and two test pads 100, this embodiment divides the area where the test pads 100 are set into regions, so that the test pads 100 include multiple test sub-pads 101 arranged in a matrix at intervals along the first direction and the second direction. This increases the number of test sub-pads 101 in the test unit area 130, and correspondingly, also increases the number of structures under test 190 in the test unit area 130. This means that when testing the same number of structures under test 190, the test unit area 130 used in this embodiment of the invention is reduced, so that the area occupied by the test structure is smaller, thereby increasing the area of the effective chip area.
[0042] In this embodiment, adjacent test sub-pads 101 are spaced at the same distance in the first direction, and adjacent test sub-pads 101 are spaced at the same distance in the second direction.
[0043] It should be noted that the adjacent test sub-pads 101 are spaced at the same distance in the first direction, and the adjacent test sub-pads 101 are spaced at the same distance in the second direction. This means that the area occupied by the test pads 100 formed by multiple test sub-pads 101 is matrix-shaped, which maximizes the number of test sub-pads 101 under the premise of the same area.
[0044] It should also be noted that the adjacent test sub-pads 101 are spaced at the same distance in the first direction, and the adjacent test sub-pads 101 are spaced at the same distance in the second direction. In the test system composed of the test structure and the pins, the spacing between adjacent pins in the first direction and the spacing between adjacent pins in the second direction are made the same. In the subsequent process of performing electrical tests on the structure under test 190 sequentially through the pins, the distance the pins move in the first direction and the distance the pins move in the second direction are the same, thereby reducing the difficulty of performing electrical tests on the structure under test 190.
[0045] As an example, the multiple test sub-pads 101 are all identical in shape and size.
[0046] In this embodiment, the two test sub-pads 101 constitute a test group 102, and the structure under test 190 is adjacent to the test group 102.
[0047] It should be noted that the two test sub-pads 101 constitute a test group 102. During the subsequent electrical testing of the structure under test 190, the two test sub-pads 101 and the structure under test 190 can form a test path, so that one test sub-pad 101 in the test group 102 serves as the test signal input terminal and the other test sub-pad 101 serves as the test signal output terminal.
[0048] It should also be noted that the structure under test 190 is adjacent to the test group 102, which can reduce the distance between the structure under test 190 and the test group 102, thereby reducing the transmission distance of the test signal between the structure under test 190 and the test group 102.
[0049] In this embodiment, the number of test sub-pads 101 is an even number.
[0050] Specifically, an even number of test sub-pads 101 can make the test pads 100 form a matrix, thereby maximizing the increase in the number of test sub-pads 101 under the premise of the same area.
[0051] like Figure 1 As shown, the number of test sub-pads 101 is 4.
[0052] In this embodiment, the material of the test sub-pad 101 includes one or both of aluminum and copper.
[0053] Specifically, aluminum and copper are commonly used conductive materials for the test sub-pad 101, which can improve the electrical connection performance between the pin and the test sub-pad 101.
[0054] In this embodiment, the test structure further includes a first connection 108, located between the structure under test 190 and one of the test sub-pads 101 of the test group 102, and the structure under test 190 is electrically connected to one of the test sub-pads 101 of the test group 102 through the first connection 108.
[0055] It should be noted that the first connection 108 is used to electrically connect the structure under test 190 to one of the test sub-pads 101 of the test group 102. As an example, the first connection 108 and one of the test sub-pads 101 of the test group 102 are used as test signal input terminals.
[0056] In this embodiment, the first connection 108 is on the same layer as the test pad 100, and the first connection 108 is located in the dielectric layer (i.e., the insulating layer 160) between the test pad 100 and the structure under test 190.
[0057] In this embodiment, the material of the first connecting line 108 includes copper.
[0058] In this embodiment, the test structure further includes a second connection 109, located between the structure under test 190 and another test sub-pad 101 of the test group 102, and the structure under test 190 is electrically connected to another test pad 100 of the test group 102 through the second connection 109.
[0059] It should be noted that the second connection 109 is used to electrically connect the structure under test 190 to another test sub-pad 101 of the test group 102. As an example, the first connection 108 and another test sub-pad 101 of the test group 102 are used as test signal output terminals.
[0060] In this embodiment, the second connection 109 is on the same layer as the test pad 100, and the second connection 109 is located in the dielectric layer (i.e., the insulating layer 160) between the test pad 100 and the structure under test 190.
[0061] In this embodiment, the material of the second connection 109 includes copper.
[0062] In this embodiment, the test structure further includes an insulating layer 160 located on a substrate between adjacent test sub-pads 101, on a substrate between adjacent test pads 100, and on a substrate between the test pads 100 and the structure under test 190.
[0063] It should be noted that the insulating layer 160 provides electrical isolation between adjacent test sub-pads 101, adjacent test pads 100, and the test pads 100 and the structure under test 190. This reduces the risk of leakage between adjacent test sub-pads 101, adjacent test pads 100, and the test pads 100 and the structure under test 190, thereby improving the accuracy of the test structure in performing electrical tests on the structure under test 190.
[0064] It should also be noted that the size of the insulating layer 160 in the first direction should not be too large or too small. If the size of the insulating layer 160 in the first direction is too large, with a fixed area for the test pads 100, the number of test sub-pads 101 will decrease, and with a fixed number of structures under test 190, the area occupied by the test structures will increase, thereby reducing the area of the effective chip area. If the size of the insulating layer 160 in the first direction is too small, the risk of leakage between adjacent test sub-pads 101 will increase, affecting the accuracy of the test structure in performing electrical tests on the structures under test 190. Therefore, in this embodiment, the size of the insulating layer 160 in the first direction is 1 micrometer to 5 micrometers.
[0065] Specifically, the size of the insulating layer 160 in the second direction should not be too large or too small. If the size of the insulating layer 160 in the second direction is too large, the number of test sub-pads 101 will decrease when the area of the test pads 100 is fixed, and the area occupied by the test structure will increase when the number of structures under test 190 remains unchanged, thereby reducing the area of the effective chip area. If the size of the insulating layer 160 in the second direction is too small, the risk of leakage between adjacent test sub-pads 101 will increase, affecting the accuracy of the electrical testing of the structure under test 190 by the test structure. Therefore, in this embodiment, the size of the insulating layer 160 in the second direction is 1 micrometer to 5 micrometers.
[0066] In this embodiment, the material of the insulating layer 160 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.
[0067] Specifically, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide are all commonly used dielectric materials in insulating layers 160, possessing good insulation properties and providing high electrical isolation.
[0068] In this embodiment, the test structure further includes an alignment mark 120 located on the substrate between adjacent test sub-pads 101.
[0069] It should be noted that by setting the alignment mark 120 in the test structure, the pin can achieve initial positioning with the test pad 100 in the subsequent test method. Then the pin moves on the test sub-pad 101 along the first direction and the second direction to apply a test signal to the test sub-pad 101.
[0070] Specifically, alignment mark 120 is located in the insulating layer 160 on the substrate between adjacent test sub-pads 101.
[0071] Accordingly, embodiments of the present invention also provide a testing system. Wherein, Figure 2 A schematic diagram corresponding to one embodiment of the test system of the present invention is shown. For ease of illustration, Figure 2 Only the test pads and pins in the test system are shown.
[0072] The testing system includes: the testing structure provided by the present invention; and a probe card device including multiple probes 188, wherein the probes 188 are used to contact the test sub-pad 101 to realize the electrical testing of the structure 190 under test.
[0073] It should be noted that by dividing the test pad 100 into multiple parts along the first direction (e.g., Figure 2 (as shown in the X direction) and the second direction (as shown in the X direction) Figure 2 The test sub-pads 101 arranged in a matrix (as shown in the X direction) increase the number of test sub-pads 101 in the test unit area 130, and correspondingly increase the number of structures under test 190 in the test unit area 130. This means that when testing the same number of structures under test 190, the number of test unit areas 130 used is reduced, which reduces the area occupied by the test structure and increases the area of the effective chip area. This also means that the space occupied by the probe card device is reduced, thereby further miniaturizing the test system and improving its performance.
[0074] Specifically, the detailed description of the test structure will not be repeated here; please refer to the description of the test structure in the foregoing embodiments.
[0075] As an example, adjacent test sub-pads 101 are spaced by the same distance in the first direction, and adjacent test sub-pads 101 are spaced by the same distance in the second direction.
[0076] It should be noted that the adjacent test sub-pads 101 are spaced at the same distance in the first direction, and the adjacent test sub-pads 101 are spaced at the same distance in the second direction. This means that the area occupied by the test pads 100 formed by multiple test sub-pads 101 is matrix-shaped, which maximizes the number of test sub-pads 101 under the premise of the same area.
[0077] During electrical testing (e.g., wafer receiving test, WAT) of the structure under test 190, probes 188 in the probe card device are used to electrically connect to the test pads 100, thereby measuring the electrical parameters of the structure under test 190 through probes 188.
[0078] Specifically, during the process of electrically connecting the probe 188 in the probe card device to the test pad 100, the probe 188 is electrically connected to the center point of the test sub-pad 101.
[0079] In this embodiment, the distance between adjacent probes 188 in the first direction is equal to the distance between the center points of adjacent test sub-pads 100 in the first direction; the distance between adjacent probes 188 in the second direction is equal to the distance between the center points of adjacent test sub-pads 100 in the second direction.
[0080] It should be noted that during the subsequent application of test electrical signals to the test pads 100 for electrical testing of the structure under test 190, probes 188 are used to sequentially apply test electrical signals to each test group 102. By ensuring that the distance between adjacent probes 188 in the first direction is equal to the distance between the center points of adjacent test sub-pads 100 in the first direction, and the distance between adjacent probes 188 in the second direction is equal to the distance between the center points of adjacent test sub-pads 100 in the second direction, after the probes 188 have completed testing the test group 102, as the probes 188 move along the first or second direction to the adjacent test group 102, the probes 188 can still contact the center point of the test sub-pads 101 in the adjacent test group 102. The contact between the probes 188 and the center point of the test sub-pads 101 ensures the accurate transmission of the test signal, thereby obtaining the most accurate test data.
[0081] In this embodiment, the distance D1 between the center points of adjacent test sub-pads 100 in the first direction is a1 + b1, where a1 refers to the size of the test sub-pad 100 in the first direction; and b1 refers to the spacing between adjacent test sub-pads 100 in the first direction.
[0082] In this embodiment, the distance D2 between the center points of adjacent test sub-pads 100 in the second direction is a2 + b2, where a2 refers to the size of the test sub-pad 100 in the second direction; and b2 refers to the spacing between adjacent test sub-pads 100 in the second direction.
[0083] Accordingly, embodiments of the present invention also provide a testing method. Wherein, Figure 3 A flowchart of the steps corresponding to one embodiment of the test method of the present invention is shown.
[0084] Reference Figures 1 to 3 Step S1: Provide the test structure provided by the present invention.
[0085] Specifically, the detailed description of the test structure will not be repeated here; please refer to the description of the test structure in the foregoing embodiments.
[0086] In this embodiment, the two test sub-pads 101 constitute a test group 102, and the structure under test 190 is adjacent to the test group 102.
[0087] It should be noted that the two test sub-pads 101 constitute a test group 102. During the subsequent electrical testing of the structure under test 190, the two test sub-pads 101 and the structure under test 190 can form a test path, so that one test sub-pad 101 in the test group 102 serves as the test signal input terminal and the other test sub-pad 101 serves as the test signal output terminal.
[0088] It should also be noted that the structure under test 190 is adjacent to the test group 102, which can reduce the distance between the structure under test 190 and the test group 102, thereby reducing the transmission distance of the test signal between the structure under test 190 and the test group 102.
[0089] Reference Figures 1 to 3 Step S2: Apply a test electrical signal to the test pad 100 to perform electrical testing on the structure under test 190.
[0090] It should be noted that by dividing the test pad 100 into multiple test sub-pads 101 arranged in a matrix along the first and second directions, the number of test sub-pads 101 set in the test unit area 130 is increased. This means that the spacing between adjacent test sub-pads 101 is reduced. Correspondingly, during the electrical testing of the structure under test 190, the moving distance of the probe 188 between the test sub-pads 101 is reduced, thereby improving the testing efficiency.
[0091] In this embodiment, the step of applying a test electrical signal to the test pad 100 to perform electrical testing on the structure under test 190 includes: sequentially applying a test electrical signal to each of the test groups 102 to perform electrical testing on the structure under test 190.
[0092] Specifically, test electrical signals are applied to each of the test groups 102 in sequence to perform electrical tests on the structure under test 190, thereby reducing the problem of mutual signal interference between different structures under test 190.
[0093] In this embodiment, the step of sequentially applying test electrical signals to each test group 102 includes: sequentially applying test electrical signals to each test group 102 through probe 188.
[0094] Specifically, probe 188 is used to electrically connect to test sub-pad 101 in test group 102, thereby measuring the electrical parameters of the structure under test 190 through probe 188.
[0095] It should be noted that during the process of sequentially applying test electrical signals to each group of test groups 102, after the test of a test structure is completed, the probe 188 is moved to the center point of the test sub-pad 101 of the adjacent test group 102 along the first direction or the second direction and electrically connected to it.
[0096] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A test structure, characterized by, include: A substrate, the substrate comprising one or more test cell regions; Test pads are located on the base of the test unit area. The test pads include multiple test sub-pads arranged in a matrix at intervals along a first direction and a second direction, wherein the first direction is perpendicular to the second direction. Multiple structures under test are located on the substrate of the test unit area. The structures under test are adjacent to the test pads and are electrically connected to the test sub-pads.
2. The test structure of claim 1, wherein, The test structure further includes: an insulating layer located on a substrate between adjacent test sub-pads, on a substrate between adjacent test pads, and on a substrate between the test pads and the structure under test.
3. The test structure of claim 2, wherein, The insulating layer has a dimension of 1 micrometer to 5 micrometers in the first direction; The insulating layer has a dimension of 1 micrometer to 5 micrometers in the second direction.
4. The test structure as described in claim 2, characterized in that, The insulating layer is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.
5. The test structure as described in claim 1, characterized in that, The adjacent test sub-pads are spaced at the same distance in the first direction; The adjacent test sub-pads are spaced at the same distance in the second direction.
6. The test structure as described in claim 1, characterized in that, The multiple test sub-pads are all identical in shape and size.
7. The test structure as described in claim 1, characterized in that, Two of the test sub-pads form a test group, and the structure under test is adjacent to the test group; The test structure further includes: a first connection line located between the structure under test and one of the test sub-pads of the test group, and the structure under test is electrically connected to one of the test sub-pads of the test group through the first connection line; The second connection is located between the structure under test and another test pad in the test group, and the structure under test is electrically connected to the other test pad in the test group through the second connection.
8. The test structure as described in claim 1, characterized in that, The number of test sub-pads is an even number.
9. The test structure as described in claim 1, characterized in that, The material of the test sub-pad includes one or both of aluminum and copper.
10. The test structure as described in claim 1, characterized in that, The test structure also includes alignment marks located on the substrate between adjacent test sub-pads.
11. A testing system, characterized in that, include: The test structure as described in any one of claims 1 to 10; The probe card device includes multiple probes that are used to contact the test pads to perform electrical testing on the structure under test.
12. The testing system as described in claim 11, characterized in that, The distance between adjacent probes in the first direction is equal to the distance between the center points of adjacent test sub-pads in the first direction; The distance between adjacent probes in the second direction is equal to the distance between the center points of adjacent test sub-pads in the second direction.
13. The testing system as described in claim 12, characterized in that, The adjacent test sub-pads are spaced at the same distance in the first direction, and the adjacent test sub-pads are spaced at the same distance in the second direction; The distance D1 between the center points of adjacent test sub-pads in the first direction is D1 = a1 + b1, where a1 refers to the dimension of the test sub-pad in the first direction; and b1 refers to the spacing between adjacent test sub-pads in the first direction. The distance D2 between the center points of adjacent test sub-pads in the second direction is D2 = a2 + b2, where a2 refers to the dimension of the test sub-pad in the second direction; and b2 refers to the spacing between adjacent test sub-pads in the second direction.
14. A testing method, characterized in that, include: Provide a test structure as described in any one of claims 1 to 10; A test electrical signal is applied to the test pad to perform electrical testing on the structure under test.
15. The test method as described in claim 14, characterized in that, Two of the test sub-pads form a test group, and the structure under test is adjacent to the test group; The step of applying a test electrical signal to the test pad to perform electrical testing on the structure under test includes: sequentially applying a test electrical signal to each of the test groups to perform electrical testing on the structure under test.
16. The test method as described in claim 15, characterized in that, The step of sequentially applying test electrical signals to each of the test groups includes: sequentially applying test electrical signals to each of the test groups through a probe.