An alignment mark, a method of manufacturing the same and a mask plate

Abstract

The application provides an alignment mark, a preparation method thereof and a mask plate. The alignment mark is formed on a substrate and comprises a plurality of mark structures arranged in parallel with each other. The mark structure comprises a plurality of alignment blocks arranged discontinuously. By dividing the existing strip-shaped alignment mark into the discontinuous alignment blocks, the pattern density of the alignment mark region and the functional structure region can be adjusted more conveniently, the pattern density of the two regions is adapted to each other, the process compatibility of the alignment mark and the functional structure is improved, and the preparation of the unnecessary process level and the mask plate is reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to an alignment mark, a method for preparing the same, and a mask. Background Technology

[0002] In the manufacturing process of semiconductor integrated circuits, it is often necessary to cover or remove material at specific locations on existing structural layers to form the required components of the integrated circuit. Therefore, achieving alignment between various structural layers is crucial. Alignment is closely related to photolithography. During photolithography, to ensure the overlay accuracy between device layers, alignment marks are usually placed in the front-end process layers for alignment with subsequent layers.

[0003] In existing technologies, alignment marks formed on wafers are generally periodic patterns, typically formed by the periodic arrangement of multiple stripe structures. However, the application of current stripe structures in some processes has limitations. For example, in deep silicon etching, the loading effect leads to different etching rates in regions with different pattern densities. Factors affecting the etching rate mainly include material transport and reactant consumption. Regarding material transport, for the same process time, larger trench width patterns have higher etching rates and corresponding greater etching depths; similarly, regarding reactant consumption, the etching rate varies in different regions depending on the exposed silicon area. Therefore, existing stripe alignment marks, due to their large pattern size, have etching rates that differ significantly from the actual structural regions, making them incompatible. Directly using existing stripe alignment marks in deep silicon etching often results in defect sources and fails to achieve alignment. To address this issue, alignment marks are typically omitted at deep silicon etching layers, and an additional mask with alignment marks is fabricated for alignment at that layer and subsequent layers, which increases costs.

[0004] Therefore, it is necessary to develop a new alignment mark that can adapt to the requirements of various processes and has better compatibility at different levels to avoid the problems in the prior art.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] The purpose of this invention is to provide a novel alignment mark to achieve better process compatibility. To address the aforementioned problems, an alignment mark, its preparation method, and a mask are provided below.

[0007] In a first aspect, this application provides an alignment mark formed on a substrate. The alignment mark includes a multi-channel marking structure arranged parallel to each other, and the marking structure includes multiple discontinuous alignment blocks. By dividing the existing strip-shaped alignment mark into discontinuous multi-segment alignment blocks, the pattern density of the alignment mark region and the functional structure region can be adjusted more conveniently, ensuring that the pattern densities of the two are compatible. This improves the process compatibility between the alignment mark and the functional structure, and reduces potentially unnecessary process layers and mask fabrication.

[0008] In some embodiments, adjacent multiple marking structures are equidistantly distributed, and the multiple alignment blocks in each marking structure are arranged equidistantly or non-equidistantly. The alignment blocks can be adjusted to indicate different process conditions.

[0009] In some embodiments, the alignment marks are trench structures or protrusion structures. Compatible with deposition and removal processes in semiconductor structure fabrication, the alignment marks can be formed simultaneously with the formation of the functional structure.

[0010] In some embodiments, a process layer is formed on the substrate; a functional structure is formed on the process layer; the process layer is any one of an insulating layer, an epitaxial layer, or a dielectric layer.

[0011] In some embodiments, the alignment marks are provided in at least one set, and the alignment marks are formed at at least one corner of the process layer or at least one corner of the functional structure.

[0012] In some embodiments, the spacing of the alignment blocks is determined based on the graphic density of the functional structure, such that the graphic density of the alignment marks is adapted to the graphic density of the functional structure. The graphic density can be easily adjusted by adjusting the spacing of the alignment blocks in the alignment marks.

[0013] In some embodiments, the alignment marks are formed on a deep silicon etching process layer, and the structural parameters of the alignment marks are determined by the pattern density of the functional structure of the deep silicon etching process layer.

[0014] In a second aspect, this application provides a mask plate including alignment mark patterns, the alignment mark patterns being used to form an alignment mark as described in any one of the first aspects.

[0015] Thirdly, this application provides a method for preparing alignment marks, comprising: providing a mask having an alignment mark pattern; providing a substrate, and transferring the alignment mark pattern to the surface of the substrate using photolithography and etching processes to form alignment marks.

[0016] In some embodiments, the etching process is a dry etching process or a wet etching process.

[0017] Compared with the prior art, the beneficial effects of the present invention mainly include the following: by dividing the existing strip-shaped alignment marks into discontinuous multi-segment alignment blocks, it is easier to adjust the pattern density of the alignment mark area and the functional structure area, ensuring that the pattern density of the two is compatible, thereby improving the compatibility of the alignment marks and reducing potentially unnecessary process layers and mask preparation. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of a semiconductor structure provided by the present invention.

[0020] Figure 2 A schematic diagram of alignment marks in the prior art provided by the present invention.

[0021] Figure 3 This is a schematic diagram of an alignment mark provided in Embodiment 1 of the present invention. Detailed Implementation

[0022] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front, or back, are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the present invention.

[0023] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0024] The steps in the following embodiments do not correspond one-to-one with the contents of the invention.

[0025] Example 1

[0026] like Figure 1The diagram illustrates a semiconductor structure according to the present invention. Alignment marks 2 and a functional structure 3 are formed on a substrate 1. The functional structure 3 can be any existing semiconductor structure, such as a metal interconnect structure, a transistor, or a MEMS structure. In this embodiment, the substrate 1 is single-crystal silicon; in other embodiments, the substrate 1 can include various semiconductor materials, such as germanium, silicon germanium, gallium arsenide, or silicon carbide; similarly, the substrate 1 can also include other layered structures, such as at least one of an epitaxial layer, a silicon nitride layer, or a silicon dioxide layer.

[0027] In some embodiments, alignment marks 2 may be provided in at least one set, and the number and position of the alignment marks 2 may be determined according to design requirements. For example, in some embodiments, alignment marks 2 may be formed at at least one corner of the substrate 1; in some embodiments, alignment marks 2 may be formed at at least one corner of the functional structure 3; in some embodiments, alignment marks 2 may be formed between adjacent functional structures 3; in some embodiments, alignment marks 2 may be provided at the central part of the substrate 1.

[0028] refer to Figure 2 A schematic diagram of a prior art alignment mark is shown. The alignment mark 2 is a marking pattern formed by the periodic arrangement of multiple stripe structures 20. When formed on a substrate 1, it typically exhibits a periodic pattern structure with protrusions and grooves. Figure 2 As shown, the alignment mark 2 is formed by periodically arranging nine strip structures 20. Each strip structure 20 has a width of 'a' and a length of 'c'. The spacing between adjacent strip structures 20 is the same, which is 'b' in this case. The total width of the alignment mark 2 is 'd'. It can be understood that the specific dimensions of the alignment mark 2 need to be confirmed based on product requirements. Taking a product's critical dimension (CD) of 0.3 μm as an example, the width 'a' of the strip structure 20 can be 1.6 μm, and the length 'c' can be 38 μm.

[0029] However, for existing alignment marks 2 (e.g., ASML AH53), since their basic unit is a strip structure 20, incompatibility issues arise between alignment marks 2 and functional structure 3 in many processes during design or fabrication. The main reason for this problem is the difference in pattern density between alignment marks 2 and functional structure 3; that is, the significant differences in size and distribution between alignment marks 2 and functional structure 3 make it impossible to simultaneously achieve precise fabrication of both structures during processing. These problems are particularly noticeable in material removal processes, such as etching and chemical mechanical polishing.

[0030] This section uses deep silicon etching as an example. It's understandable that due to the loading effect, regions with different pattern densities on the substrate will exhibit varying etching rates. From a microscopic perspective, the root cause of the loading effect is the material transport rate. In the formed trench structure, a wider trench facilitates the transport of material towards the bottom, resulting in a faster etching rate. That is, within the same processing time, a larger trench width leads to a greater etching depth, potentially causing different etching rates between alignment mark 2 and functional structure 3. For example, if alignment mark 2 is larger than functional structure 3, its etching rate will be faster. Similarly, from a macroscopic perspective, the root cause of the loading effect is the reactant consumption rate. For instance, in the alignment mark 2 region, the exposed silicon area is smaller, resulting in slower consumption and also contributing to the difference in etching rate. Therefore, directly using existing strip-shaped alignment marks in current deep silicon etching processes often results in defect sources and fails to achieve the desired alignment. To address this issue, alignment marks are typically removed at deep silicon etching layers. Instead, an additional mask with alignment marks is fabricated for alignment at that layer and subsequent layers, which increases costs.

[0031] To address the compatibility issues of alignment mark 2 caused by the difference in graphic density between alignment mark 2 and functional structure 3, this application proposes a novel alignment mark design that can significantly improve its compatibility in different processes.

[0032] refer to Figure 3 This invention provides an alignment mark 2, which comprises multiple marking structures 21 arranged parallel to each other. Each marking structure 21 includes multiple discontinuously arranged alignment blocks 210. In this embodiment, the alignment mark 2 is a periodic structure. The total length of the alignment mark 2 is c (i.e., the length of the marking structure 21), and the total width is d. The width of the marking structure 21 is a (i.e., the width of the alignment block 210), and the spacing between adjacent marking structures 21 is b. Each alignment block 210 has the same size and a width of a, and the spacing between two adjacent alignment blocks 210 within the same marking structure 21 is e. It can be understood that in this embodiment... Figure 3 The alignment mark 2 shown can be regarded as... Figure 2The alignment mark 2 shown is obtained by segmenting each strip structure 20. Based on this, the alignment mark 2 provided in this embodiment can have the outer contour of the alignment mark 2 in the prior art, with extremely high compatibility, and can naturally achieve the alignment function of the alignment mark 2 in the prior art. On the other hand, segmenting the strip structure 20 can obtain various alignment marks with adjustable graphic density. In this way, by simply adjusting the size and spacing of the alignment block 210, a graphic density adapted to the functional structure 3 can be obtained, thereby solving the incompatibility problem between the two. Taking the critical dimension (CD) of the product as an example, the strip structure 20 can be cut into alignment blocks 210 of at least 0.3 μm in size. Of course, adaptive adjustments can also be made according to the actual situation.

[0033] In this embodiment, Figure 3 The provided alignment mark 2 is a periodic structure, with each mark structure 21 having a substantially similar length and width. Within the mark structure 21, the size and spacing of the alignment blocks 210 are identical. However, in other embodiments, the size (i.e., length and width) and spacing of the alignment blocks 210 can differ. Therefore, the specific division of the mark structure 21 is not limited and depends on the actual product evaluation design. Taking deep silicon etching as an example, the structural parameters of the alignment mark, including the number of mark structures 21, the spacing between adjacent mark structures 21, and the length, width, spacing, and number of alignment blocks 210, are determined by the pattern density of the functional structure 3 in the deep silicon etching process layer. In other words, the pattern density of the alignment mark 2 is the degree to which the alignment mark 2 region will not exhibit a significant loading effect during deep silicon etching.

[0034] In this embodiment, the alignment mark 2 is a graphic with a rectangular outline formed by a periodic arrangement of multiple alignment blocks 210; in other embodiments, it may be other graphics, such as a cross-shaped graphic formed by a periodic arrangement of multiple alignment blocks 210.

[0035] The present invention also provides a mask having a pattern for forming an alignment mark provided in this application.

[0036] This invention also provides a method for preparing alignment marks, comprising the following steps: providing a mask having an alignment mark pattern on it; providing a substrate, and transferring the alignment mark pattern to the substrate surface using photolithography and etching processes to form alignment marks. It is understood that the alignment marks can be formed directly on the semiconductor substrate, or they can be formed on process layers such as insulating layers, epitaxial layers, or dielectric layers on the substrate. The etching process for forming the alignment marks 2 can be dry etching (e.g., plasma etching) or wet etching.

[0037] In particular, an application of alignment marks is also provided, which is specifically applied in a deep silicon etching process, including the following steps: placing alignment marks on a deep silicon etching process layer, and then exposing the deep silicon etching process layer as an alignment layer.

[0038] The common English terms or letters used in this invention for clarity of description are for illustrative purposes only and are not limiting interpretations or specific uses. They should not be used to limit the scope of protection of this invention based on their possible Chinese translations or specific letters.

[0039] It should also be noted that in this article, relational terms such as “first” and “second” are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

Claims

1. An alignment mark, characterized in that, The alignment mark is formed on the substrate and includes a multi-channel mark structure arranged in parallel with each other. The mark structure includes multiple discontinuous alignment blocks.

2. An alignment mark according to claim 1, characterized in that, The adjacent multiple marker structures are equidistantly distributed, and the multiple alignment blocks in each marker structure are either equidistantly arranged or non-equidistantly arranged.

3. An alignment mark according to claim 1, characterized in that, The alignment mark is a groove structure or a raised structure.

4. An alignment mark according to claim 2, characterized in that, A process layer is formed on the substrate; a functional structure is formed on the process layer; the process layer is any one of an insulating layer, an epitaxial layer, or a dielectric layer.

5. An alignment mark according to claim 4, characterized in that, The alignment marks are provided in at least one set, and the alignment marks are formed at at least one corner of the process layer or at least one corner of the functional structure.

6. An alignment mark according to claim 4, characterized in that, The spacing of the alignment blocks is determined according to the graphic density of the functional structure, so that the graphic density of the alignment marks is adapted to the graphic density of the functional structure.

7. An alignment mark according to claim 6, characterized in that, The alignment marks are formed on the deep silicon etching process layer, and the structural parameters of the alignment marks are determined by the pattern density of the functional structure of the deep silicon etching process layer.

8. A photomask, characterized in that, The mask includes alignment mark patterns for forming an alignment mark as described in any one of claims 1-7.

9. A method for preparing an alignment mark as described in any one of claims 1-7, characterized in that, include: A mask is provided, the mask having alignment mark patterns; A substrate is provided, and the alignment mark pattern is transferred to the surface of the substrate using photolithography and etching processes to form alignment marks.

10. A method for preparing an alignment mark according to claim 9, characterized in that, The etching process is either a dry etching process or a wet etching process.

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