Chip adapter plate and method of formation
By etching heat dissipation cavities and heat dissipation pillars in the chip adapter board, combined with the design of conductive vias, the problems of metal migration and thermal stress at high temperatures are solved, improving the thermal management and reliability of chip packaging.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HUBEI XINGCHEN TECH CO LTD
- Filing Date
- 2026-02-06
- Publication Date
- 2026-05-29
AI Technical Summary
Existing chip packaging structures suffer from interconnect failures due to metal atom migration under high-temperature conditions, and traditional heat dissipation capabilities are insufficient to cope with thermal stress issues in high-power scenarios, affecting system performance and reliability.
Design a chip adapter board by etching heat dissipation cavities and heat dissipation pillars inside the substrate and filling them with thermally conductive material, combined with conductive vias to improve heat management and conductivity, and optimize the heat distribution of the packaging structure.
It enhances the overall thermal integrity of the packaging structure, effectively conducts and manages the heat generated during chip operation, and improves the thermal management and long-term operational stability of the system.
Smart Images
Figure CN122121698A_ABST
Abstract
Description
Technical Field
[0001] This application relates to semiconductor technology, and more particularly to a chip adapter board and a method for forming it. Background Technology
[0002] In chip design, high-density capacitor placement is a critical aspect of signal-power co-design, directly impacting system performance and reliability. Simultaneously, the faster the temperature change rate, the greater the resulting thermal stress, which has a particularly pronounced impact on advanced packaging structures. Temperature is one of the core factors affecting chip reliability: high temperatures accelerate the migration of metal atoms. When the chip's operating temperature rises, the atomic migration rate in metal interconnects (especially copper interconnects) increases significantly, leading to defects such as voids or build-ups, ultimately potentially causing open-circuit or short-circuit failures. Summary of the Invention
[0003] This application provides a chip adapter board that improves the overall thermal integrity of the chip adapter board through heat dissipation pillars and conductive vias in the heat dissipation cavity, effectively conducts, disperses and manages the heat generated during chip operation, and optimizes heat dissipation performance.
[0004] The technical solution of this application embodiment is implemented as follows: In a first aspect, embodiments of this application provide a chip adapter board, the chip adapter board including a substrate and a first carrier wafer, wherein the substrate and the first carrier wafer are vacuum bonded; The adapter board is divided into a heat dissipation area and an interconnection area; A first heat dissipation cavity is formed by etching inside the substrate located in the heat dissipation area; The heat dissipation area also includes a plurality of heat dissipation pillars, each of which extends along a first direction, a portion of which is located in the first heat dissipation cavity, and another portion of which penetrates the first surface of the substrate and the first carrier wafer. The first surface of the substrate refers to the etched surface. The substrate and the first carrier wafer located in the interconnect region are penetrated by a plurality of conductive vias along a first direction, and the different conductive vias are isolated from each other. The heat dissipation column is filled with a heat-conducting material, and the conductive through hole is filled with a conductive material.
[0005] In some embodiments, the interface shape of the heat dissipation column includes one or more of the following: circular, square, and polygonal.
[0006] In some embodiments, the chip adapter board further includes a wiring layer, wherein the wiring layer, the substrate of the adapter board, and the first carrier wafer are arranged along a first direction; The wiring layer is penetrated by multiple second heat dissipation cavities, and the second heat dissipation cavities are connected to the first heat dissipation cavity; The conductive via extends to the wiring layer and is connected to the metal interconnect in the wiring layer; The first end of the heat dissipation pillar extends to the wiring layer, and the first end of the heat dissipation pillar is connected to the metal interconnect in the wiring layer; the first end refers to the end close to the first surface of the substrate.
[0007] In some embodiments, the chip adapter board also satisfies one or more of the following conditions: (1) The inner wall of the first heat dissipation cavity is filled with insulating material, and the interior of the second heat dissipation cavity is filled with insulating material; (2) The insulating material is boron nitride; (3) The inner wall of the heat dissipation column and the inner wall of the conductive through hole are oxidized to form a first oxide layer; (4) The thermally conductive material and the conductive material are made of metallic copper; (5) The etching depth of the heat dissipation pillar is less than the etching depth of the conductive via; (6) The etching depth of the first heat dissipation cavity is less than the etching depth of the conductive via.
[0008] Secondly, embodiments of this application provide a method for forming a chip adapter board, the method comprising: A semiconductor structure comprising a substrate and a first carrier wafer is provided, wherein a portion of the semiconductor structure is a heat dissipation region and another portion of the semiconductor structure is an interconnect region; Multiple first sub-heat dissipation cavities are formed by etching the interior of the substrate located in the heat dissipation area; The first surface of the substrate is vacuum bonded to the first carrier wafer; Multiple heat dissipation pillars are etched into the semiconductor structure between adjacent first sub-heat dissipation cavities; The semiconductor structure between adjacent first sub-heating cavities and between adjacent heat dissipation pillars is completely etched to form the first heat dissipation cavity; Multiple conductive vias are formed by etching the interior of the semiconductor structure located in the interconnect region; A thermally conductive material is deposited in the heat dissipation pillar, and a conductive material is deposited in the conductive via to form a chip adapter board.
[0009] In some embodiments, after vacuum bonding the first surface of the substrate to the first carrier wafer, the method further includes: The first carrier wafer is thinned, and a buffer layer is deposited on the thinned first carrier wafer; Multiple heat dissipation pillars are formed by etching along a first direction to a first preset depth on a semiconductor structure between adjacent first sub-heat dissipation cavities; Multiple conductive vias are formed by etching along a first direction to a second predetermined depth in the semiconductor structure of the interconnect region. Wherein, the first preset depth is less than the etching depth of the first sub-heat dissipation cavity along the first direction, and the second preset depth is greater than the etching depth of the first sub-heat dissipation cavity along the first direction.
[0010] In some embodiments, when both the thermally conductive material and the conductive material are target materials, the step of depositing the thermally conductive material into the heat dissipation pillar and depositing the conductive material into the conductive via specifically includes: The substrate material of the inner wall of the heat dissipation column and the inner wall of the conductive via is partially oxidized to form a first oxide layer. The target material is deposited into the heat dissipation pillar and the conductive via; A wiring layer is formed above the buffer layer; wherein the wiring layer includes multiple metal interconnects; The first end of the heat dissipation pillar extends to the wiring layer and is connected to the metal interconnect; the conductive via extends to the wiring layer and is connected to the metal interconnect; the first end refers to the end close to the first surface of the substrate.
[0011] In some embodiments, the complete etching of the substrate between adjacent first sub-heat dissipation cavities and the substrate between adjacent heat dissipation pillars to form the first heat dissipation cavity specifically includes: The wiring layer is etched to form a plurality of second heat dissipation cavities, the second heat dissipation cavities penetrating the wiring layer and connected to a portion of the first sub-heat dissipation cavity; Etching solution is dripped into the second heat dissipation cavity to completely etch the substrate between the first sub-heat dissipation cavities and the substrate between the heat dissipation pillars, forming the first heat dissipation cavity.
[0012] In some embodiments, the inner wall of the first heat dissipation cavity and the interior of the second heat dissipation cavity are filled with insulating material to form a dielectric layer; The second surface of the substrate is etched until the metal filling the conductive via is exposed; the second surface is opposite to the first surface. A second oxide layer is formed on the second surface of the substrate, and a UBM structure is formed by exposing the conductive via to the portion of the second oxide layer.
[0013] Thirdly, the application provides an electronic device that includes at least the chip adapter board as described in the first aspect.
[0014] This application provides a chip adapter board, which includes a substrate and a first carrier wafer, and the substrate and the first carrier wafer are vacuum bonded. The adapter board is divided into a heat dissipation area and an interconnection area. A first heat dissipation cavity is formed by etching inside the substrate in the heat dissipation area. The heat dissipation area also includes multiple heat dissipation pillars, each extending along a first direction. A portion of each heat dissipation pillar is located in the first heat dissipation cavity, and the other portion of the heat dissipation pillar penetrates the first surface of the substrate and the first carrier wafer. The substrate and the first carrier wafer in the interconnection area are penetrated by multiple conductive vias along the first direction, and different conductive vias are isolated from each other. The heat dissipation pillars are filled with thermally conductive material, and the conductive vias are filled with conductive material. In this way, by etching the first heat dissipation cavity in the heat dissipation area of the chip adapter board, and etching the heat dissipation pillars and conductive vias in the heat dissipation area and the interconnection area respectively, a chip adapter board with high heat dissipation efficiency is provided. The heat dissipation pillars and conductive vias in the heat dissipation cavity improve the overall thermal integrity of the chip adapter board, effectively conduct, disperse, and manage the heat generated during chip operation, and optimize heat dissipation performance. Attached Figure Description
[0015] Figure 1 This is a schematic diagram of the structure of the first type of chip adapter board provided in the embodiments of this application; Figure 2 This is a schematic diagram of the structure of the second type of chip adapter board provided in the embodiments of this application; Figure 3 This is a schematic flowchart of a chip adapter board forming method provided in an embodiment of this application; Figure 4 This is a schematic diagram of the first type of mask etching provided in the embodiments of this application; Figure 5 This is a schematic diagram of the second type of mask etching provided in the embodiments of this application; Figure 6 This is a schematic diagram of the first step of forming a chip adapter board according to an embodiment of this application; Figure 7 This is a schematic diagram of the second step of forming a chip adapter board according to an embodiment of this application; Figure 8 This is a schematic diagram of the third step in the formation of a chip adapter board provided in an embodiment of this application; Figure 9 This is a schematic diagram of the fourth step in the formation of a chip adapter board provided in an embodiment of this application; Figure 10 This is a schematic diagram of the fifth step in the formation of a chip adapter board provided in an embodiment of this application; Figure 11 This is a schematic diagram of the sixth step in the formation of a chip adapter board provided in an embodiment of this application; Figure 12 This is a schematic diagram of an electronic device structure provided in an embodiment of this application.
[0016] It should be noted that the terms "first" and "second" mentioned above are only used to distinguish between different options and do not represent the degree of superiority or inferiority of the options or their priority in the implementation process. Detailed Implementation
[0017] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0018] It is understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the disclosure. It should also be noted that, for ease of description, only the parts relevant to the disclosure are shown in the accompanying drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to limit the disclosure. In the following description, references to "some embodiments" describe a subset of all possible embodiments; however, it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict. It should be noted that the terms "first, second, third, fourth" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third, fourth" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.
[0019] In existing chip packaging structures, high temperatures not only accelerate the migration of metal atoms, leading to voids or accumulations in interconnects and causing open or short circuit faults, but also generate significant thermal stress due to rapid temperature changes, affecting the stability and long-term reliability of the packaging structure. Especially in high-power scenarios such as artificial intelligence and high-performance computing, the heat dissipation capabilities of traditional packaging are insufficient to cope with the rapidly increasing power density, becoming a bottleneck restricting system performance and reliability.
[0020] In contrast, advanced packaging structures incorporating silicon interposers offer significant advantages in terms of increased integration density, shorter interconnect lengths, improved signal integrity, and power consumption control through high-density interconnects and multi-chip integration. However, this structure still suffers from interlayer heat dissipation issues, especially in 2.5D / 3D stacked designs, where heat accumulation can exacerbate localized temperature rises and thermal stress, impacting overall thermal management and reliability. Therefore, this application proposes a chip interposer designed to enhance interlayer heat conduction and optimize internal temperature distribution within the package, thereby improving the overall thermal integrity and long-term operational stability of advanced packaging systems.
[0021] The embodiments of this application will now be described in detail with reference to the accompanying drawings.
[0022] In some embodiments of this application, see Figure 1 This illustrates a schematic diagram of the structure of the first type of chip adapter board 10 provided in an embodiment of this application. Figure 1 As shown, the chip adapter board 10 includes a substrate 110 and a first carrier wafer 130, and the substrate 110 and the first carrier wafer 130 are vacuum bonded; the adapter board is divided into a heat dissipation area and an interconnection area; a first heat dissipation cavity 111 is formed by etching inside the substrate 110 located in the heat dissipation area; the heat dissipation area also includes a plurality of heat dissipation pillars 112, each heat dissipation pillar 112 extending along a first direction, a part of each heat dissipation pillar 112 being located in the first heat dissipation cavity 111, and another part of the heat dissipation pillar 112 penetrating the first surface of the substrate 110 and the first carrier wafer 130, the first surface of the substrate referring to the etched surface; the substrate 110 and the first carrier wafer 130 located in the interconnection area are penetrated by a plurality of conductive vias 113 along the first direction, and different conductive vias 113 are isolated from each other; wherein, the heat dissipation pillars 112 are filled with thermally conductive material, and the conductive vias 113 are filled with conductive material.
[0023] Here, a first heat dissipation cavity 111 is deeply etched into the substrate 110 located in the heat dissipation area of the chip adapter 10. Essentially, this etching creates a region with extremely high local thermal resistance within the substrate 110, preventing the heat generated by the chip from easily diffusing laterally into the surrounding substrate. The thermally conductive material filling the heat dissipation pillar 112 results in extremely low thermal resistance. Part of the heat dissipation pillar 112 is located within the first heat dissipation cavity 111, while the other part penetrates the first surface of the substrate 110, forming a vertical channel with the lowest thermal resistance. Due to the high thermal resistance of the first heat dissipation cavity 111, it directs the heat generated in the chip to the heat dissipation pillar 112 with its extremely low thermal resistance, allowing the heat dissipation pillar 112 to conduct the heat generated in the chip. The high thermal resistance of the first heat dissipation cavity 111 creates a significant temperature difference between the chip heat source and the heat dissipation pillar 112, enhancing the thermal force driving heat towards the heat dissipation pillar 112 and improving its heat dissipation efficiency.
[0024] It should be noted that the interface shape of the heat sink 112 includes one or more of the following: circular, square and polygonal, and this embodiment does not limit it.
[0025] It should be noted that the etching depth of the heat sink 112 is less than the etching depth of the conductive via 113, and the etching depth of the first heat sink cavity 111 is less than the etching depth of the conductive via 113.
[0026] Here, the conductive via 113 penetrates the substrate 110 of the interconnect region, and different conductive vias 113 are isolated by the substrate. The conductive material filled in the conductive via 113 can transmit the signals generated by the chip.
[0027] In some embodiments, both the thermally conductive material filling the heat sink 112 and the conductive material filling the conductive via 113 are made of copper. Copper can be used for both thermal and electrical conduction. Therefore, the conductive via 113 can also assist in heat dissipation, transferring the heat generated by the chip.
[0028] It should be noted that copper contains a large number of freely moving electrons, which are responsible for both the transfer of electric charge and heat. Therefore, copper can conduct both heat and electricity.
[0029] It should be noted that in other embodiments, the heat-conducting material can also be gold (Au), silver (Ag), or aluminum (Al); the conductive material can also be gold (Au), silver (Ag), or aluminum (Al). Gold (Au), silver (Ag), and aluminum (Al) can all be used for heat conduction and electrical conduction. This embodiment does not limit the heat-conducting and conductive materials.
[0030] It should be noted that in this embodiment, the substrate 110 of the chip adapter board 10 is a silicon substrate. In other embodiments, it can be other types of substrates, and this embodiment does not limit it.
[0031] It should be further noted that the thermal conductivity of the silicon substrate is about 150 W / mK, while the thermal conductivity of air is only about 0.026 W / mK. Therefore, the thermal resistance of the first heat dissipation cavity formed by etching in the substrate is extremely high.
[0032] For some embodiments of this application, please refer to Figure 2 This illustrates a schematic diagram of the structure of the second type of chip adapter board 10 provided in an embodiment of this application. Figure 2As shown, the chip adapter board 10 also includes a wiring layer 120, and the wiring layer 120, the substrate 110 of the adapter board, and the first carrier wafer 130 are arranged along a first direction; the wiring layer 120 is penetrated by a plurality of second heat dissipation cavities 121, and the second heat dissipation cavities 121 are connected to the first heat dissipation cavity 111; the conductive via 113 extends to the wiring layer 120 and is connected to the metal interconnect in the wiring layer 120; the first end of the heat dissipation pillar 112 extends to the wiring layer 120 and is connected to the metal interconnect in the wiring layer 120; the first end refers to the end close to the first surface of the substrate 110.
[0033] In this embodiment, the wiring layer 120 includes multiple metal interconnect layers. Several metal interconnect lines in the wiring layer 120 are distributed in different metal interconnect layers. Each metal interconnect layer is isolated by a dielectric (such as silicon dioxide or a material with a lower dielectric constant) to prevent short circuits and signal crosstalk between different metal interconnect layers.
[0034] It should be noted that the material of the metal interconnect is copper, but other materials can be used in other embodiments, and this embodiment does not limit it.
[0035] It should be noted that this embodiment does not limit the number or location distribution of metal interconnects.
[0036] In some embodiments, please continue to see Figure 2 The substrate material of the inner wall of the heat dissipation column 112 and the inner wall of the conductive through hole 113 is partially oxidized to form a first oxide layer 114.
[0037] It should be noted that the substrates of the inner walls of the heat dissipation column 112 and the conductive via 113 are oxidized by thermal oxidation or thin film deposition, thereby forming a uniform first oxide layer 114 on the inner walls of the heat dissipation column 112 and the conductive via 113. The first oxide layer 114 plays a supporting role in the filling process of the heat dissipation column 112 and the conductive via 113, and the first oxide layer 114 can further optimize the heat dissipation efficiency of the heat dissipation column 112.
[0038] In some embodiments, please continue to see Figure 2 The inner wall of the first heat dissipation cavity 111 and the interior of the second heat dissipation cavity 121 are filled with insulating material to form a thin dielectric layer 115, which can prevent electrical short circuits caused by contact between the heat dissipation column 112 and the substrate 110, block electromagnetic interference or electromagnetic coupling that may be introduced by the heat dissipation column 112, and buffer the substrate cracking caused by the huge thermal stress generated.
[0039] In this embodiment, boron nitride high thermal conductivity film is selected as the insulating material to balance the requirements of insulation and high heat dissipation performance. In other embodiments where heat dissipation requirements are not high, conventional dielectric films such as silicon oxide and silicon nitride can also be used as insulating materials.
[0040] Here, the wiring layer 120 is penetrated by multiple second heat dissipation cavities 121, and the second heat dissipation cavities 121 pass through the first surface of the substrate 110 and are connected to the first heat dissipation cavity 111. The second heat dissipation cavity 121 can assist in the transfer of a small portion of heat.
[0041] Here, both the heat sink 112 and the conductive via 113 are essentially through-silicon vias (TSVs). The conductive via 113 extends to the wiring layer 120 and is perpendicularly electrically connected to the metal interconnect layer in the wiring layer 120, transmitting electrical signals inside the chip. Simultaneously, due to the good thermal conductivity of the conductive material filling the conductive via 113, it also conducts some heat. The first end of the heat sink 112 is connected to the metal interconnect line of the wiring layer 120, and the other end is located in the first heat dissipation cavity 111. The heat generated by the chip is transferred to the first heat dissipation cavity 111 via the substrate 110. The first heat dissipation cavity 111 drives the heat towards the heat sink 112, and the heat is vertically transferred via the heat sink 112.
[0042] For some embodiments of this application, please refer to Figure 3 This illustrates a flowchart of a method for forming a chip adapter board 10 according to an embodiment of this application. Figure 3 As shown, the method includes: S11: Provides a semiconductor structure including a substrate and a first carrier wafer, a portion of the semiconductor structure being a heat dissipation region and another portion of the semiconductor structure being an interconnect region.
[0043] It should be noted that the semiconductor structure can be a silicon interposer or a glass interposer.
[0044] S12: The interior of the substrate located in the heat dissipation area is etched to form multiple first sub-heat dissipation cavities.
[0045] Please see here. Figure 4 The substrate located in the heat dissipation area is etched based on the first mask to generate a continuous first sub-heat dissipation cavity; wherein, the first mask includes a plurality of first preset patterns, the substrate of the heat dissipation area not covered by the first preset patterns is etched to form the first sub-heat dissipation cavity, and the area covered by the first preset patterns forms a reserved area.
[0046] S13: Vacuum bond the first surface of the substrate to the first carrier wafer.
[0047] S14: Multiple heat dissipation pillars are etched in the semiconductor structure between adjacent first sub-heat dissipation cavities.
[0048] Please see here. Figure 5 The semiconductor structure located in the reserved area is etched based on the second mask to generate continuous heat dissipation pillars; wherein, the second mask includes multiple second preset patterns, and the semiconductor structure in the reserved area not covered by the second preset patterns is etched to form heat dissipation pillars.
[0049] It should be noted that the second preset pattern in the second mask can be a circle, a square, or a polygon.
[0050] S15: Completely etch the substrate between adjacent first sub-heating cavities and the semiconductor structure between adjacent heat dissipation pillars to form the first heat dissipation cavity.
[0051] Here, wet etching is used to remove the substrate material between the first sub-heat dissipation cavities and between the heat dissipation pillars, which can ensure efficient heat exchange of the fluid in the heat dissipation pillars and microchannels; wherein, multiple first sub-heat dissipation cavities are fused and connected to form the first heat dissipation cavity.
[0052] S16: Multiple conductive vias are formed by etching the interior of the semiconductor structure located in the interconnect region.
[0053] Here, the semiconductor structure located in the interconnect region is etched based on the third mask to generate continuous conductive vias; wherein, the third mask includes multiple third preset patterns, and the semiconductor structure in the interconnect region not covered by the third preset patterns is etched to form conductive vias.
[0054] It should be noted that in this embodiment, a positive mask combined with a positive etching (positive photoresist) process is used to etch the first sub-heat dissipation cavity, heat dissipation pillar and conductive via on the semiconductor structure. In other embodiments, a negative mask combined with a negative etching (reverse photoresist) process can also be used to etch the first sub-heat dissipation cavity, heat dissipation pillar and conductive via on the semiconductor structure.
[0055] It should be noted that the size of the first heat dissipation cavity is larger than the size of the conductive through hole, and the size of the conductive through hole is larger than the size of the heat dissipation column.
[0056] S17: Deposit thermally conductive material into the heat sink pillars and deposit conductive material into the conductive vias to form a chip adapter board.
[0057] It should be noted that in this embodiment, both the thermally conductive and electrically conductive materials are made of copper. In other embodiments, the thermally conductive and electrically conductive materials may also be made of gold, silver, or aluminum.
[0058] Here, the chip adapter board dissipates the heat generated by the chip through the heat dissipation pillars in the heat dissipation area, and transmits the electrical signals generated by the chip through the conductive vias in the interconnect area.
[0059] For some embodiments of this application, please refer to Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 This illustrates a step-by-step formation diagram of a chip adapter board 10 provided in an embodiment of this application. For example... Figure 6 As shown, a semiconductor structure 30 including a substrate 110 and a first carrier wafer 130 is provided. A portion of the semiconductor structure 30 belongs to a heat dissipation region, and another portion of the semiconductor structure 30 belongs to an interconnect region. The specific steps in forming the chip adapter board include: S101: Multiple first sub-heat dissipation cavities 111-1 are formed by etching the interior of the substrate 110 located in the heat dissipation area. Please refer to [link to relevant documentation]. Figure 6 (a) and (b) in the example.
[0060] S102: Vacuum bond the first surface of the substrate 110 to the first carrier wafer 130. (See below) Figure 6 (c) in the middle.
[0061] It should be noted that the first surface of the substrate 110 of the semiconductor structure refers to the etched surface.
[0062] S103: Thin the first carrier wafer 130 and deposit a buffer layer 116 on the thinned first carrier wafer 130. (See below) Figure 7 (d) and (e) in the text.
[0063] S104: By etching along a first direction to a first preset depth on the semiconductor structure between adjacent first sub-heat dissipation cavities 111-1, a plurality of heat dissipation pillars 112 are formed. Please refer to [link to relevant documentation]. Figure 8 (f) in the middle.
[0064] S105: By etching along a first direction to a second preset depth in the semiconductor structure of the interconnect region, a plurality of conductive vias 113 are formed. Please refer to [link to relevant documentation]. Figure 8 (f) in the middle.
[0065] It should be noted that the first preset depth is less than the etching depth of the first sub-heat dissipation cavity 111-1 along the first direction, and the second preset depth is greater than the etching depth of the first sub-heat dissipation cavity 111-1 along the first direction.
[0066] S106: The substrate material of the inner wall of the heat dissipation pillar 112 and the inner wall of the conductive via 113 is partially oxidized to form a first oxide layer 114. Please refer to [link to relevant documentation]. Figure 8 (g) in the middle.
[0067] S107: Deposit thermally conductive material into the heat dissipation pillar 112, and deposit conductive material into the conductive via 113. Please refer to [link to relevant documentation]. Figure 8 (h) in the middle.
[0068] S108: A wiring layer 120 is formed above the buffer layer 116; wherein the wiring layer 120 includes multiple metal interconnects; the first end of the heat sink 112 extends to the wiring layer 120 and is connected to the metal interconnects; the conductive via 113 extends to the wiring layer 120 and is connected to the metal interconnects; the first end of the heat sink 112 refers to the end near the first surface of the substrate, see [link to relevant documentation]. Figure 9 (i) in the middle.
[0069] S109: The wiring layer 120 is etched to form multiple second heat dissipation cavities 121. The second heat dissipation cavities 121 penetrate the wiring layer 120 and are connected to a portion of the first sub-heat dissipation cavities 111-1. Please refer to [link to relevant documentation]. Figure 9 (j) in the middle.
[0070] S110: Etching solution is dripped into the second heat dissipation cavity 121 to completely etch the substrate between the first sub-heat dissipation cavities 111-1 and the substrate 110 between the heat dissipation pillars 112, forming the first heat dissipation cavity 111. Please refer to [link to relevant documentation]. Figure 10 (k) in the middle.
[0071] S111: The inner wall of the first heat dissipation cavity 111 and the interior of the second heat dissipation cavity 121 are filled with insulating material to form a dielectric layer 115. Please refer to [link to relevant documentation]. Figure 10 (l) in the middle.
[0072] S112: A second carrier wafer 140 is provided, and the semiconductor structure 30 is bonded to the second carrier wafer 140. The second carrier wafer 140 is located on the side of the wiring layer 120 away from the substrate 110. Please refer to [link to relevant documentation]. Figure 11 (m) in the middle.
[0073] S113: Etch the second surface of substrate 110 until the metal filling the conductive via 113 is exposed. See [link to documentation]. Figure 11 (n) in the middle.
[0074] It should be noted that the second surface is opposite to the first surface.
[0075] S114: A second oxide layer 117 is formed on the second surface of the substrate 110, and a UBM structure 131 is formed on the portion of the conductive via 113 exposed to the second oxide layer 117. Please continue to see Figure 11 (n) in the middle.
[0076] Here, a chip adapter board 10 is formed on the semiconductor structure 30 according to the steps described above.
[0077] Specifically, the first surface of the semiconductor structure 30 is vacuum bonded to the first carrier wafer 130, and the bonded first carrier wafer 130 is thinned to the target thickness, and a buffer layer 116 is deposited on the thinned first carrier wafer 130.
[0078] Here, vacuum bonding is performed between the semiconductor structure 30 and the first carrier wafer 130 to maintain the stability of the first sub-heat sink 111-1 after bonding. The target thickness of the first carrier wafer 130 after bonding is 1-20 μm.
[0079] In some embodiments, the semiconductor structure 30 can be a silicon wafer, and the first carrier wafer 130 can also be a silicon wafer. When the two are bonded, the silicon surface of the semiconductor structure 30 comes into contact with the silicon surface of the first carrier wafer 130, thereby forming a silicon-silicon bonding interface.
[0080] In other embodiments, the semiconductor structure 30 can be a silicon wafer, and the first carrier wafer 130 can also be a silicon wafer, but an oxide layer (such as silicon dioxide) is prepared on the surface of the first carrier wafer 130. When the two are bonded, the silicon surface of the semiconductor structure 30 comes into contact with the oxide surface of the first carrier wafer 130, thereby forming a silicon-oxide bonding interface.
[0081] In some other embodiments, the semiconductor structure 30 is a silicon wafer with an oxide layer on its surface, and the first carrier wafer 130 is also a silicon wafer with an oxide layer on its surface. When the two are bonded, the two oxide surfaces come into contact with each other, thereby forming an oxide-oxide bonding interface.
[0082] Here, the silicon dioxide layer in the bonding interface serves as a protective layer when forming the heat dissipation pillar 112 in subsequent processes.
[0083] It should be noted that the larger the size of the first sub-heat sink 111-1, the greater the stress it experiences during bonding, leading to deformation of the first sub-heat sink 111-1. Therefore, the size of the first sub-heat sink 111-1 should not be set too large; instead, a micron-level heat dissipation microchannel should be used. Simultaneously, the buffer layer 116 deposited on the first carrier wafer 130 can buffer thermal stress.
[0084] At this point, the semiconductor structure 30, after bonding and buffer layer deposition, has a micron-level first sub-heat dissipation cavity reserved inside. This first sub-heat dissipation cavity 111-1 can significantly enhance heat conduction and diffusion efficiency. The processed semiconductor structure is the same as that of a conventional silicon substrate.
[0085] Specifically, a plurality of heat dissipation pillars 112 are etched along a first direction on the substrate 110 between adjacent first sub-heat dissipation cavities 111-1; a plurality of conductive vias 113 are etched along the first direction in the substrate 110 of the interconnect region, the size of the conductive vias 113 is larger than the size of the heat dissipation pillars 112, and the spacing between the heat dissipation pillars 112 between adjacent first sub-heat dissipation cavities 111-1 is small, while the spacing between the heat dissipation pillars 112 between non-adjacent first sub-heat dissipation cavities 111-1 is large; the etching depth of the heat dissipation pillars 112 along the first direction is less than the etching depth of the conductive vias 113 along the first direction.
[0086] Specifically, the inner walls of the heat dissipation pillars 112 and the inner walls of the thermally conductive vias 113 are oxidized by thermal oxidation or thin film deposition to form a first oxide layer 114, and then filled with metallic copper into the oxidized inner walls of the heat dissipation pillars 112 and the thermally conductive vias 113. The substrate 110 between the multiple heat dissipation pillars 112 formed on the substrate 110 between adjacent first sub-heat dissipation cavities 111-1 is partially oxidized.
[0087] It should be noted that filling the heat sink 112 with copper can significantly reduce its internal thermal resistance; while filling the conductive via 113 with copper can effectively reduce its internal resistance. Copper can be used for both thermal and electrical conduction.
[0088] Furthermore, a wiring layer 120 is formed above the first oxide layer 114 by a successive metal thin film deposition process. Each deposition of a metal thin film (e.g., copper, aluminum, etc.) generates a corresponding metal interconnect, ultimately forming a complete wiring structure containing multiple metal interconnects. The heat dissipation pillars 112 and conductive vias 113 are respectively connected to the metal interconnects in the wiring layer 120. The internally filled copper metal and the metal interconnects dissipate heat generated inside the chip and transmit electrical signals inside the chip.
[0089] Here, the first oxide layer 114 can prevent metal atoms in the metal interconnect layer and the metal atoms filled in the heat dissipation pillars 112 and conductive vias 113 from diffusing into the substrate in the semiconductor structure.
[0090] Furthermore, the second heat dissipation cavity 121, which penetrates the wiring layer 120, is connected to a portion of the first sub-heat dissipation cavity 111-1. To ensure efficient heat exchange between the heat dissipation pillars 112 and the fluid in the microchannels, etching solution is poured into the end of the second heat dissipation cavity 121 away from the first heat dissipation cavity. Using a wet etching process and by controlling the etching time, the substrate between adjacent first sub-heat dissipation cavities 111-1 and the substrate between heat dissipation pillars 112 are completely etched. At this time, multiple first sub-heat dissipation cavities 111-1 are fused and connected to form the first heat dissipation cavity 111.
[0091] Here, a boron nitride high thermal conductivity thin film is used as an insulating material to fill and seal the second heat dissipation cavity, and the inner wall of the first heat dissipation cavity is also covered with an insulating material to form a dielectric layer 115.
[0092] Furthermore, the side of the semiconductor structure 30 located in the wiring layer 120 away from the substrate 110 is bonded to the second carrier wafer 140. The second carrier wafer 140 can be a silicon wafer or a glass wafer, and it is used to provide mechanical support and protection for the semiconductor structure.
[0093] The second surface of the semiconductor structure 30 is etched until the metal filling the conductive via 113 is exposed. A second oxide layer 117 is formed on the second surface of the semiconductor structure 30. The second oxide layer 117 does not cover the conductive via 113. The portion of the conductive via 113 exposed to the second oxide layer 117 forms a UBM structure 131. The UBM structure 131 is in contact with the metal filling the conductive via 113.
[0094] It should be noted that the UBM structure 131 is composed of multiple layers of thin metal stacks, with a total thickness on the micrometer scale. Each of the stacked thin metal layers has a specific function. Since the top surface of the semiconductor structure 30 is a silicon substrate, and the copper interconnects are buried underneath, the UBM structure 131 can adopt an aluminum / nickel-vanadium / copper metal stack structure. The aluminum layer acts as an adhesion layer, directly adhering to the top surface of the semiconductor structure 30 or adhering to the second oxide layer 117. The nickel-vanadium alloy layer acts as a barrier layer, preventing the diffusion of copper atoms inside the conductive via 113. The copper layer acts as a conductive seed layer for electroplating. Subsequently, through photolithography and electroplating processes, copper pillars of a certain thickness are formed on the surface of the copper layer. Solder caps are formed at the top of the copper pillars to form microbumps, which are then connected to external chips.
[0095] Here, the second oxide layer 117 covers the second surface of the semiconductor structure 30 to prevent electrical short circuits in subsequent processes; by not covering the top of the conductive via 113, the metal region for fabricating the UBM structure is precisely exposed, enhancing the adhesion strength between the UBM structure and the substrate. The UBM structure 131 can be connected to the chip, transmitting chip signals and assisting in heat dissipation.
[0096] In summary, the chip adapter provided in this application provides a semiconductor structure including a heat dissipation area and an interconnection area. Multiple first sub-heat dissipation cavities are formed by etching the interior of the substrate located in the heat dissipation area. The first surface of the substrate of the semiconductor structure is vacuum-bonded to a first carrier wafer. The first carrier wafer is thinned, and a buffer layer is deposited on the thinned first carrier wafer. Multiple heat dissipation pillars are formed by etching on the substrate between adjacent first sub-heat dissipation cavities. A first oxide layer is formed on the inner wall of the heat dissipation pillars and the inner wall of the conductive vias. A thermally conductive material is deposited in the heat dissipation pillars, and a conductive material is deposited in the conductive vias. A wiring layer is formed above the first oxide layer, and the wiring layer includes multiple metal interconnects. The conductive vias extend... The heat sink extends to the wiring layer and connects to the metal interconnect. The heat sink is located in the first sub-heat sink cavity and is not connected to the metal interconnect. The wiring layer is etched to form multiple second heat sink cavities. The second heat sink cavities penetrate the wiring layer and connect to a portion of the first sub-heat sink cavity. Etching solution is dripped into the second heat sink cavity to completely etch the substrate between the first sub-heat sink cavities and the substrate between the heat sinks to form the first heat sink cavity. The inner wall of the first heat sink cavity and the interior of the second heat sink cavity are filled with insulating material to form a dielectric layer. The semiconductor structure is bonded to the second carrier wafer. The second surface of the substrate is etched until the metal filled inside the conductive via is exposed. A second oxide layer is formed on the second surface of the substrate. The portion of the conductive via exposed to the second oxide layer forms a UBM structure.
[0097] In this way, when the silicon interposer is connected to an external chip through the UBM structure, the heat generated by the chip is transferred to the first heat dissipation cavity through the substrate. The first heat dissipation cavity drives the heat to the heat dissipation pillar, and the heat is vertically transferred to the second carrier wafer through the heat dissipation pillar, and the heat is diffused to the outside. At the same time, the electrical signal generated by the chip is vertically transferred through the conductive via. Since the conductive material filled in the conductive via has good thermal conductivity, the conductive via will also conduct some of the heat.
[0098] Therefore, this application provides a chip adapter board with high heat dissipation efficiency. The overall thermal integrity of the chip adapter board is improved by the first heat dissipation cavity, heat dissipation pillar and conductive through hole, which effectively conducts, disperses and manages the heat generated when the chip is working and optimizes the heat dissipation performance.
[0099] In some embodiments of this application, see Figure 12 This illustrates a structural schematic diagram of the electronic device 40 provided in an embodiment of this application. For example... Figure 12 As shown, the electronic device 40 includes at least the chip adapter board 10 described in the foregoing embodiments.
[0100] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure. It should be noted that in this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.
[0101] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.
[0102] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.
[0103] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.
[0104] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.
[0105] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.
Claims
1. A chip adapter board, characterized in that, The chip adapter board includes a substrate and a first carrier wafer, and the substrate and the first carrier wafer are vacuum bonded. The adapter board is divided into a heat dissipation area and an interconnection area; A first heat dissipation cavity is formed by etching inside the substrate located in the heat dissipation area; The heat dissipation area also includes a plurality of heat dissipation pillars, each of which extends along a first direction, a portion of which is located in the first heat dissipation cavity, and another portion of which penetrates the first surface of the substrate and the first carrier wafer. The first surface of the substrate refers to the etched surface. The substrate and the first carrier wafer located in the interconnect region are penetrated by a plurality of conductive vias along a first direction, and the different conductive vias are isolated from each other. The heat dissipation column is filled with a heat-conducting material, and the conductive through hole is filled with a conductive material.
2. The chip adapter board according to claim 1, characterized in that, The interface shape of the heat dissipation column includes one or more of the following: circular, square, and polygonal.
3. The chip adapter board according to claim 1, characterized in that, The chip adapter board further includes a wiring layer, and the wiring layer, the substrate of the adapter board, and the first carrier wafer are arranged along a first direction; The wiring layer is penetrated by multiple second heat dissipation cavities, and the second heat dissipation cavities are connected to the first heat dissipation cavity; The conductive via extends to the wiring layer and is connected to the metal interconnect in the wiring layer; The first end of the heat dissipation pillar extends to the wiring layer, and the first end of the heat dissipation pillar is connected to the metal interconnect in the wiring layer; the first end refers to the end close to the first surface of the substrate.
4. The chip adapter board according to claim 3, characterized in that, The chip adapter board also meets one or more of the following conditions: (1) The inner wall of the first heat dissipation cavity is filled with insulating material, and the interior of the second heat dissipation cavity is filled with insulating material; (2) The insulating material is boron nitride; (3) The inner wall of the heat dissipation column and the inner wall of the conductive through hole are oxidized to form a first oxide layer; (4) The thermally conductive material and the conductive material are made of metallic copper; (5) The etching depth of the heat dissipation pillar is less than the etching depth of the conductive via; (6) The etching depth of the first heat dissipation cavity is less than the etching depth of the conductive via.
5. A method for forming a chip adapter board, characterized in that, The method includes: A semiconductor structure comprising a substrate and a first carrier wafer is provided, wherein a portion of the semiconductor structure is a heat dissipation region and another portion of the semiconductor structure is an interconnect region; Multiple first sub-heat dissipation cavities are formed by etching the interior of the substrate located in the heat dissipation area; The first surface of the substrate is vacuum bonded to the first carrier wafer; Multiple heat dissipation pillars are etched into the semiconductor structure between adjacent first sub-heat dissipation cavities; The semiconductor structure between adjacent first sub-heating cavities and between adjacent heat dissipation pillars is completely etched to form the first heat dissipation cavity; Multiple conductive vias are formed by etching the interior of the semiconductor structure located in the interconnect region; A thermally conductive material is deposited in the heat dissipation pillar, and a conductive material is deposited in the conductive via to form a chip adapter board.
6. The method according to claim 5, characterized in that, After vacuum bonding the first surface of the substrate to the first carrier wafer, the method further includes: The first carrier wafer is thinned, and a buffer layer is deposited on the thinned first carrier wafer; Multiple heat dissipation pillars are formed by etching along a first direction to a first preset depth on a semiconductor structure between adjacent first sub-heat dissipation cavities; Multiple conductive vias are formed by etching along a first direction to a second predetermined depth in the semiconductor structure of the interconnect region. Wherein, the first preset depth is less than the etching depth of the first sub-heat dissipation cavity along the first direction, and the second preset depth is greater than the etching depth of the first sub-heat dissipation cavity along the first direction.
7. The method according to claim 5, characterized in that, When both the thermally conductive material and the conductive material are target materials, the step of depositing the thermally conductive material into the heat dissipation pillar and depositing the conductive material into the conductive via specifically includes: The substrate material of the inner wall of the heat dissipation column and the inner wall of the conductive via is partially oxidized to form a first oxide layer. The target material is deposited into the heat dissipation pillar and the conductive via; A wiring layer is formed above the buffer layer; wherein the wiring layer includes multiple metal interconnects; The first end of the heat dissipation pillar extends to the wiring layer and is connected to the metal interconnect; the conductive via extends to the wiring layer and is connected to the metal interconnect; the first end refers to the end close to the first surface of the substrate.
8. The method according to claim 7, characterized in that, The process of completely etching the substrate between adjacent first sub-heat dissipation cavities and the substrate between adjacent heat dissipation pillars to form the first heat dissipation cavity specifically includes: The wiring layer is etched to form a plurality of second heat dissipation cavities, the second heat dissipation cavities penetrating the wiring layer and connected to a portion of the first sub-heat dissipation cavity; Etching solution is dripped into the second heat dissipation cavity to completely etch the substrate between the first sub-heat dissipation cavities and the substrate between the heat dissipation pillars, forming the first heat dissipation cavity.
9. The method according to claim 5, characterized in that, The method further includes: The inner wall of the first heat dissipation cavity and the interior of the second heat dissipation cavity are filled with insulating material to form a dielectric layer; The second surface of the substrate is etched until the metal filling the conductive via is exposed; the second surface is opposite to the first surface. A second oxide layer is formed on the second surface of the substrate, and a UBM structure is formed by exposing the conductive via to the portion of the second oxide layer.
10. An electronic device, characterized in that... Includes the chip adapter board as described in any one of claims 1 to 4.