Chip adapter plate and method of formation

Abstract

The application provides a chip adapter plate, which comprises a substrate and a first carrier wafer, and the substrate and the first carrier wafer are vacuum bonded; the adapter plate is divided into a heat dissipation area and an interconnection area; the substrate and the first carrier wafer of the chip adapter plate located in the heat dissipation area are penetrated by a plurality of heat-conducting through holes, heat dissipation microchannels are distributed between different heat-conducting through holes, and the heat-conducting through holes are filled with heat-conducting materials; the substrate and the first carrier wafer of the chip adapter plate located in the interconnection area are penetrated by a plurality of conductive through holes, different conductive through holes are isolated from each other, and the conductive through holes are filled with conductive materials. In this way, by etching heat dissipation microchannels in the heat dissipation area of the chip adapter plate, and etching heat-conducting through holes and conductive through holes in the heat dissipation area and the interconnection area respectively, a chip adapter plate with high heat dissipation efficiency is provided, the overall thermal integrity of the chip adapter plate is improved through the heat dissipation microchannels and the through holes, the heat generated during the operation of the chip is effectively conducted, dispersed and managed, and the heat dissipation performance is optimized.

Description

Technical Field

[0001] This application relates to semiconductor technology, and more particularly to a chip adapter board and a method for forming it. Background Technology

[0002] In chip design, high-density capacitor placement is a critical aspect of signal-power co-design, directly impacting system performance and reliability. Simultaneously, the faster the temperature change rate, the greater the resulting thermal stress, which has a particularly pronounced impact on advanced packaging structures. Temperature is one of the core factors affecting chip reliability: high temperatures accelerate the migration of metal atoms. When the chip's operating temperature rises, the atomic migration rate in metal interconnects (especially copper interconnects) increases significantly, leading to defects such as voids or build-ups, ultimately potentially causing open-circuit or short-circuit failures. Summary of the Invention

[0003] This application provides a chip adapter board that improves the overall thermal integrity of the chip adapter board through heat dissipation microchannels and through holes, effectively conducts, disperses and manages the heat generated when the chip is working, and optimizes heat dissipation performance.

[0004] The technical solution of this application embodiment is implemented as follows: In a first aspect, embodiments of this application provide a chip adapter board, the chip adapter board including a substrate and a first carrier wafer, wherein the substrate and the first carrier wafer are vacuum bonded; The chip adapter board is divided into a heat dissipation area and an interconnection area; The substrate and the first carrier wafer located in the heat dissipation area are penetrated by multiple thermally conductive vias, and heat dissipation microchannels are distributed between different thermally conductive vias, and the thermally conductive vias are filled with thermally conductive material; The substrate and the first carrier wafer located in the interconnect region are penetrated by a plurality of conductive vias, the different conductive vias are isolated from each other, and the conductive vias are filled with conductive material.

[0005] In some embodiments, the inner wall of the conductive via is oxidized; The substrate material between the heat dissipation microchannel and the heat-conducting via is completely oxidized.

[0006] In some embodiments, the chip adapter board further includes a wiring layer, wherein the wiring layer and the substrate of the chip adapter board and the first carrier wafer are arranged along a first direction, and the first direction is parallel to the extension direction of the thermal via. The conductive via extends to the wiring layer and is connected to the metal interconnect in the wiring layer; The thermal via extends to the wiring layer and is connected to the metal interconnects in the wiring layer.

[0007] In some embodiments, the heat dissipation microchannels are not filled with a medium.

[0008] In some embodiments, the chip adapter is connected to a target semiconductor chip, and the target semiconductor chip is located on the side of the substrate away from the wiring layer; The portion of the conductive via exposed on the substrate away from the wiring layer forms a first UBM structure to transmit signals from the target semiconductor chip; The portion of the thermally conductive via exposed on the substrate away from the wiring layer forms a second UBM structure to dissipate heat from the target semiconductor chip.

[0009] In some embodiments, the chip adapter board also satisfies one or more of the following conditions: The thermally conductive material and the conductive material are made of the same target material; The target material is copper; The thickness of the substrate material between the heat dissipation microchannel and the heat-conducting via is 0.3μm-0.5μm.

[0010] Secondly, embodiments of this application provide a method for forming a chip adapter board, the method comprising: A semiconductor structure comprising a substrate and a first carrier wafer is provided, wherein a portion of the semiconductor structure is a heat dissipation region and another portion of the semiconductor structure is an interconnect region; The substrate located in the heat dissipation area is etched based on the first mask to generate continuous heat dissipation microchannels; wherein, the first mask includes a plurality of first preset patterns, the substrate of the heat dissipation area not covered by the first preset patterns is etched to form the heat dissipation microchannels, and the area covered by the first preset patterns forms a via reservation area. The first surface of the substrate is vacuum bonded to the first carrier wafer, and the first surface of the substrate refers to the etched surface; Based on the second mask template, the substrate and the first carrier wafer located in the via reservation area and the interconnect area are etched. The etched holes in the via reservation area form thermally conductive vias, and the etched holes in the interconnect area form conductive vias. A thermally conductive material is deposited in the thermally conductive vias, and a conductive material is deposited in the conductive vias to form the chip adapter board.

[0011] In some embodiments, after vacuum bonding the first surface of the substrate to the first carrier wafer, the method further includes: The first carrier wafer is thinned, and a buffer layer is deposited on the thinned first carrier wafer; Based on the second mask template, the buffer layer, the substrate, and the first carrier wafer located in the via reservation area and the interconnect area are etched to form a plurality of thermally conductive vias and a plurality of electrically conductive vias.

[0012] In some embodiments, when both the thermally conductive material and the conductive material are target materials, depositing the thermally conductive material into the thermally conductive via and depositing the conductive material into the conductive via specifically includes: The buffer layer and the inner wall of the conductive via are oxidized, and the substrate material between the heat dissipation microchannel and the heat-conducting via is completely oxidized to form a first oxide layer. The target material is deposited into the thermally conductive via and the electrically conductive via; A wiring layer is formed above the first oxide layer; wherein the wiring layer includes a plurality of metal interconnects, the conductive vias extend to the wiring layer and are connected to the metal interconnects in the wiring layer; the thermally conductive vias extend to the wiring layer and are connected to the metal interconnects in the wiring layer. A second carrier wafer is provided, the semiconductor structure is bonded to the second carrier wafer, and the second carrier wafer is located on the side of the wiring layer away from the substrate; The second surface of the semiconductor structure is etched until the metal filling the conductive and thermal vias is exposed; the second surface is opposite to the first surface. A second oxide layer is formed on the second surface of the semiconductor structure, and a first UBM structure is formed on the portion of the conductive via exposed to the second oxide layer to transmit signals of the target semiconductor chip; a second UBM structure is formed on the portion of the thermally conductive via exposed to the second oxide layer to dissipate heat from the target semiconductor chip.

[0013] Thirdly, the application provides an electronic device that includes at least the chip adapter board as described in the first aspect.

[0014] This application provides a chip adapter board, which includes a substrate and a first carrier wafer, and the substrate and the first carrier wafer are vacuum bonded. The chip adapter board is divided into a heat dissipation area and an interconnection area. The substrate and the first carrier wafer in the heat dissipation area are penetrated by multiple thermally conductive vias, and heat dissipation microchannels are distributed between different thermally conductive vias, and the thermally conductive vias are filled with thermally conductive material. The substrate and the first carrier wafer in the interconnection area are penetrated by multiple conductive vias, and different conductive vias are isolated from each other, and the conductive vias are filled with conductive material. In this way, by etching heat dissipation microchannels in the heat dissipation area of ​​the chip adapter board, and etching thermally conductive vias and conductive vias in the heat dissipation area and the interconnection area respectively, a chip adapter board with high heat dissipation efficiency is provided. The heat dissipation microchannels and vias improve the overall thermal integrity of the chip adapter board, effectively conduct, disperse and manage the heat generated during chip operation, and optimize heat dissipation performance. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the structure of the first type of chip adapter board provided in the embodiments of this application; Figure 2 This is a schematic diagram of the structure of the second type of chip adapter board provided in the embodiments of this application; Figure 3 This is a schematic diagram of substrate material oxidation provided in an embodiment of this application; Figure 4 This is a schematic flowchart of a chip adapter board forming method provided in an embodiment of this application; Figure 5 This is a schematic diagram of the first step of forming a chip adapter board according to an embodiment of this application; Figure 6 This is a schematic diagram of the second step of forming a chip adapter board according to an embodiment of this application; Figure 7 This is a schematic diagram of the third step in the formation of a chip adapter board provided in an embodiment of this application; Figure 8 This is a schematic diagram of the fourth step in the formation of a chip adapter board provided in an embodiment of this application; Figure 9 This is a schematic diagram of the fifth step in the formation of a chip adapter board provided in an embodiment of this application; Figure 10 This is a schematic diagram of the first type of mask etching provided in the embodiments of this application; Figure 11 This is a schematic diagram of the second type of mask etching provided in the embodiments of this application; Figure 12 This is a schematic diagram of an electronic device structure provided in an embodiment of this application.

[0016] It should be noted that the terms "first" and "second" mentioned above are only used to distinguish between different options and do not represent the degree of superiority or inferiority of the options or their priority in the implementation process. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0018] It is understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the disclosure. It should also be noted that, for ease of description, only the parts relevant to the disclosure are shown in the accompanying drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to limit the disclosure. In the following description, references to "some embodiments" describe a subset of all possible embodiments; however, it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict. It should be noted that the terms "first, second, third, fourth" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third, fourth" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0019] In existing chip packaging structures, high temperatures not only accelerate the migration of metal atoms, leading to voids or accumulations in interconnects and causing open or short circuit faults, but also generate significant thermal stress due to rapid temperature changes, affecting the stability and long-term reliability of the packaging structure. Especially in high-power scenarios such as artificial intelligence and high-performance computing, the heat dissipation capabilities of traditional packaging are insufficient to cope with the rapidly increasing power density, becoming a bottleneck restricting system performance and reliability.

[0020] In contrast, advanced packaging structures incorporating silicon interposers offer significant advantages in terms of increased integration density, shorter interconnect lengths, improved signal integrity, and power consumption control through high-density interconnects and multi-chip integration. However, this structure still suffers from interlayer heat dissipation issues, especially in 2.5D / 3D stacked designs, where heat accumulation can exacerbate localized temperature rises and thermal stress, impacting overall thermal management and reliability. Therefore, this application proposes a chip interposer designed to enhance interlayer heat conduction and optimize internal temperature distribution within the package, thereby improving the overall thermal integrity and long-term operational stability of advanced packaging systems.

[0021] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0022] In some embodiments of this application, see Figure 1 This illustrates a schematic diagram of the structure of the first type of chip adapter board 10 provided in an embodiment of this application. Figure 1 As shown, the chip adapter board 10 includes a substrate 110 and a first carrier wafer 140, and the substrate 110 and the first carrier wafer 140 are vacuum bonded; the chip adapter board 10 is divided into a heat dissipation area and an interconnection area; the substrate 110 and the first carrier wafer 140 located in the heat dissipation area are penetrated by a plurality of thermally conductive vias 111, and heat dissipation microchannels 112 are distributed between different thermally conductive vias 111, and the thermally conductive vias 111 are filled with thermally conductive material; the substrate 110 and the first carrier wafer 140 located in the interconnection area are penetrated by a plurality of conductive vias 113, and different conductive vias 113 are isolated from each other, and the conductive vias 113 are filled with conductive material.

[0023] Here, the substrate 110 of the chip adapter board in the heat dissipation area and the first carrier wafer 140 are penetrated by thermally conductive vias 111. The heat generated by the chip can be diffused through the thermally conductive material filled in the thermally conductive vias 111. The heat dissipation microchannels 112 distributed between different thermally conductive vias 111 can also diffuse heat. The substrate 110 of the interconnect area and the first carrier wafer 140 are penetrated by conductive vias 113. The conductive material filled in the conductive vias 113 can transmit the signals generated by the chip.

[0024] In some embodiments, the heat dissipation microchannel 112 is not filled with a dielectric material, and the thermally conductive material filled in the thermally conductive via 111 and the conductive material filled in the conductive via 113 are the same target material, which is copper. Copper can be used for both thermal conduction and electrical conduction.

[0025] It should be noted that copper contains a large number of freely moving electrons, which are responsible for both the transfer of electric charge and heat. Therefore, copper can conduct both heat and electricity.

[0026] It should be noted that in other embodiments, the heat-conducting material can also be gold (Au), silver (Ag), or aluminum (Al); the conductive material can also be gold (Au), silver (Ag), or aluminum (Al). Gold (Au), silver (Ag), and aluminum (Al) can all be used for heat conduction and electrical conduction. This embodiment does not limit the heat-conducting and conductive materials.

[0027] It should be noted that the substrate of the chip adapter board in this embodiment is a silicon substrate. In other embodiments, it can be other types of substrates, and this embodiment does not limit it.

[0028] In this embodiment, please refer to Figure 2 The diagram illustrates the structure of the second type of chip adapter board 10 provided in this embodiment. The substrate material between the heat dissipation microchannel 112 and the heat-conducting via 111 is completely oxidized, and the inner wall of the conductive via 113 is oxidized to form a first oxide layer 114.

[0029] It should be noted that the substrate material between the heat dissipation microchannel 112 and the thermally conductive via 111, as well as the inner wall of the conductive via 113, are oxidized by thermal oxidation or thin film deposition. The resulting first oxide layer 114 also covers the side of the first carrier wafer 140 that is penetrated. The first oxide layer 114 does not cover the thermally conductive via 111 and the conductive via 113.

[0030] Here, the generated first oxide layer 114 can further optimize the heat dissipation efficiency of the heat-conducting via 111.

[0031] like Figure 3 As shown, in some embodiments, the substrate material between the heat dissipation microchannel 112 and the thermally conductive via 111 is completely oxidized, and the inner wall of the conductive via 113 is oxidized; in other embodiments, the substrate material between the heat dissipation microchannel 112 and the thermally conductive via 111 is partially oxidized. In some embodiments, the thickness of the substrate material between the heat dissipation microchannel 112 and the thermally conductive via 111 is 0.3 μm-0.5 μm. When the substrate material between the heat dissipation microchannel 112 and the thermally conductive via 111 is completely oxidized, the heat dissipation effect of this structure is better than that of the structure where the substrate material is partially oxidized; the oxidized substrate material between the heat dissipation microchannel 112 and the thermally conductive via 111 is used as support when the thermally conductive material is filled into the thermally conductive via 111.

[0032] In some embodiments of this application, please refer to... Figure 2 The chip adapter board 10 also includes a wiring layer 120. The wiring layer 120, the substrate 110 of the chip adapter board 10, and the first carrier wafer 140 are arranged along a first direction, and the first direction is parallel to the extension direction of the thermal via 111. The conductive via 113 extends to the wiring layer 120 and is connected to the metal interconnect in the wiring layer 120. The thermal via 111 extends to the wiring layer 120 and is connected to the metal interconnect in the wiring layer 120.

[0033] It should be noted that the material of the metal interconnect is copper, but other materials can be used in other embodiments, and this embodiment does not limit it.

[0034] In this embodiment, the wiring layer 120 includes multiple metal interconnect layers. Several metal interconnect lines in the wiring layer 120 are distributed in different metal interconnect layers. Each metal interconnect layer is isolated by a dielectric (such as silicon dioxide or a material with a lower dielectric constant) to prevent short circuits and signal crosstalk between different metal interconnect layers.

[0035] It should be noted that this embodiment does not limit the number or location distribution of metal interconnects.

[0036] Here, both the thermal via 111 and the conductive via 113 are essentially through-silicon vias (TSVs). The conductive via 113 extends to the wiring layer 120 and is electrically connected perpendicularly to the metal interconnects in the wiring layer 120, transmitting electrical signals inside the chip and dissipating heat generated inside the chip. The thermal via 111 extends to the wiring layer 12 and is electrically connected perpendicularly to the metal interconnects in the wiring layer 120, dissipating heat generated inside the chip.

[0037] In some embodiments of this application, please refer to... Figure 2 The chip adapter board 10 is connected to the target semiconductor chip 20, and the target semiconductor chip 20 is located on the side of the substrate 110 away from the wiring layer 120; the portion of the conductive via 113 exposed on the side of the substrate 110 away from the wiring layer 120 forms a first UBM structure 131 to transmit signals from the target semiconductor chip 20; the portion of the thermal via 111 exposed on the side of the substrate 110 away from the wiring layer 120 forms a second UBM structure 132 to dissipate heat from the target semiconductor chip 20.

[0038] Here, the first UBM structure 131 and the second UBM structure 132 are located on the top surface of the chip adapter plate 10 and connected to the target semiconductor chip 20. The first UBM structure 131 transmits the signal generated by the target semiconductor chip 20 through the conductive via 113; the second UBM structure 132 discharges the heat generated by the target semiconductor chip 20 through the thermal via 111. The top surface of the chip adapter plate 10 refers to the side away from the wiring layer 120.

[0039] In some embodiments, please continue to see Figure 2 A second oxide layer 115 of a certain thickness is deposited on the side of the substrate 110 of the chip adapter board 10 away from the wiring layer 120. The second oxide layer 115 does not cover the thermal via 111 and the conductive via 113. The first UBM structure 131 and the second UBM structure 132 are respectively located on the surface of the second oxide layer 115 and are connected to the target semiconductor chip 20.

[0040] It should be noted that both the first and second UBM structures are composed of multiple layers of thin metal stacks, with a total thickness on the micrometer scale. Each of the stacked thin metal layers has a specific function. Since the top surface of the chip adapter is a silicon substrate, with buried copper interconnects underneath, the first or second UBM structure can adopt an aluminum / nickel-vanadium / copper metal stack structure. The aluminum layer acts as an adhesion layer, directly adhering to the top surface of the chip adapter or to the second oxide layer; the nickel-vanadium alloy layer acts as a barrier layer, preventing the diffusion of copper atoms inside conductive or thermal vias; the copper layer acts as a conductive seed layer for electroplating. Subsequently, through photolithography and electroplating processes, copper pillars of a certain thickness are formed on the surface of this copper layer, and solder caps are formed at the top of the copper pillars to create microbumps for connection with the target semiconductor chip.

[0041] Here, the second oxide layer 115 covers the side of the substrate 110 of the chip adapter board 10 away from the wiring layer 120, which can prevent electrical short circuits in subsequent processes; by not covering the top of the thermal via 111 and the conductive via 113, the metal area for fabricating the UBM structure is exposed; the adhesion strength between the UBM structure and the substrate is enhanced.

[0042] For some embodiments of this application, please refer to Figure 4 This illustrates a flowchart of a chip adapter board forming method provided in an embodiment of this application. Figure 4 As shown, the method includes: S11: Provides a semiconductor structure including a substrate and a first carrier wafer, a portion of the semiconductor structure being a heat dissipation region and another portion of the semiconductor structure being an interconnect region.

[0043] It should be noted that the semiconductor structure can be a silicon interposer or a glass interposer.

[0044] S12: Based on the first mask, the substrate located in the heat dissipation area is etched to generate continuous heat dissipation microchannels; wherein, the first mask includes multiple first preset patterns, the substrate of the heat dissipation area not covered by the first preset patterns is etched to form heat dissipation microchannels, and the area covered by the first preset patterns forms a through-hole reserved area.

[0045] It should be noted that the first preset pattern in the first mask can be a circle, a square, or a polygon.

[0046] S13: Vacuum bond the first surface of the substrate to the first carrier wafer.

[0047] It should be noted that the first surface of the substrate refers to the surface that is being etched.

[0048] S14: Based on the second mask, the substrate and the first carrier wafer located in the via reservation area and the interconnect area are etched. The etched holes in the via reservation area form thermally conductive vias, and the etched holes in the interconnect area form conductive vias.

[0049] It should be noted that the etching holes in the second mask can be circular, square, or polygonal.

[0050] It should be noted that in this embodiment, a positive mask combined with a positive etching (positive photoresist) process is used to etch heat dissipation microchannels, thermally conductive vias and conductive vias on the substrate. In other embodiments, a negative mask combined with a negative etching (reverse photoresist) process can also be used to etch heat dissipation microchannels, thermally conductive vias and conductive vias on the substrate.

[0051] It should be noted that the size of conductive vias and thermal vias is smaller than the size of heat dissipation microchannels.

[0052] S15: Deposit thermally conductive material into the thermally conductive vias and deposit conductive material into the conductive vias to form a chip adapter board.

[0053] It should be noted that in this embodiment, both the thermally conductive and electrically conductive materials are made of copper. In other embodiments, the thermally conductive and electrically conductive materials may also be made of gold, silver, or aluminum.

[0054] Here, the chip adapter board dissipates the heat generated by the target semiconductor chip through the thermally conductive vias in the heat dissipation area and the conductive vias in the interconnect area.

[0055] For some embodiments of this application, please refer to Figure 5 , Figure 6 , Figure 7 , Figure 8 and Figure 9 This illustrates a step-by-step formation diagram of a chip adapter board 10 provided in an embodiment of this application. For example... Figure 5 As shown, a semiconductor structure 30 including a substrate 110 and a first carrier wafer 140 is provided. A portion of the semiconductor structure 30 belongs to a heat dissipation region, and another portion of the semiconductor structure belongs to an interconnect region. The specific steps in forming the chip adapter board include: S101: The substrate 110 located in the heat dissipation area is etched based on the first mask to generate continuous heat dissipation microchannels 112; wherein, the first mask includes multiple first preset patterns, the substrate 110 in the heat dissipation area not covered by the first preset patterns is etched to form heat dissipation microchannels 112, and the areas covered by the first preset patterns form via reservation areas. Please refer to [link to relevant documentation]. Figure 5 (a) and (b) in the example.

[0056] S102: Vacuum bond the first surface of the substrate 110 to the first carrier wafer 140. (See below) Figure 5(c) in the middle; It should be noted that the first surface of the substrate 110 of the semiconductor structure refers to the etched surface.

[0057] S103: Thin the first carrier wafer 140 and deposit a buffer layer 116 on the thinned first carrier wafer 140. (See below) Figure 6 (d) and (e) in the text.

[0058] S104: Based on the second mask, the buffer layer 116, substrate 110, and first carrier wafer 140 located in the via reservation area and interconnect area are etched to form multiple thermally conductive vias 111 and multiple electrically conductive vias 113. Please refer to [link to relevant documentation]. Figure 7 (f) in the middle.

[0059] S105: Oxidize the upper part of the buffer layer 116 and the inner wall of the conductive via 113. The substrate material between the heat dissipation microchannel 112 and the heat-conducting via 111 is completely oxidized to form the first oxide layer 114. Please refer to [link to relevant documentation]. Figure 7 (g) in the middle.

[0060] S106: Deposit the target material into the thermally conductive via 111 and the electrically conductive via 113. (See also...) Figure 7 (h) in the middle.

[0061] S107: A wiring layer 120 is formed above the first oxide layer 114; wherein the wiring layer 120 includes multiple metal interconnects, conductive vias 113 extend into the wiring layer 120 and are connected to the metal interconnects in the wiring layer 120; thermally conductive vias 111 extend into the wiring layer 120 and are connected to the metal interconnects in the wiring layer 120. (See also...) Figure 8 (i) in the middle.

[0062] S108: A second carrier wafer 150 is provided, and the semiconductor structure 30 is bonded to the second carrier wafer 150. The second carrier wafer 150 is located on the side of the wiring layer 120 away from the substrate 110. Please refer to [link to relevant documentation]. Figure 8 (j) in the middle.

[0063] S109: Etch the second surface of the semiconductor structure 30 until the metal filling the conductive via 113 and the thermal via 111 is exposed. See [link to relevant documentation] Figure 9 (k) in the middle; It should be noted that the second surface is opposite to the first surface.

[0064] S110: A second oxide layer 115 is formed on the second surface of the semiconductor structure 30. A first UBM structure 131 is formed by exposing the conductive via 113 to the second oxide layer 115, and a second UBM structure 132 is formed by exposing the thermal via 111 to the second oxide layer 115. Please refer to [link to relevant documentation]. Figure 9 (l) in the middle.

[0065] A chip adapter board is formed on the semiconductor structure according to the above steps.

[0066] Specifically, such as Figure 10 As shown, the first preset pattern on the first mask is used to etch the substrate of the heat dissipation area in a circular pattern. The first preset pattern is transparent, and the part of the first mask other than the first preset pattern is opaque. Therefore, the substrate of the heat dissipation area not covered by the first preset pattern is etched to form heat dissipation microchannels, and the area covered by the first preset pattern forms a through-hole reserved area.

[0067] The first surface of the semiconductor structure 30 is vacuum bonded to the first carrier wafer 140, and the bonded first carrier wafer 140 is thinned to the target thickness. A buffer layer 116 is deposited on the thinned first carrier wafer 140.

[0068] like Figure 11 As shown, thermally conductive and electrically conductive vias are etched into the structure after the deposition of the buffer layer 116 using a second mask. The etched holes on the second mask are circular, etching the via reservation area and interconnect area to form thermally conductive vias 111 and electrically conductive vias 113 respectively. The etched holes on the second mask are transparent, while the parts of the second mask other than the etched holes are opaque. Therefore, the via reservation area not covered by the etched holes forms the thermally conductive via 111, and the interconnect area not covered by the etched holes forms the electrically conductive via 113.

[0069] At this time, the size of the thermally conductive via 111 is smaller than the size of the via reserved area between adjacent heat dissipation microchannels 112, and at least a 0.3μm-0.5μm annular substrate is reserved to support the formation of the thermally conductive via 111.

[0070] Here, vacuum bonding is performed between the semiconductor structure 30 and the first carrier wafer 140 to maintain the stability of the heat dissipation microchannel 112 after bonding.

[0071] It should be noted that the target thickness of the first carrier wafer 140 after bonding is 1-20 μm.

[0072] In some embodiments, the semiconductor structure 30 can be a silicon wafer, and the first carrier wafer 140 can also be a silicon wafer. When the two are bonded, the silicon surface of the semiconductor structure 30 comes into contact with the silicon surface of the first carrier wafer 140, thereby forming a silicon-silicon bonding interface.

[0073] In other embodiments, the semiconductor structure 30 can be a silicon wafer, and the first carrier wafer 140 can also be a silicon wafer, but an oxide layer (such as silicon dioxide) is prepared on the surface of the first carrier wafer 140. When the two are bonded, the silicon surface of the semiconductor structure 30 comes into contact with the oxide surface of the first carrier wafer 140, thereby forming a silicon-oxide bonding interface.

[0074] In some other embodiments, the semiconductor structure 30 is a silicon wafer with an oxide layer on its surface, and the first carrier wafer 140 is also a silicon wafer with an oxide layer on its surface. When the two are bonded, the two oxide surfaces come into contact with each other, thereby forming an oxide-oxide bonding interface.

[0075] It should be noted that the larger the size of the heat dissipation microchannel 112, the greater the stress it experiences during bonding, leading to deformation of the heat dissipation microchannel 112. Therefore, the size of the heat dissipation microchannel 112 should not be set too large; a micrometer-level heat dissipation microchannel is preferable. Meanwhile, the buffer layer 116 deposited on the first carrier wafer 140 can buffer thermal stress.

[0076] At this point, the semiconductor structure, after bonding and buffer layer deposition, has a micron-level heat dissipation microchannel designed inside. This heat dissipation microchannel can significantly enhance heat conduction and diffusion efficiency. The processed semiconductor structure is the same as that of a conventional silicon substrate.

[0077] Furthermore, a first oxide layer 114 is formed on the inner wall of the conductive via 113 and the inner wall of the thermal via 111 above the buffer layer 116 by thermal oxidation or thin film deposition, and the target material is filled into the formed thermal via 111 and conductive via 113. To improve heat dissipation, a relatively thin substrate between the sidewall of the thermal via 111 and the heat dissipation microchannel 112 is completely oxidized, and the thickness of the completely oxidized substrate remains consistent at the bottom and sidewall of the thermal via 111; thus, a uniform first oxide layer 114 is formed on the inner wall of the thermal via 111, and the first oxide layer 114 provides support during subsequent filling of the thermal via 111. In addition, the thickness of the first oxide layer 114 formed on the inner wall of the conductive via 113 is consistent with the thickness of the first oxide layer 114 on the inner wall of the thermal via 111.

[0078] In this embodiment, both the thermally conductive via 111 and the conductive via 113 use metallic copper as the filler material. Filling the thermally conductive via with copper can significantly reduce its internal thermal resistance; while filling the conductive via with copper can effectively reduce its internal resistance. Copper can be used for both thermal and electrical conduction.

[0079] Furthermore, a wiring layer 120 is formed above the first oxide layer 114 by a successive metal thin film deposition process. Each deposition of a metal thin film (e.g., copper, aluminum, etc.) corresponds to the generation of a metal interconnect, ultimately forming a complete wiring structure containing multiple metal interconnects. Thermal vias 111 and conductive vias 113 are respectively connected to the metal interconnects in the wiring layer 120, transmitting electrical signals inside the chip and dissipating heat generated inside the chip through the target material filled inside and the metal interconnects.

[0080] Here, the first oxide layer 114 can prevent the metal atoms of the metal interconnect layer and the metal atoms filled in the thermally conductive vias 111 and the conductive vias 113 from diffusing into the substrate in the semiconductor structure.

[0081] Furthermore, the side of the semiconductor structure 30 located in the wiring layer 120 away from the substrate 110 is bonded to the second carrier wafer 150. The second carrier wafer 150 can be a silicon wafer or a glass wafer, and it is used to provide mechanical support and protection for the semiconductor structure.

[0082] Furthermore, the second surface of the semiconductor structure 30 is etched until the metal filling the conductive via 113 and the thermal via 111 is exposed. A second oxide layer 115 is formed on the second surface of the semiconductor structure 30. The second oxide layer 115 does not cover the thermal via 111 and the conductive via 113. The portion of the conductive via 113 exposed to the second oxide layer 115 forms a first UBM structure 131, which is in contact with the metal filling the conductive via 113. The portion of the thermal via 111 exposed to the second oxide layer 115 forms a second UBM structure 132, which is in contact with the metal filling the thermal via 111.

[0083] Here, the second oxide layer 115 covers the second surface of the semiconductor structure to prevent electrical short circuits in subsequent processes; by not covering the tops of the thermal vias 111 and the conductive vias 113, the metal region for fabricating the UBM structure is precisely exposed; this enhances the adhesion strength between the UBM structure and the substrate. The first UBM structure 131 and the second UBM structure 132 can be connected to the chip; the first UBM structure 131 transmits signals from the chip; and the second UBM structure 132 dissipates heat from the chip.

[0084] In summary, the chip adapter provided in this application provides a semiconductor structure including a heat dissipation area and an interconnection area. Based on a first preset pattern in a first mask, the substrate located in the heat dissipation area is etched to generate continuous heat dissipation microchannels. The first surface of the semiconductor structure is bonded to a first carrier wafer, the first carrier wafer is thinned, and a buffer layer is deposited on the thinned first carrier wafer. Based on etching holes in a second mask, the buffer layer and substrate located in the heat dissipation area and the interconnection area are etched to form multiple thermally conductive vias and multiple electrically conductive vias. A first oxide layer is formed above the buffer layer, on the inner wall of the conductive vias, and on the inner wall of the thermally conductive vias, and metal is deposited onto the substrate. In the thermally conductive vias and conductive vias; a wiring layer is formed above the first oxide layer, the wiring layer including multiple metal interconnects, the conductive vias extending to the wiring layer and connecting with the metal interconnects, and the thermally conductive vias extending to the wiring layer and connecting with the metal interconnects; the semiconductor structure is bonded to the second carrier wafer, the second surface of the semiconductor structure is etched until the metal filled inside the conductive and thermally conductive vias is exposed, a second oxide layer is formed on the second surface of the semiconductor structure, the portion of the conductive vias exposed to the second oxide layer forms a first UBM structure to transmit signals of the chip; the portion of the thermally conductive vias exposed to the second oxide layer forms a second UBM structure to dissipate heat of the chip. In this way, by etching heat dissipation microchannels in the heat dissipation area of ​​the chip adapter board, and etching thermally conductive vias and conductive vias in the heat dissipation area and interconnection area respectively, the thermally conductive vias and conductive vias are connected to the first UBM structure and the second UBM structure respectively, and connected to the chip through the first UBM structure and the second UBM structure, a chip adapter board with high heat dissipation efficiency is provided. The heat dissipation microchannels and vias improve the overall thermal integrity of the chip adapter board, effectively conduct, disperse and manage the heat generated during chip operation, and optimize heat dissipation performance.

[0085] In some embodiments of this application, see Figure 12 This illustrates a structural schematic diagram of the electronic device 40 provided in an embodiment of this application. For example... Figure 7 As shown, the electronic device 40 includes at least the chip adapter board 10 described in the foregoing embodiments.

[0086] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure. It should be noted that in this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0087] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0088] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0089] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0090] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0091] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A chip adapter board, characterized in that, The chip adapter board includes a substrate and a first carrier wafer, and the substrate and the first carrier wafer are vacuum bonded. The chip adapter board is divided into a heat dissipation area and an interconnection area; The substrate and the first carrier wafer located in the heat dissipation area are penetrated by multiple thermally conductive vias, and heat dissipation microchannels are distributed between different thermally conductive vias, and the thermally conductive vias are filled with thermally conductive material; The substrate and the first carrier wafer located in the interconnect region are penetrated by a plurality of conductive vias, the different conductive vias are isolated from each other, and the conductive vias are filled with conductive material.

2. The chip adapter board according to claim 1, characterized in that, The inner wall of the conductive via is oxidized; The substrate material between the heat dissipation microchannel and the heat-conducting via is completely oxidized.

3. The chip adapter board according to claim 1, characterized in that, The chip adapter board further includes a wiring layer, and the wiring layer, the substrate of the chip adapter board, and the first carrier wafer are arranged along a first direction, and the first direction is parallel to the extension direction of the thermal via. The conductive via extends to the wiring layer and is connected to the metal interconnect in the wiring layer; The thermal via extends to the wiring layer and is connected to the metal interconnects in the wiring layer.

4. The chip adapter board according to claim 1, characterized in that, The heat dissipation microchannels are not filled with any medium.

5. The chip adapter board according to claim 3, characterized in that, The chip adapter board is connected to the target semiconductor chip, and the target semiconductor chip is located on the side of the substrate away from the wiring layer; The portion of the conductive via exposed on the substrate away from the wiring layer forms a first UBM structure to transmit signals from the target semiconductor chip; The portion of the thermally conductive via exposed on the substrate away from the wiring layer forms a second UBM structure to dissipate heat from the target semiconductor chip.

6. The chip adapter board according to claim 1, characterized in that, The chip adapter board also meets one or more of the following conditions: The thermally conductive material and the conductive material are made of the same target material; The target material is copper; The thickness of the substrate material between the heat dissipation microchannel and the heat-conducting via is 0.3μm-0.5μm.

7. A method for forming a chip adapter board, characterized in that, The method includes: A semiconductor structure comprising a substrate and a first carrier wafer is provided, wherein a portion of the semiconductor structure is a heat dissipation region and another portion of the semiconductor structure is an interconnect region; The substrate located in the heat dissipation area is etched based on the first mask to generate continuous heat dissipation microchannels; wherein, the first mask includes a plurality of first preset patterns, the substrate of the heat dissipation area not covered by the first preset patterns is etched to form the heat dissipation microchannels, and the area covered by the first preset patterns forms a via reservation area. The first surface of the substrate is vacuum bonded to the first carrier wafer, and the first surface of the substrate refers to the etched surface; Based on the second mask template, the substrate and the first carrier wafer located in the via reservation area and the interconnect area are etched. The etched holes in the via reservation area form thermally conductive vias, and the etched holes in the interconnect area form conductive vias. A thermally conductive material is deposited in the thermally conductive vias, and a conductive material is deposited in the conductive vias to form the chip adapter board.

8. The method according to claim 7, characterized in that, After vacuum bonding the first surface of the substrate to the first carrier wafer, the method further includes: The first carrier wafer is thinned, and a buffer layer is deposited on the thinned first carrier wafer; Based on the second mask template, the buffer layer, the substrate, and the first carrier wafer located in the via reservation area and the interconnect area are etched to form a plurality of thermally conductive vias and a plurality of electrically conductive vias.

9. The method according to claim 8, characterized in that, When both the thermally conductive material and the conductive material are target materials, the deposition of the thermally conductive material into the thermally conductive via and the deposition of the conductive material into the conductive via specifically includes: The buffer layer and the inner wall of the conductive via are oxidized, and the substrate material between the heat dissipation microchannel and the heat-conducting via is completely oxidized to form a first oxide layer. The target material is deposited into the thermally conductive via and the electrically conductive via; A wiring layer is formed above the first oxide layer; wherein the wiring layer includes a plurality of metal interconnects, the conductive vias extend to the wiring layer and are connected to the metal interconnects in the wiring layer; the thermally conductive vias extend to the wiring layer and are connected to the metal interconnects in the wiring layer. A second carrier wafer is provided, the semiconductor structure is bonded to the second carrier wafer, and the second carrier wafer is located on the side of the wiring layer away from the substrate; The second surface of the semiconductor structure is etched until the metal filling the conductive and thermal vias is exposed; the second surface is opposite to the first surface. A second oxide layer is formed on the second surface of the semiconductor structure, and a first UBM structure is formed on the portion of the conductive via exposed to the second oxide layer to transmit signals of the target semiconductor chip; a second UBM structure is formed on the portion of the thermally conductive via exposed to the second oxide layer to dissipate heat from the target semiconductor chip.

10. An electronic device, characterized in that... Includes the chip adapter board according to any one of claims 1 to 6.

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