An on-chip flash memory multi-level prefetch acceleration structure

Abstract

This invention provides a multi-level prefetch acceleration structure for on-chip FLASH memory, relating to the field of processor memory access optimization technology. It includes a first prefetch accelerator with an internal cache and multiple second prefetch accelerators, each second prefetch accelerator corresponding to a flash memory block. When a read request arrives on the bus, the cache of the first prefetch accelerator is first queried. If the required data is available, the first prefetch accelerator directly returns the data; otherwise, the second prefetch accelerator corresponding to the read request is queried. If the data is available, the second prefetch accelerator directly returns the data; if neither is available, the flash memory is accessed, and the cache of the prefetch accelerator is updated. Based on the block design of flash memory in a multi-port parallel access structure, this invention further reduces direct access to the flash memory through a hierarchical prefetch accelerator design, significantly reducing average access latency and improving the overall performance of the system chip.

Description

Technical Field

[0001] This invention relates to the field of processor memory access optimization technology, and more specifically, to a multi-level prefetch acceleration structure for on-chip FLASH memory. Background Technology

[0002] With the increasing demand for high-performance computing in modern system-on-a-chip (SoC), the concurrent access requirements of each processor core to on-chip memory have increased significantly under multi-core architectures, thus placing higher demands on the bandwidth of on-chip memory.

[0003] Compared to SRAM, FLASH memory has a relatively slower access speed and higher read / write latency, resulting in a more significant speed difference between FLASH memory and the processor. This speed difference causes the processor to frequently wait for instructions or data to load, impacting the overall performance of the system chip.

[0004] Therefore, there is an urgent need for an on-chip FLASH memory acceleration structure that can improve FLASH memory access speed and reduce the speed difference between FLASH memory and processor. Summary of the Invention

[0005] The purpose of this invention is to provide a multi-level prefetch acceleration structure for on-chip FLASH memory to improve the aforementioned problems. To achieve this objective, the technical solution adopted by this invention is as follows:

[0006] A multi-level prefetch acceleration structure for on-chip FLASH memory includes a first prefetch accelerator and multiple second prefetch accelerators. Both the first prefetch accelerator and the second prefetch accelerators are equipped with caches. Each second prefetch accelerator corresponds to a flash memory block of the flash memory.

[0007] When a read request arrives on the bus, if the first data is in the cache of the first prefetch accelerator, the first prefetch accelerator sends the first data in its cache to the bus, where the first data is the data corresponding to the read request.

[0008] If the first data is not present in the cache of the first prefetch accelerator, then it is determined whether the first data is present in the cache of the third prefetch accelerator. The third prefetch accelerator is the second prefetch accelerator corresponding to the first flash memory block, and the first flash memory block is a flash memory block that stores the first data.

[0009] If the first data is present in the cache of the third prefetch accelerator, the third prefetch accelerator sends the first data in its cache to the bus;

[0010] If the first data is not present in the cache of the third prefetch accelerator, the flash memory is accessed based on the read request, and the caches of the first prefetch accelerator and the third prefetch accelerator are updated based on the first data.

[0011] As a preferred embodiment of the present invention, the size of the cache line of the first prefetch accelerator is set based on the data bus width;

[0012] The size of the cache line of the second prefetch accelerator is set based on the minimum programming and reading granularity of the flash memory.

[0013] As a preferred embodiment of the present invention, the size of the cache line of the first prefetch accelerator is n times the width of the data bus, where n is an integer greater than 1;

[0014] The size of the cache line of the second prefetch accelerator is m times the minimum programming and reading granularity, where m is an integer greater than 1.

[0015] As a preferred embodiment of the present invention, the address mapping method of the caches of the first prefetch accelerator and the second prefetch accelerator is set-associative mapping.

[0016] As a preferred embodiment of the present invention, the address mapping method of the cache of the first prefetch accelerator is a 2-way set-associative mapping;

[0017] The address mapping method of the cache of the second prefetch accelerator is 4-way set-associative mapping.

[0018] As a preferred embodiment of the present invention, the memory address of the flash memory includes a first field, a second field, and a third field;

[0019] The first field is used to identify the cache line;

[0020] The second field is used to identify a cache group, and a cache group includes multiple cache lines;

[0021] The third field is used to select data from the cached rows.

[0022] As a preferred embodiment of the present invention, updating the caches of the first prefetch accelerator and the third prefetch accelerator based on the first data includes:

[0023] If the cache memory of the first prefetch accelerator or the third prefetch accelerator contains a free first cache line, then the first data is written to the first cache line;

[0024] If there is no free cache line in the cache of the first prefetch accelerator or the third prefetch accelerator, the second cache line in the fourth prefetch accelerator is selected based on the LRU policy, and the second cache line is replaced by the third cache line. The fourth prefetch accelerator is the first prefetch accelerator or the third prefetch accelerator that does not have a free cache line. The third cache line is the cache line containing the first data.

[0025] As a preferred embodiment of the present invention, if a first read request arrives and neither the first prefetch accelerator nor the fifth prefetch accelerator has the second data corresponding to the first read request, then a fourth cache line is written into the caches of the first prefetch accelerator and the fifth prefetch accelerator. The fifth prefetch accelerator is the second prefetch accelerator corresponding to the second flash memory block. The second flash memory block is the flash memory block that stores the second data. The fourth cache line is a cache line containing the second data.

[0026] If a second read request arrives after the first read request arrives, and neither the first prefetch accelerator nor the fifth prefetch accelerator has the third data corresponding to the second read request, then the fifth cache line is written into the caches of the first prefetch accelerator and the fifth prefetch accelerator. The third data is data in the second flash memory block that is different from the second data. The fifth cache line is a cache line containing the third data.

[0027] If a third read request arrives after the second read request arrives, and the fourth cache line in the cache of the fifth prefetch accelerator is to be replaced based on the LRU policy, the first prefetch accelerator removes the fourth cache line from its cache.

[0028] If the third read request arrives, and the fifth cache line in the cache of the fifth prefetch accelerator is to be replaced based on the LRU policy, the fifth prefetch accelerator removes the fifth cache line from its cache.

[0029] As a preferred embodiment of the present invention, it further includes:

[0030] When a write request arrives on the bus, if a sixth prefetch accelerator exists, the fourth data corresponding to the write request is written into the sixth cache line of the sixth prefetch accelerator and the third flash memory block, respectively. The sixth prefetch accelerator is either the first prefetch accelerator or the second prefetch accelerator that has the first address corresponding to the write request. The sixth cache line is a cache line that has the first address, and the third flash memory block is a flash memory block that has the first address.

[0031] If the sixth prefetch accelerator is not present, the fourth data is written to the third flash memory block.

[0032] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing embodiments of the invention. Attached Figure Description

[0033] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a schematic diagram of a multi-level prefetch acceleration structure for on-chip FLASH memory as described in an embodiment of the present invention;

[0035] Figure 2 This is a schematic diagram of another structure of the multi-level prefetch acceleration structure of on-chip FLASH memory described in an embodiment of the present invention;

[0036] Figure 3 This is a schematic diagram illustrating the relationship between multi-level prefetch accelerators under various cache relationship strategies in an on-chip FLASH memory multi-level prefetch acceleration structure as described in an embodiment of the present invention.

[0037] Figure 4 This is a schematic diagram illustrating the relationship between multi-level prefetch accelerators under a cache relationship strategy in an on-chip FLASH memory multi-level prefetch acceleration structure as described in an embodiment of the present invention.

[0038] Figure 5 This is a schematic diagram illustrating the relationship between multi-level prefetch accelerators under another cache relationship strategy for a multi-level prefetch acceleration structure of on-chip FLASH memory described in an embodiment of the present invention. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0040] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0041] Example 1:

[0042] This embodiment provides a multi-level prefetch acceleration structure for on-chip FLASH memory.

[0043] It should be noted that compared to SRAM, FLASH memory has a relatively slower access speed and higher read / write latency, resulting in a more significant speed difference between FLASH memory and the processor. This speed difference causes the processor to frequently wait for instructions or data to load, impacting the overall performance of the system chip.

[0044] To address the aforementioned issues, this embodiment designs an on-chip FLASH prefetch acceleration structure based on caching principles. Unlike the cache between the processor and main memory, which prefetches necessary instructions or data from main memory for rapid access, the prefetch accelerator in this structure is specifically designed to prefetch instructions or data from the FLASH memory, ensuring a fast response when bus requests arrive. This design improves the access speed of the FLASH memory, thereby enhancing the overall processing performance of the system chip.

[0045] Furthermore, due to the inherent characteristics of high latency and large programming granularity in FLASH memory, prefetch acceleration strategies face unique challenges, particularly regarding miss penalties. When a miss occurs, data must be retrieved from the high-latency FLASH memory, incurring significant penalties. The simplest way to reduce miss penalties is to increase the capacity of the prefetch accelerator. With advancements in manufacturing processes, integrating larger capacity prefetch accelerators on-chip has become increasingly feasible. However, as prefetch accelerator capacity increases, access latency also increases accordingly, as larger prefetch accelerators require longer times for address decoding and data lookup.

[0046] Therefore, this embodiment provides a multi-level prefetch acceleration structure for on-chip FLASH memory based on a high-bandwidth parallel access architecture. This structure, building upon the block-based design of the multi-port parallel access FLASH memory, further reduces direct access to the FLASH memory through a hierarchical prefetch accelerator design, significantly lowering the average access latency and improving the overall performance of the system chip.

[0047] A multi-level prefetch acceleration structure for on-chip FLASH memory, such as Figure 1 As shown, it includes a first prefetch accelerator and multiple second prefetch accelerators. Both the first prefetch accelerator and the second prefetch accelerators are equipped with caches. Each second prefetch accelerator corresponds to a flash memory block of the flash memory.

[0048] When a read request arrives on the bus, if the first data is in the cache of the first prefetch accelerator, the first prefetch accelerator sends the first data in its cache to the bus, where the first data is the data corresponding to the read request.

[0049] If the first data is not present in the cache of the first prefetch accelerator, then it is determined whether the first data is present in the cache of the third prefetch accelerator. The third prefetch accelerator is the second prefetch accelerator corresponding to the first flash memory block, and the first flash memory block is a flash memory block that stores the first data.

[0050] If the first data is present in the cache of the third prefetch accelerator, the third prefetch accelerator sends the first data in its cache to the bus;

[0051] If the first data is not present in the cache of the third prefetch accelerator, the flash memory is accessed based on the read request, and the caches of the first prefetch accelerator and the third prefetch accelerator are updated based on the first data.

[0052] It is understandable that, such as Figure 2 As shown in the diagram, the Level 1 and Level 2 prefetch accelerators refer to the FLASH memory, which is the opposite of the processor's cache level. When an access request arrives, this structure first checks the Level 2 prefetch accelerator. If the Level 2 prefetch accelerator hits, data can be quickly retrieved from it within a single cycle; if the Level 2 prefetch accelerator misses, the system searches the Level 1 prefetch accelerator for the target data based on the high-order address. If the Level 1 prefetch accelerator hits, the data is retrieved directly from it; if the Level 1 prefetch accelerator also misses, the FLASH memory is accessed. When multi-core processors or multi-bus hosts access FLASH memory frequently, traditional solutions relying solely on Level 1 cache are prone to cache thrashing, leading to decreased data consistency and increased access latency. This embodiment, by setting a two-level cache structure, significantly reduces cache thrashing caused by parallel access while ensuring data consistency, thereby effectively improving data read efficiency and system real-time performance.

[0053] As a preferred embodiment, the size of the cache line of the first prefetch accelerator is set based on the data bus width;

[0054] The size of the cache line of the second prefetch accelerator is set based on the minimum programming and reading granularity of the flash memory.

[0055] As a preferred embodiment, the size of the cache line of the first prefetch accelerator is n times the width of the data bus, where n is an integer greater than 1;

[0056] The size of the cache line of the second prefetch accelerator is m times the minimum programming and reading granularity, where m is an integer greater than 1.

[0057] Understandably, taking a FLASH memory IP with a minimum programming and reading granularity of 128 bits and a data bus width of 64 bits as an example, the cache line size of the first-level prefetch accelerator is designed to be 512 bits to address this characteristic. Figure 2 The Chinese character set is represented as 512R, consisting of four 128-bit words. Figure 2 The value is represented as 128W to match the read / write granularity of the FLASH memory; the cache line size of the secondary prefetch accelerator is 256 bits. Figure 2 The Chinese character set is represented as 256R, consisting of four 64-bit double words. Figure 2 The value is 64W to match the width of the data bus and transmission requirements.

[0058] As a preferred embodiment of the present invention, the address mapping method of the caches of the first prefetch accelerator and the second prefetch accelerator is set-associative mapping.

[0059] Understandably, address mapping is a crucial component of cache design, defining how main memory addresses are mapped to cache locations and how the cache efficiently accesses data. A well-designed address mapping not only improves cache hit rate but also optimizes access latency and controls hardware implementation complexity, significantly impacting overall system chip performance. Direct mapping offers the simplest hardware implementation and lowest lookup latency, but it has a higher collision rate and is prone to cache thrashing, where multiple main memory blocks are repeatedly mapped to the same cache line, leading to frequent cache line replacements. Fully associative mapping has the lowest collision rate because main memory blocks can be mapped to any location in the cache, but it has the highest lookup latency. Set-associative mapping combines the advantages of direct and fully associative mapping. The cache is divided into several sets, each supporting a limited degree of associativity, thus achieving a good balance between hit rate and lookup latency. Set-associative mapping effectively reduces collision misses while avoiding the high latency and complexity of fully associative mapping.

[0060] In a multi-level prefetch acceleration architecture for FLASH, when a request arrives, the controller first searches the second-level prefetch accelerator. If the second-level prefetch accelerator hits, the data is required to be returned to the bus within one cycle; if it misses, the data is retrieved from the first-level prefetch accelerator, which also requires retrieval within one cycle. This places high demands on the lookup latency of both levels of prefetch accelerators. If a fully associative mapping method is used for cache address mapping, the lookup latency will increase significantly because fully associative mapping requires row-by-row comparisons throughout the entire prefetch accelerator, increasing the lookup time and failing to meet the single-cycle access requirement. Furthermore, considering the application characteristics of FLASH storage, most data accesses are concentrated on a small number of data blocks, so the prefetch accelerator capacity should not be too large. If a direct mapping method is used, it may lead to cache conflict problems because multiple data blocks may be mapped to the same location, resulting in frequent replacement operations, affecting the cache hit rate, and thus impacting performance.

[0061] To address these issues, this embodiment employs a set-associative mapping approach for address mapping between the first-level and second-level prefetch accelerators. By dividing the prefetch accelerators into multiple groups, each group can store multiple cache lines, thereby reducing cache conflicts. Furthermore, since the lookup range is smaller than that of fully associative mapping, lookup latency is also reduced, meeting the requirement of single-cycle access.

[0062] As a preferred embodiment of the present invention, the address mapping method of the cache of the first prefetch accelerator is a 2-way set-associative mapping;

[0063] The address mapping method of the cache of the second prefetch accelerator is 4-way set-associative mapping.

[0064] Understandably, for a Level 1 prefetch accelerator in a multi-level FLASH prefetch architecture, its capacity is relatively small, primarily prefetching data from one block of FLASH memory. To maximize prefetch hit rate while maintaining single-cycle access, a 4-way set-associative mapping is used. This method effectively reduces prefetch conflicts and improves prefetch hit rate, thus ensuring efficient data access within a smaller-capacity prefetch accelerator. For a Level 2 prefetch accelerator in a multi-level FLASH prefetch architecture, it needs to prefetch n blocks of FLASH data, resulting in a larger capacity compared to the Level 1 prefetch accelerator, and therefore a slower access speed. To optimize performance, lookup latency needs to be reduced to compensate for the speed decrease caused by the larger capacity. Therefore, a 2-way set-associative mapping is used. This mapping method makes the lookup process more efficient, thereby shortening the access time.

[0065] As a preferred embodiment, the memory address of the flash memory includes a first field, a second field, and a third field;

[0066] The first field is used to identify the cache line;

[0067] The second field is used to identify a cache group, and a cache group includes multiple cache lines;

[0068] The third field is used to select data from the cached rows.

[0069] Understandably, the memory address is divided into three parts: the high-order Tag field identifies the data block, the middle Index field locates the specific group, and the low-order Offset field selects the specific data within the data block. During each access, the Index field first locates the specific group, then the Tag field is compared with the Tag value of each cache block within that group, while simultaneously checking if the corresponding valid bit is 1. If a Tag value matches the input Tag field and its valid bit is 1, a prefetch hit is detected, and the hit signal is activated. Subsequently, the corresponding data block is output to the data bus via a multiplexer. The entire hit determination and output process can be completed within one clock cycle, thus achieving high-speed data access.

[0070] Meanwhile, the 2-way set-associative approach maintains a good prefetch hit rate. Similar to the set-associative mapping principle of the first-level prefetch accelerator, the second-level prefetch accelerator determines a hit by matching the Tag field of the address with the Tag in the cache block and combining this with the determination of the valid bits. After selecting the matching data through a multiplexer, the data can be quickly driven onto the bus when a hit occurs, ensuring efficient access in a single cycle.

[0071] As a preferred embodiment of the present invention, updating the caches of the first prefetch accelerator and the third prefetch accelerator based on the first data includes:

[0072] If the cache memory of the first prefetch accelerator or the third prefetch accelerator contains a free first cache line, then the first data is written to the first cache line;

[0073] If there is no free cache line in the cache of the first prefetch accelerator or the third prefetch accelerator, the second cache line in the fourth prefetch accelerator is selected based on the LRU policy, and the second cache line is replaced by the third cache line. The fourth prefetch accelerator is the first prefetch accelerator or the third prefetch accelerator that does not have a free cache line. The third cache line is the cache line containing the first data.

[0074] Understandably, in the design of prefetch accelerators, the choice of replacement algorithm and data consistency maintenance strategy directly determine the system's performance and implementation complexity. LRU and LFU replacement algorithms fully utilize the principle of locality, prioritizing the retention of data blocks that conform to temporal or frequency locality, while FIFO and random replacement strategies do not reflect locality characteristics. Therefore, most mainstream caching systems currently employ LRU or LFU replacement strategies.

[0075] Given that the primary function of on-chip FLASH memory is to store instructions rather than data, instruction access typically exhibits strong temporal locality. The LRU replacement algorithm effectively adapts to this characteristic by prioritizing the replacement of the least recently used data block, effectively preserving hot instructions, further improving prefetch hit rate and access efficiency, thereby optimizing performance.

[0076] Furthermore, the LRU replacement algorithm is relatively simple to implement, especially in the scenario described in this embodiment where the cache capacity is small. Efficient management can be achieved with just a doubly linked list. The doubly linked list maintains the access order of cache blocks, with the head storing the most recently accessed data block and the tail storing the least recently used data block. In contrast, the LFU replacement algorithm requires a more complex data structure to track the access frequency of each cache block. It typically combines a hash table and a min-heap to maintain the access frequency order. The hash table is used to quickly locate cache blocks, and the min-heap is used to find the block with the lowest access frequency. Therefore, the implementation complexity of LFU is significantly higher than that of LRU.

[0077] Meanwhile, LRU is better suited for parallel access scenarios. In high-bandwidth parallel access structures, LRU, with its simple insertion and deletion operations, can better handle high-concurrency requests. LFU, on the other hand, performs slightly worse in high-concurrency scenarios because it needs to frequently update the access frequency counter and adjust the min-heap order, potentially leading to significant latency, especially under high concurrency.

[0078] Considering the significant advantages of the LRU replacement algorithm in adapting to the temporal locality of instruction access, hardware implementation complexity, and high concurrency processing capabilities, this embodiment ultimately selected the LRU strategy as the replacement strategy for the multi-level prefetch acceleration structure.

[0079] This embodiment adds a historical record RAM module to store the access history information of each cache line, including the line address and last access time. When a cache hit occurs or replacement is needed, the historical record is updated in real time to ensure it reflects the latest usage status of the cache line. The comparison module quickly locates the least used cache line based on the historical information and generates the corresponding control signal. Then, the LRU circuit module generates a replacement signal and update information for the target line, marks and replaces the least used cache line. The active path selection module accurately selects the target replacement path through a decoder and updates the corresponding cache line with the new data.

[0080] The LRU strategy not only simplifies hardware implementation but also optimizes cache performance. Through this design, the LRU replacement algorithm can efficiently manage the cache at the hardware level, maximizing the response speed and concurrent processing capability when accessing FLASH memory, while ensuring low implementation complexity.

[0081] As a preferred embodiment of the present invention, if a first read request arrives and neither the first prefetch accelerator nor the fifth prefetch accelerator has the second data corresponding to the first read request, then a fourth cache line is written into the caches of the first prefetch accelerator and the fifth prefetch accelerator. The fifth prefetch accelerator is the second prefetch accelerator corresponding to the second flash memory block. The second flash memory block is the flash memory block that stores the second data. The fourth cache line is a cache line containing the second data.

[0082] If a second read request arrives after the first read request arrives, and neither the first prefetch accelerator nor the fifth prefetch accelerator has the third data corresponding to the second read request, then the fifth cache line is written into the caches of the first prefetch accelerator and the fifth prefetch accelerator. The third data is data in the second flash memory block that is different from the second data. The fifth cache line is a cache line containing the third data.

[0083] If a third read request arrives after the second read request arrives, and the fourth cache line in the cache of the fifth prefetch accelerator is to be replaced based on the LRU policy, the first prefetch accelerator removes the fourth cache line from its cache.

[0084] If the third read request arrives, and the fifth cache line in the cache of the fifth prefetch accelerator is to be replaced based on the LRU policy, the fifth prefetch accelerator removes the fifth cache line from its cache.

[0085] In a multi-level caching architecture, the cache relationship strategy refers to the rules and methods by which data is organized and stored between different levels of cache. The design of the relationship strategy directly affects cache space utilization, data consistency management complexity, and overall performance. Common cache relationship strategies include Inclusive, Exclusive, and NINE (non-inclusive non-exclusive) strategies. The relationship strategy determines the distribution relationship of data blocks in the two levels of cache and the rules for data migration between cache levels. Figure 3 As shown, the Inclusive strategy means that the L2 cache of the second-level prefetch accelerator must contain all the contents of the L1 cache of the first-level prefetch accelerator, that is, the L1 cache is a strict subset of the L2 cache; the Exclusive strategy means that the L1 and L2 caches are completely mutually exclusive, that is, the data in the L1 and L2 caches do not overlap at all; the NINE strategy allows the contents of the L1 and L2 caches to be neither strictly inclusive nor completely mutually exclusive.

[0086] Due to the difference between the FLASH multi-level prefetch accelerator and the multi-level cache in this embodiment, the Inclusive strategy loses its meaning in this scenario, so the Inclusive strategy is not considered.

[0087] like Figure 4 As shown, in the Exclusive policy, if a read request for data X arrives, both L2 and L1 are in a miss state, so the cache line containing X is filled from FLASH into the L2 prefetch accelerator. If a read request for data Y arrives, both L2 and L1 are still in a miss state, so the cache line containing Y is filled from FLASH into the L2 prefetch accelerator. If another read request for data Z arrives at this time, if the cache line containing X must be evicted from the L1 prefetch accelerator, that is, if the cache line will be replaced due to the LRU policy, then it will be removed from the L2 prefetch accelerator and written into the L1 prefetch accelerator.

[0088] The Exclusive strategy enables data to migrate dynamically between different caches, which can reduce some duplicate data and thus maximize the use of cache space. However, it is relatively complex to implement. For this FLASH multi-level prefetch acceleration structure, since the prefetch accelerator capacity is small, the Exclusive strategy may result in data frequently jumping between the L1 prefetch accelerator and the L2 prefetch accelerator, leading to a significant increase in power consumption.

[0089] like Figure 5As shown, in the NINE strategy, if a read data request X arrives, both the L2 and L1 prefetch accelerators are in a miss state. Therefore, cache lines containing X are filled from FLASH into the L1 and L2 prefetch accelerators. If a read data request Y arrives, L2 and L1 are still in a miss state. Therefore, cache lines containing Y are continued to be filled from FLASH into the L1 and L2 prefetch accelerators. If another read data request arrives at this time, if a cache line containing X must be evicted from the L1 prefetch accelerator, it will be evicted from the L2 prefetch accelerator without affecting the L1 prefetch accelerator. If a cache line containing Y must be evicted from the L1 prefetch accelerator, it will be evicted from the L1 prefetch accelerator without affecting the L2 prefetch accelerator.

[0090] Compared to the Exclusive strategy, the NINE strategy is simpler to implement in hardware. When the L2 prefetch accelerator is full and data needs to be evicted, the L1 prefetch accelerator does not need to be notified. Similarly, when the L1 prefetch accelerator is full and data needs to be evicted, the L2 prefetch accelerator does not need to be notified. This simplifies cache management logic and avoids frequent data migration between the L1 and L2 prefetch accelerators. In high-bandwidth parallel access scenarios, this design is more suitable for the multi-level prefetch acceleration structure of FLASH memory, and therefore it has been selected as the final implementation scheme for the relationship strategy of FLASH multi-level prefetch acceleration structure.

[0091] As a preferred embodiment, it also includes:

[0092] When a write request arrives on the bus, if a sixth prefetch accelerator exists, the fourth data corresponding to the write request is written into the sixth cache line of the sixth prefetch accelerator and the third flash memory block, respectively. The sixth prefetch accelerator is either the first prefetch accelerator or the second prefetch accelerator that has the first address corresponding to the write request. The sixth cache line is a cache line that has the first address, and the third flash memory block is a flash memory block that has the first address.

[0093] If the sixth prefetch accelerator is not present, the fourth data is written to the third flash memory block.

[0094] Understandably, in a multi-level prefetch accelerator architecture, the write operation strategy determines how data is written to the prefetch accelerator and FLASH memory, directly affecting data consistency between the multi-level prefetch accelerator and FLASH. First, let's analyze the write hit scenario. If a write-back strategy is adopted, only the data in the prefetch accelerator is modified, without immediately writing it to FLASH. The data is only written back to FLASH when the cache line is replaced. However, due to the complexity of FLASH memory operations, this write-back strategy is difficult to implement in this architecture. Therefore, this design chooses a write-through strategy. When a write hit occurs in the L1 or L2 prefetch accelerator, data is written to both the prefetch accelerator and FLASH memory simultaneously, thus ensuring data consistency between the prefetch accelerator and FLASH memory. For write misses, this design employs a non-write allocation strategy paired with the write-through strategy. When a write operation misses the prefetch accelerator, the data is directly written to FLASH.

[0095] This embodiment first addresses the issue of insufficient available bandwidth of on-chip memory in multi-core architectures by designing a multi-port parallel access structure. Furthermore, addressing the speed mismatch between on-chip FLASH memory and the on-chip main processor, a high-bandwidth parallel access structure with multi-level cache prefetching of FLASH memory is designed based on cache principles. This structure, taking into account the inherent characteristics of FLASH memory and the decentralized integration of memory in parallel access architectures, incorporates a two-level prefetch accelerator relationship strategy, address mapping method, replacement algorithm, and write operation strategy to reduce the number of direct accesses to FLASH memory and improve the overall processing performance of the system chip.

[0096] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0097] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A multi-level prefetch acceleration structure for on-chip FLASH memory, characterized in that, It includes a first prefetch accelerator and multiple second prefetch accelerators. Both the first prefetch accelerator and the second prefetch accelerators are equipped with caches. Each second prefetch accelerator corresponds to a flash memory block of the flash memory. When a read request arrives on the bus, if the first data is in the cache of the first prefetch accelerator, the first prefetch accelerator sends the first data in its cache to the bus, where the first data is the data corresponding to the read request. If the first data is not present in the cache of the first prefetch accelerator, then it is determined whether the first data is present in the cache of the third prefetch accelerator. The third prefetch accelerator is the second prefetch accelerator corresponding to the first flash memory block, and the first flash memory block is a flash memory block that stores the first data. If the first data is present in the cache of the third prefetch accelerator, the third prefetch accelerator sends the first data in its cache to the bus; If the first data is not present in the cache of the third prefetch accelerator, the flash memory is accessed based on the read request, and the caches of the first prefetch accelerator and the third prefetch accelerator are updated based on the first data.

2. The on-chip FLASH memory multi-level prefetch acceleration structure according to claim 1, characterized in that... The size of the cache line of the first prefetch accelerator is set based on the data bus width; The size of the cache line of the second prefetch accelerator is set based on the minimum programming and reading granularity of the flash memory.

3. The on-chip FLASH memory multi-level prefetch acceleration structure according to claim 2, characterized in that... The size of the cache line of the first prefetch accelerator is n times the width of the data bus, where n is an integer greater than 1; The size of the cache line of the second prefetch accelerator is m times the minimum programming and reading granularity, where m is an integer greater than 1.

4. The on-chip FLASH memory multi-level prefetch acceleration structure according to claim 3, characterized in that... The address mapping method of the caches of the first prefetch accelerator and the second prefetch accelerator is set-associative mapping.

5. The on-chip FLASH memory multi-level prefetch acceleration structure according to claim 4, characterized in that... The address mapping method of the cache of the first prefetch accelerator is a 2-way set-associative mapping; The address mapping method of the cache of the second prefetch accelerator is 4-way set-associative mapping.

6. The on-chip FLASH memory multi-level prefetch acceleration structure according to claim 5, characterized in that... The memory address of the flash memory includes a first field, a second field, and a third field; The first field is used to identify the cache line; The second field is used to identify a cache group, and a cache group includes multiple cache lines; The third field is used to select data from the cache line.

7. The on-chip FLASH memory multi-level prefetch acceleration structure according to claim 1, characterized in that, The step of updating the caches of the first prefetch accelerator and the third prefetch accelerator based on the first data includes: If the cache memory of the first prefetch accelerator or the third prefetch accelerator contains a free first cache line, then the first data is written to the first cache line; If there is no free cache line in the cache of the first prefetch accelerator or the third prefetch accelerator, the second cache line in the fourth prefetch accelerator is selected based on the LRU policy, and the second cache line is replaced by the third cache line. The fourth prefetch accelerator is the first prefetch accelerator or the third prefetch accelerator that does not have a free cache line. The third cache line is the cache line containing the first data.

8. The on-chip FLASH memory multi-level prefetch acceleration structure according to claim 7, characterized in that... If the first read request arrives and neither the first prefetch accelerator nor the fifth prefetch accelerator has the second data corresponding to the first read request, then the fourth cache line is written into the caches of the first prefetch accelerator and the fifth prefetch accelerator. The fifth prefetch accelerator is the second prefetch accelerator corresponding to the second flash memory block. The second flash memory block is the flash memory block that stores the second data. The fourth cache line is a cache line containing the second data. If a second read request arrives after the first read request arrives, and neither the first prefetch accelerator nor the fifth prefetch accelerator has the third data corresponding to the second read request, then the fifth cache line is written into the caches of the first prefetch accelerator and the fifth prefetch accelerator. The third data is data in the second flash memory block that is different from the second data. The fifth cache line is a cache line containing the third data. If a third read request arrives after the second read request arrives, and the fourth cache line in the cache of the fifth prefetch accelerator is to be replaced based on the LRU policy, the first prefetch accelerator removes the fourth cache line from its cache. If the third read request arrives, and the fifth cache line in the cache of the fifth prefetch accelerator is to be replaced based on the LRU policy, the fifth prefetch accelerator removes the fifth cache line from its cache.

9. The on-chip FLASH memory multi-level prefetch acceleration structure according to claim 1, characterized in that, Also includes: When a write request arrives on the bus, if a sixth prefetch accelerator exists, the fourth data corresponding to the write request is written into the sixth cache line of the sixth prefetch accelerator and the third flash memory block, respectively. The sixth prefetch accelerator is either the first prefetch accelerator or the second prefetch accelerator that has the first address corresponding to the write request. The sixth cache line is a cache line that has the first address, and the third flash memory block is a flash memory block that has the first address. If the sixth prefetch accelerator is not present, the fourth data is written to the third flash memory block.

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