A data processing unit

Abstract

This invention provides a data processing unit, relating to the field of high-performance computing technology. The data processing unit includes a first-precision data masking processing module, a first-precision arithmetic module, and a second-precision arithmetic module. The first-precision data masking processing module is connected to both the first-precision arithmetic module and the second-precision arithmetic module. The first-precision data masking processing module includes a logic operation processing unit and a first multiplexer, with the logic operation processing unit connected to the first multiplexer. The data processing unit provided in this embodiment of the invention reduces module power consumption by using a forced mask to prevent abrupt changes in the input data of the first-precision arithmetic module.

Description

Technical Field

[0001] This invention relates to the field of high-performance computing technology, and more specifically to a data processing unit. Background Technology

[0002] The vector execution unit is the core hardware component in vector processors or modern CPUs that enables data-parallel computing. Its core design philosophy is based on a single-instruction, multiple-data architecture, which processes a group of data elements simultaneously with a single instruction, thereby significantly improving computational parallelism and efficiency.

[0003] With the continuous development of AI technology and large-scale models, the demand for vector operators and vector processors is increasing daily, especially in scenarios requiring high-throughput computing. While they offer significant advantages in specific tasks, their increased power consumption is also quite noticeable. As the parallelism of operations and the types and types of operations that need to be supported continue to increase, their high power consumption problem becomes increasingly prominent. This necessitates the chip to provide a large supply current, while also posing a significant challenge to heat dissipation. Therefore, power consumption control for vector processors has become one of the key focuses of their development.

[0004] In vector processor design, to fully utilize data bandwidth and computing resources, the internal data transfer bus is typically used to its maximum extent. This means that the number of elements transferred within the same clock cycle varies depending on the bit width. To avoid data transfer congestion, vector execution units usually employ different degrees of parallelism for different data types. While this design ensures efficient use of the internal bus bandwidth, it can cause logic jumps in some non-corresponding data type vector execution units during data transfer, increasing power consumption. A common approach to this problem is to create a gated clock for each data type operator and use additional control information to enable and disable the gated clock. This approach has two drawbacks: First, it is unfriendly to back-end chip design, increasing the clock tree hierarchy and making clock convergence more difficult. Second, the control logic is more complex, requiring a certain control margin to enable and disable the gated clock. Summary of the Invention

[0005] To address the problems in the prior art, embodiments of the present invention provide a data processing unit that can at least partially solve the problems existing in the prior art.

[0006] On one hand, the present invention proposes a data processing unit, including a first-precision data mask processing module, a first-precision calculation module, and a second-precision calculation module, wherein the first-precision data mask processing module is connected to both the first-precision calculation module and the second-precision calculation module; wherein: The first precision data mask processing module includes a logic operation processing unit and a first multiplexer, wherein the logic operation processing unit is connected to the first multiplexer; The logic operation processing unit is used to perform logic operation processing based on the mask information and the first precision flag signal to obtain a logic operation control signal. The first multiplexer is used to select the first precision data according to the logic operation control signal and the first mask preset value, to obtain the first part of data corresponding to the first precision calculation module and the second part of data corresponding to the second precision calculation module, and to send the first part of data to the first precision calculation module and the second part of data to the second precision calculation module.

[0007] Specifically, the logic operation processing unit is used for: The inverted first precision flag signal is ORed with the mask information to obtain the logic operation control signal.

[0008] The first precision calculation module includes a first calculation unit, wherein: The first arithmetic unit is used to perform calculations on the first part of the data, obtain and output the first calculation result.

[0009] The second precision calculation module includes a first conversion unit, a second multiplexer, a second calculation unit, a second conversion unit, and a third multiplexer connected in sequence, wherein: The first conversion unit is used to convert the second part of the data to obtain converted data with a second precision. The second multiplexer is used to select the converted data based on the first precision flag signal and the second part of the data to obtain the first selected data; The second arithmetic unit is used to perform calculations on the first selected data, obtain and output a second calculation result; The second conversion unit is used to further convert the second calculation result to obtain reconverted data with a data precision of the first precision; The third multiplexer is used to select the reconverted data based on the first precision flag signal and the second calculation result, and output the selected reconverted data.

[0010] In another aspect, embodiments of the present invention provide a distributed attention computation method, comprising: Logical operation control signals are obtained by performing logical operation processing based on the mask information and the first precision flag signal. The first precision data is selected according to the logic operation control signal and the first mask preset value to obtain the first part of data and the second part of data, and then the first part of data and the second part of data are sent.

[0011] According to one aspect of this disclosure, a vector execution unit is provided, the vector execution unit including the data processing unit as described above.

[0012] According to one aspect of this disclosure, a vector processor is provided, the vector processor including the vector execution unit as described above.

[0013] According to one aspect of this disclosure, a chip is provided that includes the vector processor described above.

[0014] According to one aspect of this disclosure, a board is provided, the board including the chip as described above.

[0015] According to one aspect of this disclosure, an electronic device is provided, the electronic device including the board as described above.

[0016] The data processing unit provided in this embodiment of the invention includes a first-precision data mask processing module, a first-precision calculation module, and a second-precision calculation module. The first-precision data mask processing module is connected to both the first-precision calculation module and the second-precision calculation module. Specifically, the first-precision data mask processing module includes a logic operation processing unit and a first multiplexer, with the logic operation processing unit connected to the first multiplexer. The logic operation processing unit performs logic operation processing based on mask information and a first-precision flag signal to obtain a logic operation control signal. The first multiplexer selects first-precision data based on the logic operation control signal and a first mask preset value to obtain a first portion of data corresponding to the first-precision calculation module and a second portion of data corresponding to the second-precision calculation module. It then sends the first portion of data to the first-precision calculation module and the second portion of data to the second-precision calculation module. By using a forced mask, the input data of the first-precision calculation module does not change abruptly, thereby reducing module power consumption. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings: Figure 1This is a schematic diagram of the structure of a data processing unit provided in an embodiment of the present invention.

[0018] Figure 2 This is a schematic diagram of the structure of the first precision data masking processing module provided in an embodiment of the present invention.

[0019] Figure 3 This is a schematic diagram of the structure of the vector execution unit provided in an embodiment of the present invention.

[0020] Figure 4 This is a schematic diagram of the structure of the first precision calculation module provided in an embodiment of the present invention.

[0021] Figure 5 This is a schematic diagram of the structure of the second precision calculation module provided in an embodiment of the present invention.

[0022] Figure 6 This is a schematic diagram of the structure of the second-precision data masking processing module provided in an embodiment of the present invention.

[0023] Figure 7 This is a schematic diagram of the structure of a data processing unit provided in another embodiment of the present invention. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Here, the illustrative embodiments and descriptions of the present invention are used to explain the present invention, but are not intended to limit the present invention. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other.

[0025] Explanation of relevant terms: AI stands for Artificial Intelligence.

[0026] SIMD: Single Instruction Multiple Data, which allows a single instruction to perform operations on multiple data simultaneously.

[0027] Operational parallelism: The number of elements that can be operated on simultaneously within a single physical clock cycle.

[0028] Data processing unit: It is a vector data processing unit contained in the vector execution unit, and is a general term for the vector arithmetic logic unit (Vector ALU) and the vector multiply-add unit (Vector MAC), etc.

[0029] Figure 1 This is a schematic diagram of the structure of a data processing unit provided in an embodiment of the present invention, as shown below. Figure 1As shown, the data processing unit provided in this embodiment of the invention includes a first-precision data mask processing module 1, a first-precision calculation module 2, and a second-precision calculation module 3. The first-precision data mask processing module 1 is connected to both the first-precision calculation module 2 and the second-precision calculation module 3. The first precision data mask processing module 1 includes a logic operation processing unit and a first multiplexer, wherein the logic operation processing unit is connected to the first multiplexer; for example Figure 2 As shown, the FP16 mask unit corresponds to the first precision data mask processing module 1.

[0030] The logic operation processing unit is used to perform logic operation processing based on the mask information and the first precision flag signal to obtain a logic operation control signal; such as Figure 2 As shown, the first precision flag signal is FP16_flag, the mask information is mask, Data1 is the first precision data, such as FP16 data, and Data2 is the second precision data, such as FP32 data. That is, the data precision of the first precision data is lower than that of the second precision data. Both the first precision data and the second precision data are input data used for calculation by the data processing unit.

[0031] The first multiplexer is used to select the first precision data according to the logic operation control signal and the first mask preset value, to obtain the first part of data corresponding to the first precision calculation module 2 and the second part of data corresponding to the second precision calculation module 3, and to send the first part of data to the first precision calculation module 2 and the second part of data to the second precision calculation module 3.

[0032] Optionally, the data processing unit also includes an adaptive mask generation unit, which is connected to the first-precision data mask processing module. This adaptive mask generation unit is used to detect the input data jump rate, the load rate of the data processing unit, and the pipeline execution stage inside the data processing unit in real time, and generate a dynamic adaptive mask factor to realize the mask strategy adjustment by intensity and stage, replacing the traditional fixed mask method and achieving fine power consumption control.

[0033] Specifically, the data processing unit load rate refers to the total load rate of the first precision processing module and the second precision processing module.

[0034] In one feasible implementation, a strong masking strategy is enabled when the input data jump rate is high (e.g., above a first jump rate threshold) and / or the computation unit load rate is low (e.g., below a first load threshold); a half-masking strategy is enabled when the input data jump rate is moderate (e.g., between a first jump rate threshold and a second jump rate threshold) and / or the computation unit load rate is moderate (e.g., between a first load threshold and a second load threshold); and a masking strategy is disabled when the input data jump rate is low (e.g., below a second jump rate threshold) and / or the computation unit load rate is high (e.g., above a second load threshold, or running at full load).

[0035] Among them, the strong masking strategy means that when the dynamic adaptive masking factor is enabled (e.g., '1'), the fine-grained masking control signal is fully effective, the first multiplexer forces the output of the programmable mask preset value, completely shields the original input data, and keeps the input of the non-working operation module at a constant level without any jumps.

[0036] Among them, the half-masking strategy refers to the dynamic adaptive masking factor being half-enabled, and the fine-grained masking control signal only masking the high-order part of the data / sign bit / exponent bit, while the mantissa part is transmitted normally, or only clamping non-critical paths.

[0037] The mask-off strategy refers to setting the dynamic adaptive mask factor to invalid (e.g., '0'), thus masking the mask control logic and directly outputting the original data to maximize computational performance.

[0038] In another feasible implementation, the adaptive mask generation unit also applies mask control of different intensities in cycles according to the pipeline execution stage.

[0039] The pipeline execution phase refers to the pipeline phase within the data processing unit itself. This is used as an example, not a limitation, and includes the data fetch phase, masking phase, execution phase, precision conversion phase, and write-back phase. The adaptive mask generation unit adaptively adjusts its masking strategy based on the current pipeline phase: a strong masking strategy is enabled during the masking and execution phases to clamp the input data of non-working modules, preventing jumps; a half-masking strategy or a disabled masking strategy is enabled during the data fetch and write-back phases to ensure normal data reading and writing and result output. This achieves phased and refined power consumption optimization without affecting computational functionality.

[0040] Correspondingly, the logic operation processing unit is used to perform combined logic processing on the inverted first precision flag signal, the original mask information and the dynamic adaptive mask factor to obtain a refined mask control signal, thereby improving control flexibility and accuracy.

[0041] The combinational logic processing includes: performing an OR operation between the inverted first precision flag signal and the original mask information, and then performing an AND operation between the inverted first precision flag signal and the dynamic adaptive mask factor to obtain the refined mask control signal.

[0042] Optionally, the first-precision data masking processing module further includes a mask preset value configuration register group, used to dynamically configure programmable mask preset values ​​according to the current operation type. Correspondingly, the first multiplexer is used to select and output the first-precision data according to the fine-tuning mask control signal and the programmable mask preset value, obtaining a first part of data input to the first-precision operation module and a second part of data input to the second-precision operation module. Forced clamping prevents non-working path inputs from changing, reducing unnecessary power consumption at the source. The second-precision operation module includes a data precision conversion unit and a cross-precision mask expansion unit. The cross-precision mask expansion unit is used to synchronously perform bit-width expansion on the mask information when the data is converted from low-bit width to high-bit width, so that the mask granularity matches the precision of the converted data.

[0043] More specifically, the cross-precision mask extension unit expands a single-bit mask into a multi-bit mask, so that each element of the high-bit-width data after conversion corresponds to an independent mask bit, ensuring that the mask granularity matches the data precision, avoiding problems such as masking failure and masking position offset during cross-precision operations, and ensuring precise and effective power consumption control.

[0044] Optionally, the programmable mask preset values ​​configured in the mask preset value configuration register group include: 0 value, NaN value, infinity value, activation function boundary value, and trigonometric function fixed point value.

[0045] The mask preset value configuration register group dynamically configures programmable mask preset values ​​according to the current operation type, supporting multiple forms such as 0 values, NaN values, infinity values, activation function boundary values, and trigonometric function fixed-point values, making the mask mechanism adaptable to various scenarios such as arithmetic operations, AI activation function operations, and mathematical function operations.

[0046] The operation type refers to the type of mathematical or AI operation performed by the current data operation unit, including but not limited to: arithmetic operations, activation function operations, trigonometric function operations, floating-point multiplication and addition operations, and vector dot product operations.

[0047] The mask preset value configuration register group is a read-write configuration register group, which internally stores the optimal mask preset value corresponding to different operation types. During the instruction decoding stage, the data processing unit automatically identifies the type of operation being executed and selects or writes the corresponding mask preset value from the register group according to the operation type, realizing dynamic, automatic, and real-time programmable configuration.

[0048] As examples, not limitations, when the operation type is arithmetic (addition, subtraction, multiplication, division), the mask preset value is configured to 0 (all zeros in binary) to block non-working paths. When the operation type is ReLU activation function operation, the mask preset value is configured to 0, making ReLU negative input output 0, and the blocked path directly outputs 0, resulting in the lowest power consumption. When the operation type is Sigmoid / Swish activation function, the mask preset value is configured to the function boundary value / saturation value, making the blocked path output conform to a fixed value within the function range, without interfering with the operation. When the operation type is trigonometric function operation (sin / cos), the mask preset value is configured to a specific fixed-point function value, for example, the cosine value corresponding to 90° = 0, and the sin value corresponding to 0° = 0. When the operation type is abnormal value masking, the mask preset value can be configured to NaN, infinity, or invalid flag values ​​to block abnormal data paths and prevent error propagation.

[0049] This invention combines adaptive dynamic adjustment, programmable mask preset, and cross-precision mask collaboration with existing mask processing logic. Without altering the clock tree structure or increasing timing convergence pressure, it achieves intelligent low-power control of multi-precision computing units with minimal hardware area overhead. It is compatible with both general-purpose computing and AI computing scenarios, improving the versatility and performance-to-power ratio of data processing units. Specifically, the adaptive mask generation unit adjusts the mask strength in stages based on data jump rate, load, and pipeline stage. Combined with pre-mask forced clamping of non-working module inputs, invalid data jumps are significantly reduced. Compared to traditional gated clock schemes, this results in more significant power optimization and can intelligently adjust according to actual operating conditions, avoiding performance losses caused by fixed masks. Furthermore, this invention completely abandons the gated clock approach, implementing power control only on the data path without increasing clock tree levels or introducing additional timing margins. This significantly reduces the difficulty of chip physical design, improves the overall timing convergence success rate, and adapts to the design requirements of high-performance processors and AI chips.

[0050] like Figure 3 As shown, the vector execution unit includes a data processing unit, an instruction buffer unit, and a mask parsing unit. The acquisition of mask information and the first precision flag signal is explained below: The instruction cache unit is used to cache instruction information and parse it to obtain the parsing result. The parsing result includes the data length and data type. The data type is specifically the data operation type, such as addition, subtraction, multiplication, and division. The data length reflects the data precision, such as FP16 data.

[0051] The instruction buffer unit sends the data length and data type to the data processing unit. The mask parsing unit parses the mask information and sends it to the data processing unit clockwise (for example, if the data to be sent contains 1024 elements, but the data processing unit can only process a subset of elements per clock cycle, such as 32 / 64 elements, then the data processing unit needs to divide the entire 1024-element vector into multiple segments based on its processing capacity, processing one segment per clock cycle; this is what clockwise processing means). Finally, the actual data processing and masking are performed in the data processing unit.

[0052] The value of the first mask preset is determined according to the specific data type. For example, if the first precision calculation module is the module that calculates the cosine value, and you want the output result of the cosine value calculation to be 0, then the first mask preset value, namely mask_val, is the binary value corresponding to 90 degrees.

[0053] All multiplexers in this invention are also referred to as multiplexers (MUX). Taking the first multiplexer as an example, it selects a first part of data and a second part of data from first-precision data through a logic operation control signal and a first mask preset value. Taking 64 elements as an example, the logic operation control signal can select the high-order 32 elements, i.e., the second part of data, and select the low-order 32 elements, i.e., the first part of data.

[0054] The implementation principles of subsequent multiplexers, such as the second, third, fourth, fifth, and sixth multiplexers, are the same as those of the first multiplexer, and will not be elaborated further.

[0055] like Figure 4 As shown, the F16 operating unit corresponds to the first precision calculation module 2, which includes a first calculation unit, wherein: The first arithmetic unit is used to calculate the first part of the data, obtain and output the first calculation result. The first arithmetic unit is Operator (F16).

[0056] like Figure 5 As shown, the F32 operator unit corresponds to the second precision calculation module 3. The second precision calculation module 3 includes a first conversion unit Fp16 to FP32, a second multiplexer, a second operation unit Operator (F32), a second conversion unit Fp32 to Fp16, and a third multiplexer connected in sequence, wherein: The first conversion unit is used to convert the second part of the data to obtain converted data with a second precision; the first precision is Fp16 and the second precision is Fp32.

[0057] The second multiplexer is used to select the converted data based on the first precision flag signal and the second part of the data to obtain the first selected data; The second arithmetic unit is used to perform calculations on the first selected data, obtain and output a second calculation result; The second conversion unit is used to further convert the second calculation result to obtain reconverted data with a data precision of the first precision; The third multiplexer is used to select the reconverted data based on the first precision flag signal and the second calculation result, and output the selected reconverted data.

[0058] like Figure 2 As shown, the logic operation processing unit is specifically used for: The inverted first precision flag signal is ORed with the mask information to obtain the logic operation control signal. Alternatively, the first precision flag signal can be inverted first to obtain the inverted first precision flag signal ~FP16_flag.

[0059] like Figure 6 As shown, the data processing unit further includes a second-precision data masking module FP32 maskunit, which is connected to the second-precision processing module 3; wherein, the second-precision data masking module includes a fourth multiplexer and a fifth multiplexer; wherein: The fourth multiplexer is used to process the first precision flag signal, the second mask preset value, and the third mask preset value to obtain the first processed data. The second mask preset value and the third mask preset value have the same function as the first mask preset value. The second mask preset value corresponds to FP16, and the third mask preset value corresponds to FP32.

[0060] The fifth multiplexer is used to process the first processed data, the mask information, and the second precision data Data2 to obtain the second processed data, and then send the second processed data to the second precision calculation module 3.

[0061] like Figure 7 As shown, the data processing unit is further explained below: In order to make full use of the internal 1024-bit data bus, the 32 FP32 arithmetic units (second precision arithmetic modules) inside the data arithmetic unit are used to calculate the 32 data elements (32x32=1024 bits) transmitted from the bus during FP32 operations.

[0062] During FP16 operations, the data bus transmits 64 data elements (16 x 64 = 1024 bits). The higher-order 32 elements are converted into FP32 data elements by a type conversion module in the FP32 arithmetic unit before being processed, and then the result is converted back to FP16 for output. The lower-order 32 elements are directly calculated and output in 32 FP16 arithmetic units (first-precision arithmetic modules). The main problem solved by this invention is to reduce the power consumption of the module by using a forced mask to prevent the input data of the 32 FP16 arithmetic units from changing during FP32 operations.

[0063] The specific implementation process is as follows: 1. The data type signal issued by the instruction parsing unit is parsed to obtain the FP16 flag signal FP16_flag.

[0064] 2. Move the FP16 mask unit before the FP16 operation unit.

[0065] 3. Invert FP16_flag and then OR it with the original mask signal.

[0066] By following the steps above, the input data jump of the FP16 operation unit can be prevented by the original FP16 mask unit when performing FP32 operations, thereby reducing the overall power consumption of the module.

[0067] The data processing unit provided in this invention can achieve power consumption control through a masking process. That is, during the operation, some input elements need to be masked (typically each bit in the mask corresponds to a data element). These data do not participate in the operation, and when the operation result is output, the data area corresponding to these elements may be written with specific values. This invention utilizes this characteristic, processing data by determining the position of the masking process in the pre-processing pipeline and combining it with the data type of the current instruction. This prevents data in invalid paths from transitioning, reducing module power consumption with lower area overhead, while having almost no impact on the chip clock tree, facilitating overall chip timing convergence.

[0068] The data processing unit provided in this invention is mainly used in the vector operation section of various vector processors and neural network accelerators. When the data processing unit needs to support multiple data types simultaneously, the advantages of this invention compared to the traditional method using a gated clock are: Firstly, it simplifies the clock tree structure, making it easier for backend timing convergence.

[0069] Secondly, the control logic is simple and requires little additional logic. By simply placing the vector mask processing logic at the front end, only a small amount of logic needs to be added to the mask input for control, which can effectively prevent data jumps.

[0070] The technical effects of the data processing unit provided in this embodiment of the invention are reflected in the following two aspects: This approach achieves support for operations on multiple data types with a relatively small increase in area. When performing operations on low-width elements, type conversion is used to interchange the data types of high- and low-width elements, thereby reusing high-width arithmetic units to complete some calculations on low-width elements in the bus. By reusing arithmetic units for high-width elements, the number of low-width arithmetic units can be reduced, thus saving chip area.

[0071] Within arithmetic units supporting multiple data types, power consumption of redundant arithmetic units is rationally controlled with minimal area overhead and without impacting the existing clock tree. Considering the masking requirements of the vector processor itself, the position of the pre-masking processing logic within the pipeline, combined with data type information in the instructions, prevents input data from non-valid arithmetic units from transitioning through mask clamping. By fully utilizing the masking logic within the vector processor, power consumption control is achieved with minimal area overhead, without affecting the chip's original clock tree, facilitating timing convergence.

[0072] The data processing unit provided in this embodiment of the invention includes a first-precision data mask processing module, a first-precision calculation module, and a second-precision calculation module. The first-precision data mask processing module is connected to both the first-precision calculation module and the second-precision calculation module. Specifically, the first-precision data mask processing module includes a logic operation processing unit and a first multiplexer, with the logic operation processing unit connected to the first multiplexer. The logic operation processing unit performs logic operation processing based on mask information and a first-precision flag signal to obtain a logic operation control signal. The first multiplexer selects first-precision data based on the logic operation control signal and a first mask preset value to obtain a first portion of data corresponding to the first-precision calculation module and a second portion of data corresponding to the second-precision calculation module. It then sends the first portion of data to the first-precision calculation module and the second portion of data to the second-precision calculation module. By using a forced mask, the input data of the first-precision calculation module does not change abruptly, thereby reducing module power consumption.

[0073] In the above optional embodiments, the logic operation processing unit is specifically used for: The inverted first precision flag signal is ORed with the mask information to obtain the logic operation control signal.

[0074] In the above optional embodiments, the first precision calculation module includes a first calculation unit, wherein: The first arithmetic unit is used to perform calculations on the first part of the data, obtain and output the first calculation result.

[0075] In the above optional embodiments, the second precision calculation module includes a first conversion unit, a second multiplexer, a second calculation unit, a second conversion unit, and a third multiplexer connected in sequence, wherein: The first conversion unit is used to convert the second part of the data to obtain converted data with a second precision. The second multiplexer is used to select the converted data based on the first precision flag signal and the second part of the data to obtain the first selected data; The second arithmetic unit is used to perform calculations on the first selected data, obtain and output a second calculation result; The second conversion unit is used to further convert the second calculation result to obtain reconverted data with a data precision of the first precision; The third multiplexer is used to select the reconverted data based on the first precision flag signal and the second calculation result, and output the selected reconverted data.

[0076] This invention provides a data processing method based on the data processing unit, comprising: Logical operation control signals are obtained by performing logical operation processing based on the mask information and the first precision flag signal. The first precision data is selected according to the logic operation control signal and the first mask preset value to obtain the first part of data and the second part of data, and then the first part of data and the second part of data are sent.

[0077] The data processing method provided in this invention can be used to execute the processing flow of the above system embodiments. Its functions will not be repeated here, but can be referred to the detailed description of the above system embodiments.

[0078] This disclosure also proposes a vector execution unit, which includes the data processing unit described above.

[0079] This disclosure also proposes a vector processor, which includes the vector execution unit described above.

[0080] This disclosure also proposes a chip that includes the vector processor described above.

[0081] This disclosure also proposes a board that includes the chip described above.

[0082] This disclosure also proposes an electronic device, which includes the board described above.

[0083] Compared with existing technologies, the data processing unit provided in this embodiment includes a first-precision data masking module, a first-precision calculation module, and a second-precision calculation module. The first-precision data masking module is connected to both the first-precision calculation module and the second-precision calculation module. Specifically, the first-precision data masking module includes a logic operation processing unit and a first multiplexer, with the logic operation processing unit connected to the first multiplexer. The logic operation processing unit performs logic operation processing based on mask information and a first-precision flag signal to obtain a logic operation control signal. The first multiplexer selects first-precision data based on the logic operation control signal and a first mask preset value to obtain a first portion of data corresponding to the first-precision calculation module and a second portion of data corresponding to the second-precision calculation module. It then sends the first portion of data to the first-precision calculation module and the second portion of data to the second-precision calculation module. By using a forced mask, the input data of the first-precision calculation module does not change, thereby reducing module power consumption.

[0084] In the description of this specification, the references to terms such as "an embodiment," "a specific embodiment," "some embodiments," "for example," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0085] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A data processing unit, characterized in that, It includes a first-precision data mask processing module, a first-precision calculation module, and a second-precision calculation module, wherein the first-precision data mask processing module is connected to both the first-precision calculation module and the second-precision calculation module; wherein: The first precision data mask processing module includes a logic operation processing unit and a first multiplexer, wherein the logic operation processing unit is connected to the first multiplexer; The logic operation processing unit is used to perform logic operation processing based on the mask information and the first precision flag signal to obtain a logic operation control signal. The first multiplexer is used to select the first precision data according to the logic operation control signal and the first mask preset value, to obtain the first part of data corresponding to the first precision calculation module and the second part of data corresponding to the second precision calculation module, and to send the first part of data to the first precision calculation module and the second part of data to the second precision calculation module.

2. The data processing unit according to claim 1, characterized in that, The logic operation processing unit is specifically used for: The inverted first precision flag signal is ORed with the mask information to obtain the logic operation control signal.

3. The data processing unit according to claim 1, characterized in that, The first precision calculation module includes a first calculation unit, wherein: The first arithmetic unit is used to perform calculations on the first part of the data, obtain and output the first calculation result.

4. The data processing unit according to claim 1, characterized in that, The second precision calculation module includes a first conversion unit, a second multiplexer, a second calculation unit, a second conversion unit, and a third multiplexer connected in sequence, wherein: The first conversion unit is used to convert the second part of the data to obtain converted data with a second precision. The second multiplexer is used to select the converted data based on the first precision flag signal and the second part of the data to obtain the first selected data; The second arithmetic unit is used to perform calculations on the first selected data, obtain and output a second calculation result; The second conversion unit is used to further convert the second calculation result to obtain reconverted data with a data precision of the first precision; The third multiplexer is used to select the reconverted data based on the first precision flag signal and the second calculation result, and output the selected reconverted data.

5. A data processing method based on the data processing unit as described in claim 1, characterized in that, include: Logical operation control signals are obtained by performing logical operation processing based on the mask information and the first precision flag signal. The first precision data is selected according to the logic operation control signal and the first mask preset value to obtain the first part of data and the second part of data, and then the first part of data and the second part of data are sent.

6. A vector execution unit, characterized in that, It includes the data processing unit as described in any one of claims 1 to 4.

7. A vector processor, characterized in that, Includes the vector execution unit as described in claim 6.

8. A chip, characterized in that, Includes the vector processor as described in claim 7.

9. A circuit board, characterized in that, Includes the chip described in claim 8.

10. An electronic device, characterized in that, Includes the board as described in claim 9.

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