Single-bit data delay simulation processing system

Abstract

This invention relates to the field of chip technology, and more particularly to a single-bit data delay simulation processing system, comprising a first delay simulation module disposed on the input transmission path, a second delay simulation module disposed on the metastability detection path, and a third delay simulation module disposed on the output transmission path; the first delay simulation module generates a first delay value; the input transmission path transmits data after delaying the data by the first delay value to the metastability detection path; the second delay simulation module determines whether the flip point of the data after delaying the data by the first delay value falls within a preset metastability detection range; if it does, it generates a second delay value; otherwise, it sets the second delay value to 0; the metastability detection path transmits data after delaying the data by the second delay value to the output transmission path; the third delay simulation module includes M-level registers; the output transmission path outputs data after delaying it by M times (T) through the third delay simulation module. This invention improves chip development efficiency.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a single-bit data delay simulation processing system. Background Technology

[0002] In chip development, when a single-bit signal is directed to multiple clock domains, processing of the single-bit data is necessary to suppress the probability of metastability propagation. In front-end simulation, combinational logic wires are idealized and without delay. However, in back-end design, wire routing introduces delay, and due to the relatively broad delay requirements between asynchronous paths, significant delays may occur. Because front-end simulation is overly idealistic and doesn't consider delays, discovering these delays only during gate-level timing simulation (post-simulation) can have a greater impact, leading to serious problems and impacting chip development efficiency. Therefore, introducing delay information into the front-end simulation of single-bit data to identify chip design issues early and improve chip development efficiency is a pressing technical problem. Summary of the Invention

[0003] The purpose of this invention is to provide a single-bit data delay simulation processing system that can introduce delay information for simulation when single-bit data is simulated at the front end, thereby discovering chip design problems as early as possible and improving chip development efficiency.

[0004] According to a first aspect of the present invention, a single-bit data delay simulation processing system is provided, comprising: It includes an input transmission path, a metastable detection path, and an output transmission path arranged in series, as well as a first delay simulation module set in the input transmission path, a second delay simulation module set in the metastable detection path, and a third delay simulation module set in the output transmission path; The first delay simulation module is used to randomly generate a first delay value based on the preset maximum delay value corresponding to the input transmission path; The input transmission path is used to transmit single-bit data to the metastable state detection path after delaying it by a first delay value. The second delay simulation module is used to determine whether the flip point of the single-bit data after the delay of the first delay value falls within the preset metastable detection range. If it falls within the range, a second delay value is randomly generated in the range (0, T], where T is the clock period of the output transmission path. Otherwise, the second delay value is set to 0. The metastable detection path is used to transmit single-bit data to the output transmission path after delaying it by a second delay value. The third delay simulation module includes an M-level register; The output transmission path is used to output single-bit data after delaying it by M times through the third delay simulation module.

[0005] Compared with existing technologies, this invention has significant advantages and beneficial effects. Through the above technical solution, the single-bit data delay simulation processing system provided by this invention achieves considerable technological advancement and practicality, and has broad industrial application value. It possesses at least the following beneficial effects: This invention sets up a first delay simulation module in the input transmission path, a second delay simulation module in the metastable detection path, and a third delay simulation module in the output transmission path, respectively, and sets delay simulation on the three paths. This allows delay information to be introduced for simulation when single-bit data is simulated at the front end, thereby discovering chip design problems as early as possible and improving chip development efficiency. Attached Figure Description

[0006] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0007] Figure 1 This is a schematic diagram of a single-bit data delay simulation processing system provided in an embodiment of the present invention. Detailed Implementation

[0008] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0009] This invention provides a single-bit data delay simulation processing system, such as... Figure 1 As shown, it includes: This includes an input transmission path, a metastable state detection path, and an output transmission path arranged in series, as well as a first delay simulation module set in the input transmission path, a second delay simulation module set in the metastable state detection path, and a third delay simulation module set in the output transmission path. The input transmission path, metastable state detection path, and output transmission path are all paths used in the front-end simulation.

[0010] The first delay simulation module is used to randomly generate a first delay value based on a preset maximum delay value corresponding to the input transmission path. The input transmission path is used to transmit single-bit data to the metastable detection path after delaying by the first delay value. By setting the first delay simulation module, delay simulation is added to the input transmission path during the pre-simulation stage. The preset maximum delay value corresponding to the input transmission path is determined comprehensively based on factors such as the single-bit signal attribute characteristics of the chip design and the toggle frequency. Specifically, the chip design can be a GPU (Graphics Processing Unit) chip design, etc.

[0011] The second delay simulation module is used to determine whether the flip point of the single-bit data after being delayed by the first delay value falls within a preset metastability detection range. If it does, a second delay value is randomly generated within the range (0, T], where T is the clock period of the output transmission path. Otherwise, the second delay value is set to 0. The metastability detection path is used to transmit the single-bit data to the output transmission path after being delayed by the second delay value. By setting the second delay simulation module, delay simulation is added to the metastability detection path in the pre-simulation stage. It should be noted that if the flip point of the single-bit data after being delayed by the first delay value falls within the metastability detection range, metastability may occur. Randomly generating a second delay value within the range (0, T) to delay the single-bit data can reduce the probability of metastability in the single-bit data. When the flip point of the single-bit data after being delayed by the first delay value does not fall within the range (0, T), the single-bit data will definitely not be metastable in the metastability detection path. In this case, the second delay value is set to 0, that is, no delay operation is required in the metastability detection path.

[0012] The third delay simulation module includes an M-level register; the output transmission path is used to delay single-bit data by M times (T) before outputting it. By setting up the three-delay simulation module, delay simulation is added to the output transmission path during the pre-simulation stage. As an example, the value of M can be set to 3, but it is understood that the specific value of M is determined according to the specific single-bit data processing requirements.

[0013] By performing delay simulations in the input transmission path, metastable state detection path, and output transmission path during the pre-simulation stage, delay information can be introduced into the simulation of single-bit data at the front end, thereby identifying chip design problems as early as possible and improving chip development efficiency.

[0014] As one embodiment, the first delay simulation module is used to set a first random range based on the preset maximum delay value corresponding to the input transmission path. If the currently transmitted single-bit data is the first transmission data, the first random range is directly determined as the current random range. Otherwise, a second random range is generated based on the first delay value corresponding to the previous transmission single-bit data, and the intersection of the first random range and the second random range is determined as the current random range. The first delay value corresponding to the currently transmitted single-bit data is generated based on the current random range.

[0015] The delay modes of the first delay simulation module include periodic random mode and time random mode. The periodic random mode is a delay random mode with the clock period of the output transmission path as the unit, and the time random mode is a delay random mode based on the time value.

[0016] As one embodiment, the delay difference between each flip of the single-bit data transmitted on the input transmission path does not exceed 1T.

[0017] As one embodiment, if the delay mode of the first delay simulation module is a periodic random mode, then the first delay value is an integer multiple of T. The first delay simulation module is used to set (0, rounddown(R / T)] as the first random range, where R is a preset maximum delay value and rounddown is a round-down function. If the currently transmitted single-bit data is the first transmitted data, then the first random range is directly determined as the current random range. Otherwise, a second random range [E / T-1, E / T+1] is generated based on the first delay value E corresponding to the previous transmitted single-bit data. It should be noted that, since the first delay value is an integer multiple of T in the periodic random mode, E / T must be an integer. The intersection of (0, rounddown(R / T)] and [E / T-1, E / T+1] is determined as the current random range. A value W is randomly selected from the current random range, where W is an integer. W×T is determined as the first delay value corresponding to the currently transmitted single-bit data.

[0018] In a preferred embodiment, if the frequency of the output transmission path is adjusted, the delay mode of the delay simulation module is set to a periodic random mode. Using the periodic random mode provides better compatibility when the frequency of the output transmission path is adjusted.

[0019] As one embodiment, if the delay mode of the first delay simulation module is a time random mode, the first delay simulation module is used to set (0,R) as a first random range, where R is a preset maximum delay value. If the currently transmitted single-bit data is the first transmitted data, the first random range is directly determined as the current random range. Otherwise, a second random range [ET / 2,E+T / 2] is generated based on the first delay value E corresponding to the previous transmitted single-bit data. The intersection of (0,R) and [ET / 2,E+T / 2] is determined as the current random range. A U value is randomly selected from the current random range, and the U value is determined as the first delay value corresponding to the currently transmitted single-bit data.

[0020] As a preferred embodiment, if a stable clock appears in the output transmission path only after a preset time period from the initial time, that is, there may be no clock within the preset time period from the initial time, in this scenario, if a periodic random mode is used, delay simulation cannot be achieved within the preset time period from the initial time. Therefore, the delay mode of the delay simulation module can be set to a time random mode.

[0021] As one embodiment, the system can be specifically applied in a single-bit data synchronization processing scenario. The serially configured input transmission path, metastability detection path, and output transmission path are single-bit data synchronization processing transmission paths. The input transmission path is the transmission path from the source clock domain to the input interface of the destination clock domain. The metastability detection path is the detection path for the setup time and hold time of the input interface in the destination clock domain. The output transmission path is an output path composed of M cascaded beat registers.

[0022] As a preferred example, the maximum setup time and maximum hold time are selected from the standard cell library to generate the corresponding preset metastable detection range. It should be noted that selecting the maximum setup time and maximum hold time ensures coverage of the entire detection range.

[0023] In another embodiment, the system can be specifically applied to a synchronous processing scenario for asynchronous reset. The serially configured input transmission path, metastability detection path, and output transmission path constitute the asynchronous reset synchronous processing path. The input transmission path is the path from the external reset signal to the asynchronous reset port. The metastability detection path is a detection path for recovery time and removal time set at the input interface of the target register. The output transmission path is an output path composed of M cascaded beat registers.

[0024] As a preferred example, the maximum recovery time and maximum removal time are selected from the standard cell library to generate the corresponding preset metastable detection range. It should be noted that selecting the maximum recovery time and maximum removal time ensures coverage of the entire detection range.

[0025] It should be noted that the backend of chip development needs to perform timing convergence according to the settings in the first delay simulation module, the second delay simulation module, and the third delay simulation module to ensure consistency between the frontend and the backend.

[0026] The system described in this embodiment of the invention sets up a first delay simulation module in the input transmission path, a second delay simulation module in the metastable detection path, and a third delay simulation module in the output transmission path, respectively, and sets delay simulation on the three paths. This allows delay information to be introduced for simulation when single-bit data is simulated at the front end, thereby discovering chip design problems as early as possible and improving chip development efficiency.

[0027] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A single-bit data delay simulation processing system, characterized in that, include: It includes an input transmission path, a metastable detection path, and an output transmission path arranged in series, as well as a first delay simulation module set in the input transmission path, a second delay simulation module set in the metastable detection path, and a third delay simulation module set in the output transmission path; The first delay simulation module is used to randomly generate a first delay value based on the preset maximum delay value corresponding to the input transmission path; The input transmission path is used to transmit single-bit data to the metastable state detection path after delaying it by a first delay value. The second delay simulation module is used to determine whether the flip point of the single-bit data after the delay of the first delay value falls within the preset metastable detection range. If it falls within the range, a second delay value is randomly generated in the range (0, T], where T is the clock period of the output transmission path. Otherwise, the second delay value is set to 0. The metastable detection path is used to transmit single-bit data to the output transmission path after delaying it by a second delay value. The third delay simulation module includes an M-level register; The output transmission path is used to output single-bit data after delaying it by M times through the third delay simulation module.

2. The system according to claim 1, characterized in that, The delay difference between each flip of a single bit of data transmitted on the input transmission path does not exceed 1T.

3. The system according to claim 1 or 2, characterized in that, The first delay simulation module is used to set a first random range based on the preset maximum delay value corresponding to the input transmission path. If the currently transmitted single-bit data is the first transmission data, the first random range is directly determined as the current random range. Otherwise, a second random range is generated based on the first delay value corresponding to the previous transmission single-bit data, and the intersection of the first random range and the second random range is determined as the current random range. The first delay value corresponding to the currently transmitted single-bit data is generated based on the current random range.

4. The system according to claim 3, characterized in that, If the delay mode of the first delay simulation module is a periodic random mode, then the first delay value is an integer multiple of T. The first delay simulation module is used to set (0, rounddown(R / T)] as the first random range, where R is the preset maximum delay value and rounddown is the floor function. If the currently transmitted single-bit data is the first transmitted data, then the first random range is directly determined as the current random range. Otherwise, based on the first delay value E corresponding to the previous transmitted single-bit data, a second random range [E / T-1, E / T+1] is generated. The intersection of (0, rounddown(R / T)] and [E / T-1, E / T+1] is determined as the current random range. A value W is randomly selected from the current random range, where W is an integer. W×T is determined as the first delay value corresponding to the currently transmitted single-bit data.

5. The system according to claim 3, characterized in that, If the delay mode of the first delay simulation module is a time random mode, the first delay simulation module is used to set (0,R) as the first random range, where R is a preset maximum delay value. If the currently transmitted single-bit data is the first transmitted data, the first random range is directly determined as the current random range. Otherwise, a second random range [ET / 2,E+T / 2] is generated based on the first delay value E corresponding to the previous transmitted single-bit data. The intersection of (0,R) and [ET / 2,E+T / 2] is determined as the current random range. A U value is randomly selected from the current random range, and the U value is determined as the first delay value corresponding to the currently transmitted single-bit data.

6. The system according to claim 1, characterized in that, The input transmission path, metastability detection path, and output transmission path configured in series are single-bit data synchronous processing transmission paths. The input transmission path is the transmission path from the source clock domain to the input interface of the destination clock domain; The metastable state detection path is a detection path set for the setup time and hold time of the input interface in the target clock domain; The output transmission path is an output path composed of M cascaded beat registers.

7. The system according to claim 6, characterized in that, Select the maximum setup time and maximum hold time from the standard cell library to generate the corresponding preset metastable detection range.

8. The system according to claim 1, characterized in that, The input transmission path, metastable detection path, and output transmission path configured in series are asynchronous reset synchronous processing paths. The input transmission path is the path from the external reset signal to the asynchronous reset port; The metastable state detection path is a detection path set at the recovery time and removal time of the input interface of the target register; The output transmission path is an output path composed of M cascaded beat registers.

9. The system according to claim 1, characterized in that, Select the maximum recovery time and maximum removal time from the standard cell library to generate the corresponding preset metastable detection range.

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