MOS transistor modeling circuit, method and model including a parasitic bjt
By introducing a parasitic BJT circuit into the SPICE model of the MOSFET and fitting the relationship, the problem of insufficient simulation of LDMOS parasitic BJT characteristics in the existing technology is solved, and more accurate simulation results are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI HUAHONG GRACE SEMICON MFG CORP
- Filing Date
- 2026-02-27
- Publication Date
- 2026-06-02
AI Technical Summary
Existing technologies have shortcomings in simulating the parasitic BJT characteristics of LDMOS. The SPICE model cannot accurately reflect its characteristics, resulting in inaccurate simulation results.
Parasitic BJT circuits are introduced into the SPICE model of MOSFETs. By obtaining the BJT saturation current, maximum DC current gain and base-emitter junction non-ideal saturation current under different active area of the device, the relationship is fitted and added to the model to form a MOSFET model containing parasitic BJTs.
This improves the ability of MOSFET simulation to respond to parasitic BJT characteristics, thereby enhancing the accuracy and reliability of simulation results.
Smart Images
Figure CN122133584A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor simulation technology, and in particular to a MOS transistor modeling circuit, method and model including a parasitic BJT. Background Technology
[0002] MOSFETs are among the most frequently used devices in modern semiconductor integrated circuits and have a wide range of applications. SPICE (Simulation Program with Integrated Circuit Emphasis) is the most widely used circuit-level simulation program in the device design industry.
[0003] LDMOS is a type of MOSFET structure; please refer to [link / reference]. Figure 1 and Figure 2 , Figure 1 It includes the substrate (PSUB), NBL layer, DNW region, drain (D), gate (G), body (B), source (S), P-type drift region, and Nwell region. Figure 2 It includes the substrate (PSUB), NBL layer, DNW region, P-epi layer, drain (D), gate (G), body (B), source (S), N-drift region, and Pwell region.
[0004] However, when the LDMOS is turned on as a high-side switch, the drain voltage rises rapidly to the supply voltage. Due to the presence of parasitic capacitance, the body voltage also rises accordingly. When the voltage difference between the body and source (i.e., the base-emitter voltage of the parasitic PNP transistor) exceeds its turn-on voltage (approximately 0.7V), the parasitic PNP transistor will turn on. Current technology uses the BSIM4 model in SPICE for simulation; however, existing simulations cannot reflect the characteristics of the LDMOS parasitic BJT. Figure 1 The parasitic BJT is formed by three endpoints: Pdrift, NBL, and Psub. It will be enabled when Vpdrift > Vnbl. Figure 2 The parasitic BJT is formed by three terminals: Pwell, NBL, and Psub. It will be turned on when Vpwell > Vnbl = Vd. Summary of the Invention
[0005] The purpose of this invention is to provide a MOS transistor modeling circuit, method, and model that includes a parasitic BJT, which can reflect the parasitic BJT characteristics of the MOS transistor.
[0006] To achieve the above objectives, the present invention provides a MOS transistor modeling circuit including a parasitic BJT, comprising:
[0007] MOSFETs and BJTs: The base of a BJT is connected to the substrate of a MOSFET, the emitter of a BJT is connected to the drain of a MOSFET, and the collector of a BJT is connected to the body of a MOSFET.
[0008] Optionally, in the MOS transistor modeling circuit described above, the MOS transistor is an LDMOS.
[0009] Optionally, in the MOS transistor modeling circuit, the BJT transistor is a PNP transistor.
[0010] This invention also provides a MOS transistor modeling method, comprising:
[0011] In the SPICE model of the MOSFET, the saturation current of the BJT, the maximum DC current gain of the BJT, and the non-ideal saturation current of the base-emitter junction are obtained for MOSFETs with different active region areas.
[0012] The saturation current, maximum DC current gain, and non-ideal saturation current of the base-emitter junction of the BJT are fitted with the area of the active region to obtain the relationship between the saturation current, maximum DC current gain, and non-ideal saturation current of the base-emitter junction of the BJT under different active region areas.
[0013] The aforementioned relationship is added to the SPICE model of the MOSFET to obtain a MOSFET model that includes a parasitic BJT.
[0014] Optionally, in the aforementioned MOS transistor modeling method, the saturation current of the BJT, the maximum DC current gain of the BJT, and the non-ideal saturation current of the base-emitter junction are respectively fitted with the active region area to obtain the relationships between the saturation current of the BJT, the maximum DC current gain of the BJT, and the non-ideal saturation current of the base-emitter junction for MOS transistors with different active region areas, including:
[0015] The saturation current of the BJT under the MOSFET, the maximum DC current gain of the BJT, and the non-ideal saturation current of the base-emitter junction are respectively fitted with the area of the active region to obtain the mathematical fitting trend lines of the saturation current of the BJT, the maximum DC current gain of the BJT, and the non-ideal saturation current of the base-emitter junction.
[0016] The mathematical fitting trend line yields the relationships between the saturation current of BJTs with different active area areas, the maximum DC current gain of BJTs, and the non-ideal saturation current of the base-emitter junction.
[0017] Optionally, in the aforementioned MOS transistor modeling method, the relationship for the saturation current of the BJT is:
[0018] is= 4e-8*(p1*area+p2*pj)* (1 + dis_pnp_pld);
[0019] Where is is the saturation current of the BJT, area is the active region area of the device, pj is the perimeter of the active region of the device, p1 and p2 are both weighting coefficients, and dis_pnp_pld is the process deviation factor.
[0020] Optionally, in the aforementioned MOS transistor modeling method, the relationship for the maximum DC current gain of the BJT is:
[0021] bf = (8E-9 *(p1*area+p2*pj)**(-0.863))* (1 + dbf_pnp_pld);
[0022] Where bf is the maximum DC current gain of the BJT, area is the active region area of the device, pj is the perimeter of the active region of the device, p1 and p2 are both weighting coefficients, and dis_pnp_pld is the process deviation factor.
[0023] Optionally, in the aforementioned MOS transistor modeling method, the relationship between the non-ideal saturation current of the base-emitter junction is:
[0024] ise= 6e-5 * (p1*area+p2*pj)-4E-15;
[0025] Where ise is the non-ideal saturation current of the base-emitter junction, area is the area of the active region of the device, pj is the perimeter of the active region of the device, and p1 and p2 are both weighting coefficients.
[0026] The present invention also provides a MOS transistor model including a parasitic BJT, comprising:
[0027] SPICE model of a MOSFET;
[0028] The relationship between the saturation current of a BJT, the maximum DC current gain of a BJT, and the non-ideal saturation current of the base-emitter junction.
[0029] This invention also provides a simulation method for a MOS transistor model including a parasitic BJT, comprising:
[0030] Simulate the substrate current of a MOS transistor with different channel widths and channel lengths.
[0031] In the MOSFET modeling circuit, method, and model including a parasitic BJT provided in this invention, a parasitic BJT is added to the MOSFET's SPICE model, and the relationships between the BJT's saturation current, maximum DC current gain, and non-ideal saturation current of the base-emitter junction are obtained by fitting the model to MOSFETs with different active region areas. These relationships are then added to the original MOSFET SPICE model to obtain a new MOSFET model including the parasitic BJT. This allows the parasitic BJT characteristics of the MOSFET to be reflected in the simulation. Attached Figure Description
[0032] Figure 1 and Figure 2 This is a schematic diagram of the structure of a MOSFET;
[0033] Figure 3 This is a schematic diagram of a MOS transistor modeling circuit including a parasitic BJT according to an embodiment of the present invention;
[0034] Figure 4 This is a flowchart of a MOS transistor modeling method including a parasitic BJT according to an embodiment of the present invention;
[0035] Figures 5 to 7 These are the values of ib, ic, and beta obtained from tests in embodiments of the present invention;
[0036] Figure 8 A diagram showing the relationship between is and the area of the active region in an embodiment of the present invention;
[0037] Figure 9 A diagram showing the relationship between bf and the area of the active region in an embodiment of the present invention;
[0038] Figure 10 A diagram showing the relationship between ISE and the area of the active region in an embodiment of the present invention;
[0039] Figures 11 to 14 This is a simulation diagram of the substrate current under different channel widths and different channel lengths according to an embodiment of the present invention. Detailed Implementation
[0040] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0041] In the following text, the terms “first,” “second,” etc., are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms, as used herein, may be replaced where appropriate. Similarly, if the methods described herein comprise a series of steps, and the order of these steps presented herein is not necessarily the only possible order in which they can be performed, and some described steps may be omitted and / or other steps not described herein may be added to the method.
[0042] Please refer to Figure 3 This invention provides a MOS transistor modeling circuit including a parasitic BJT, comprising: a MOS transistor and a BJT transistor. The base of the BJT transistor is connected to the substrate (Psub) of the MOS transistor, the emitter of the BJT transistor is connected to the drain of the MOS transistor, and the collector of the BJT transistor is connected to the body terminal (B terminal) of the MOS transistor. When used as a high-side switch, the drain of the MOS transistor is connected to a high-voltage power supply, the source of the MOS transistor is connected to a load, and the gate of the MOS transistor is connected to a control signal. The MOS transistor is an LDMOS, and the BJT transistor is a PNP transistor.
[0043] Please refer to Figure 4 The present invention also provides a method for modeling a MOS transistor including a parasitic BJT, comprising:
[0044] S1: In the SPICE model of the MOSFET, obtain the saturation current of the BJT, the maximum DC current gain of the BJT, and the non-ideal saturation current of the base-emitter junction under the MOSFET with different active area.
[0045] S2: Fit the saturation current of the BJT, the maximum DC current gain of the BJT, and the non-ideal saturation current of the base-emitter junction to the area of the active region, respectively, to obtain the relationship between the saturation current of the BJT, the maximum DC current gain of the BJT, and the non-ideal saturation current of the base-emitter junction under MOS transistors with different active region areas.
[0046] S3: Add the relation to the SPICE model of the MOSFET to obtain the MOSFET model including the parasitic BJT.
[0047] Please refer to Figure 1In step S1, the SPICE model of the MOSFET is an existing MOSFET SPICE model. The SPICE model in this embodiment of the invention uses the BSIM4 model, a physics-based, upgradeable MOSFET model typically used to simulate CMOS device behavior in deep submicron to nanometer scale processes. A biasVg voltage is applied to the gate of the LDMOS, a vd voltage to the drain, a vs voltage to the source, a vb voltage to the body, and a vsub voltage to the substrate. Here, biasVg = 0.5V, Vd = 0~1V, Vs = Vb = Vsub = 0, causing the parasitic PNP transistor formed by Pdrift, NBL, and Psub to turn on, with Pdrift acting as the drain and NBL acting as the base and source terminals. Then, the current Ib at the nbl terminal and the current Ic at the psub terminal are tested. Please refer to... Figures 5 to 7 Ic is the collector current, Ib is the base current, and beta = Ic / Ib.
[0048] In step S2, the saturation current (is), maximum DC current gain (bf), and non-ideal saturation current (ise) of the base-emitter junction of the BJT are fitted with the active region area to obtain the relationships between the saturation current, maximum DC current gain, and non-ideal saturation current of the base-emitter junction of the BJT under different active region areas. These relationships include:
[0049] S21: Fit the saturation current of the BJT under the MOSFET, the maximum DC current gain of the BJT, and the non-ideal saturation current of the base-emitter junction to the area of the active region, respectively, to obtain the mathematical fitting trend lines of the saturation current of the BJT, the maximum DC current gain of the BJT, and the non-ideal saturation current of the base-emitter junction.
[0050] S22: Obtain the relationship between the saturation current of BJTs with different active area, the maximum DC current gain of BJTs, and the non-ideal saturation current of the base-emitter junction by mathematically fitting the trend line.
[0051] like Figures 8 to 10 The horizontal axis represents the area of the active region, and the vertical axes represent the values of is, bf, and ise, respectively. The final relationships are as follows.
[0052] The relationship for the saturation current of a BJT is:
[0053] is= 4e-8*(p1*area+p2*pj)* (1 + dis_pnp_pld);
[0054] Where is is the saturation current of the BJT, area is the active region area of the device, pj is the perimeter of the active region of the device, p1 and p2 are both weighting coefficients, and dis_pnp_pld is the process deviation factor.
[0055] The relationship between the maximum DC current gain of the BJT and the given formula is:
[0056] bf = (8E-9 *(p1*area+p2*pj)**(-0.863))* (1 + dbf_pnp_pld);
[0057] Where bf is the maximum DC current gain of the BJT, area is the active region area of the device, pj is the perimeter of the active region of the device, p1 and p2 are both weighting coefficients, and dis_pnp_pld is the process deviation factor.
[0058] The relationship between the nonideal saturation current of the base-emitter junction is as follows:
[0059] ise= 6e-5 * (p1*area+p2*pj)-4E-15;
[0060] Where ise is the non-ideal saturation current of the base-emitter junction, area is the area of the active region of the device, pj is the perimeter of the active region of the device, and p1 and p2 are both weighting coefficients.
[0061] This invention provides a MOSFET model including a parasitic BJT, comprising:
[0062] SPICE model of a MOSFET;
[0063] The relationship between the saturation current of a BJT, the maximum DC current gain of a BJT, and the non-ideal saturation current of the base-emitter junction.
[0064] The specific MOSFET model including the parasitic BJT is as follows:
[0065] subckt pld16ai (dgsb psub)
[0066] parameters
[0067] +w = 2e-5 l = 5e-7 nf = 1 count = 1 dtemp = 0 count_iso = 1 flag_pbjt= 0
[0068] …
[0069] +ad = w_pdrift*l_pdrift pd=2* (w_pdrift+l_pdrift ) p1=0.8 p2=0.2
[0070] r1 (d d1) resistor r=rds*tfac*(1+vv1*abs(v(d,s))*(tfacv1 / tfac)+vv2*v(d,s)*v(d,s)*(tfacv2 / tfac)) / ((w0*tfacw+w)) m=count*nf
[0071] mxckt (d1 g s1 b) pld16ai w=w l=l as=as ad=ad ps=ps pd=pd nf=1 nrd=1e-3 nrs=1e-3 trise=dtemp m=count*nf
[0072] r2 (s1 s) resistor r=(rds / 20)*(1+vv1*abs(v(s1,s))+vv2*v(s1,s)*v(s1,s)) / (w+w0) m=count*nf
[0073] …
[0074] / / ***parasitc bjt***
[0075] x1 ( psub b d ) pnp_pld area= ad pj= pd m=count_iso
[0076] q0 c b e pnp_pld_model m=count
[0077] +is = ‘4e-8*( p1*area+p2*pj )* ( 1 + dis_pnp_pld)’
[0078] +bf = ‘(8E-9 *( p1*area+p2*pj )**(-0.863))* ( 1 + dbf_pnp_pld )’
[0079] +ise = ‘6e-5 *(p1*area+p2*pj)- 4E-15’
[0080] Where w is the channel width, l is the channel length, nf is the cross exponent, count is the parallel multiplier, dtemp is the temperature offset, count_iso is the number of isolation structures, flag_pbjt is the parasitic BJT switch flag, ad is the area of the drain active region, pd is the perimeter of the drain active region, r1 is the simulated drain drift region resistance, r2 is the simulated source series resistance, x1 is the parasitic BJT element, is the saturation current of the BJT, bf is the maximum DC current gain of the BJT, ise is the non-ideal saturation current of the base-emitter junction, area is the area of the device active region, pj is the perimeter of the device active region, and p1 and p2 are both weighting coefficients.
[0081] The present invention also provides a simulation method for a MOS transistor model including a parasitic BJT, comprising: simulating the substrate current of the MOS transistor under different channel widths and channel lengths.
[0082] like Figures 11 to 14 As shown in the figure, the simulation curve and the measured data have a good fit, therefore, the obtained model is good.
[0083] In summary, the MOSFET modeling circuit, method, and model including a parasitic BJT provided in this embodiment of the invention add a parasitic BJT to the MOSFET's SPICE model and fit the relationships between the BJT's saturation current, maximum DC current gain, and non-ideal saturation current of the base-emitter junction for MOSFETs with different active region areas. These relationships are then added to the original MOSFET SPICE model to obtain a new MOSFET model including a parasitic BJT. This allows the parasitic BJT characteristics of the MOSFET to be reflected in the simulation.
[0084] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.
Claims
1. A MOS transistor modeling circuit including a parasitic BJT, characterized in that, include: MOSFETs and BJTs: The base of a BJT is connected to the substrate of a MOSFET, the emitter of a BJT is connected to the drain of a MOSFET, and the collector of a BJT is connected to the body of a MOSFET.
2. The MOS transistor modeling circuit as described in claim 1, characterized in that, The MOSFET is an LDMOS.
3. The MOS transistor modeling circuit as described in claim 1, characterized in that, The BJT tube is a PNP type.
4. A MOS transistor modeling method using the MOS transistor modeling circuit according to any one of claims 1 to 3, characterized in that, include: In the SPICE model of the MOSFET, the saturation current of the BJT, the maximum DC current gain of the BJT, and the non-ideal saturation current of the base-emitter junction are obtained for MOSFETs with different active region areas. The saturation current, maximum DC current gain, and non-ideal saturation current of the base-emitter junction of the BJT are fitted with the area of the active region to obtain the relationship between the saturation current, maximum DC current gain, and non-ideal saturation current of the base-emitter junction of the BJT under different active region areas. The aforementioned relationship is added to the SPICE model of the MOSFET to obtain a MOSFET model that includes a parasitic BJT.
5. The MOS transistor modeling method as described in claim 4, characterized in that, The saturation current, maximum DC current gain, and non-ideal saturation current of the base-emitter junction of the BJT are fitted to the active region area to obtain the relationships between the saturation current, maximum DC current gain, and non-ideal saturation current of the base-emitter junction for MOSFETs with different active region areas. The saturation current of the BJT under the MOSFET, the maximum DC current gain of the BJT, and the non-ideal saturation current of the base-emitter junction are respectively fitted with the area of the active region to obtain the mathematical fitting trend lines of the saturation current of the BJT, the maximum DC current gain of the BJT, and the non-ideal saturation current of the base-emitter junction. The mathematical fitting trend line yields the relationships between the saturation current of BJTs with different active area areas, the maximum DC current gain of BJTs, and the non-ideal saturation current of the base-emitter junction.
6. The MOS transistor modeling method as described in claim 4, characterized in that, The relationship for the saturation current of a BJT is: is= 4e-8*(p1*area+p2*pj)* (1 + dis_pnp_pld); Where is is the saturation current of the BJT, area is the active region area of the device, pj is the perimeter of the active region of the device, p1 and p2 are both weighting coefficients, and dis_pnp_pld is the process deviation factor.
7. The MOS transistor modeling method as described in claim 4, characterized in that, The relationship between the maximum DC current gain of a BJT is: bf = (8E-9 *(p1*area+p2*pj)**(-0.863))* (1 + dbf_pnp_pld); Where bf is the maximum DC current gain of the BJT, area is the active region area of the device, pj is the perimeter of the active region of the device, p1 and p2 are both weighting coefficients, and dis_pnp_pld is the process deviation factor.
8. The MOS transistor modeling method as described in claim 4, characterized in that, The relationship between the nonideal saturation current of the base-emitter junction is: ise= 6e-5 * (p1*area+p2*pj)-4E-15; Where ise is the non-ideal saturation current of the base-emitter junction, area is the area of the active region of the device, pj is the perimeter of the active region of the device, and p1 and p2 are both weighting coefficients.
9. A MOS transistor model including a parasitic BJT formed using the MOS transistor modeling circuit as described in any one of claims 1 to 3, characterized in that, include: SPICE model of a MOSFET; The relationship between the saturation current of a BJT, the maximum DC current gain of a BJT, and the non-ideal saturation current of the base-emitter junction.
10. A simulation method using a MOS transistor model including a parasitic BJT as described in claim 9, characterized in that, include: Simulate the substrate current of a MOS transistor with different channel widths and channel lengths.