A method for manufacturing a laser chip and a laser chip

Abstract

This disclosure provides a method for fabricating a laser chip and the laser chip itself. An N-type Inp layer is grown on a substrate. A first active layer, a conductive layer, and a second active layer are sequentially grown on top of the N-type Inp layer. A P-type Inp layer, a contact layer, and a mask layer are sequentially grown on top of the first, conductive, and second active layers. Using the mask layer as a mask, the contact layer is etched at a first position above the first active layer, a second position below the conductive layer, and a third position below the second active layer. A passivation layer is deposited, and mask etching is performed at the middle position of the passivation layer. Using the mask layer and the passivation layer as masks, etching is performed at the middle position of the N-type Inp layer down to below the N-type Inp layer. A first element is ion-implanted into the N-type Inp layer at an angle. By using angled ion implantation, the first element is implanted into the N-type Inp layer below the conductive layer, ensuring that the ion implantation depth of the N-type Inp layer meets the required standards.

Description

Technical Field

[0001] This disclosure relates to the field of optical fiber communication technology, and in particular to a method for fabricating a laser chip and the laser chip itself. Background Technology

[0002] Currently, EML chips achieve a single-wavelength modulation rate of 200 GBaud with a power consumption of approximately 100 mW. As optical module integration increases, there is a need to further reduce EML chip power consumption to meet overall power requirements. Differential drive is one effective method for reducing power consumption.

[0003] For EML chips using differential driving, the distributed feedback laser (DFB) and electroabsorption modulator (EAM) need to be electrically isolated to prevent the charge carriers of the DFB and EAM from interfering with each other. Ion implantation is typically used to form the electrical isolation layer to achieve this. However, the maximum energy of the ion implantation equipment limits the implantation depth, making it impossible to achieve the required depth for the electrical isolation layer. Summary of the Invention

[0004] This disclosure provides a method for fabricating a laser chip and a laser chip, such that the ion implantation depth of the electrically insulating layer meets the requirements.

[0005] In some embodiments, a method for fabricating a laser chip is provided, comprising:

[0006] An N-type Inp layer is grown above the substrate. A first active layer, a conductive layer, and a second active layer are grown above the N-type Inp layer. One end of the conductive layer is connected to the first active layer, and the other end of the conductive layer is connected to the second active layer. A P-type Inp layer, a contact layer, and a mask layer are grown sequentially above the first active layer, the conductive layer, and the second active layer.

[0007] Using the mask layer as a mask, the first position of the contact layer is etched downwards to above the first active layer, the second position of the contact layer is etched downwards to below the conductive layer, and the third position of the contact layer is etched downwards to below the second active layer to form the etched chip;

[0008] After etching, a passivation layer is deposited on the chip surface, and the upper surface of the passivation layer at the middle position is etched without a mask to the bottom of the passivation layer; the middle position of the passivation layer is located in the second position of the contact layer within the projection area of ​​the passivation layer;

[0009] Using the mask layer and passivation layer as a mask, the N-type Inp layer is etched downwards from the middle position to below the N-type Inp layer; the middle position of the N-type Inp layer is located in the second position of the contact layer within the projection area of ​​the N-type Inp layer.

[0010] The first element is implanted into the N-type Inp layer and the P-type Inp layer at an inclined angle. The N-type Inp layer below the first active layer and the second active layer is not doped with the first element, while the N-type Inp layer below the conduction layer is doped with the first element. The P-type Inp layer above the first active layer and the second active layer is not doped with the first element, while the P-type Inp layer above the conduction layer is doped with the first element.

[0011] The above technical solution has the following beneficial effects: An N-type Inp layer is grown above the substrate. A first active layer, a conductive layer, and a second active layer are grown above the N-type Inp layer. One end of the conductive layer is connected to the first active layer, and the other end is connected to the second active layer. The first active layer enables the laser chip to emit light. The conductive layer enables the laser chip to conduct light. The second active layer enables the laser chip to modulate light. A P-type Inp layer is grown above the first active layer, the conductive layer, and the second active layer. The P-type Inp layer and the N-type Inp layer form a PN junction, enabling the first active layer to emit light and the second active layer to modulate light. A contact layer is grown above the P-type Inp layer to allow electrical signals to be transmitted to the P-type Inp layer through the contact layer. A mask layer is grown above the contact layer to facilitate etching using the mask layer as a mask. Using a mask layer as a mask, etching is performed downwards from the first position of the contact layer to above the first active layer to form a light-emitting region; downwards from the second position of the contact layer to below the conductive layer; and downwards from the third position of the contact layer to below the second active layer to form a modulation region, thus forming the etched chip. A passivation layer is deposited on the surface of the etched chip, and the upper surface of the passivation layer at its middle position is etched without a mask to below the passivation layer, leaving the side surface at the middle position of the passivation layer intact to form sidewall protection. The middle position of the passivation layer is located within the projection area of ​​the second position of the contact layer. Using the mask layer and the passivation layer as masks, etching is performed downwards from the middle position of the N-type Inp layer to below the N-type Inp layer. The middle position of the N-type Inp layer is located within the projection area of ​​the second position of the contact layer. The same mask layer is used for both mask etching processes to avoid misalignment errors. The first element is implanted into the N-type Inp layer at an angle. The N-type Inp layer below the first and second active layers is not doped with the first element, while the N-type Inp layer below the conductive layer is doped with the first element. This gives the N-type Inp layer below the conductive layer electrical isolation properties, thereby isolating the charge carriers in the N-type Inp layer of the luminescent region from those in the N-type Inp layer of the modulation region. The first element is also implanted into the P-type Inp layer at an angle. The P-type Inp layer above the first and second active layers is not doped with the first element, while the P-type Inp layer above the conductive layer is doped with the first element. This gives the P-type Inp layer above the conductive layer electrical isolation properties, thereby isolating the charge carriers in the P-type Inp layer of the luminescent region from those in the P-type Inp layer of the modulation region. By implanting ions into the N-type Inp layer using this angled ion implantation method, the ion implantation depth of the N-type Inp layer meets the requirements, meaning the ion implantation depth of the electrically isolated layer formed by the doped P-type Inp layer meets the requirements.

[0012] In some embodiments, a method for fabricating a laser chip is provided, wherein a first element is implanted into an N-type Inp layer and a P-type Inp layer at an oblique angle, comprising:

[0013] The first element was implanted into one side of the N-type Inp layer and the P-type Inp layer at an oblique angle.

[0014] The first element was implanted at an angle into the N-type Inp layer and the other side of the P-type Inp layer.

[0015] The above technical solution has the following beneficial effects: the first element is implanted into one side of the N-type Inp layer and the P-type Inp layer at an inclined angle, and the first element is implanted into the other side of the N-type Inp layer and the P-type Inp layer at an inclined angle, which transforms the requirement for the implantation depth limit of the ion implantation device into the control of the width of the N-type Inp layer.

[0016] In some embodiments, a method for fabricating a laser chip is provided, wherein the tilt angle is 0° to 45° and 45° to 60°, but does not include 0° and 45°.

[0017] The above technical solution has the following beneficial effects: the tilt angle θ can be 0°~45° and 45°~60°, but not including 0° and 45°, so that the first element is not implanted along the lattice direction of the N-type Inp layer, reducing the tunneling effect and making it easier to control the implantation depth of the first element in the N-type Inp layer.

[0018] In some embodiments, a method for fabricating a laser chip is provided, wherein the width of the N-type Inp layer and the single ion implantation depth satisfy the following triangular relationship: width=2*d*cosθ, where width is the maximum width of the N-type Inp layer, d is the single ion implantation depth, and θ is the tilt angle.

[0019] The above technical solution has the following beneficial effects: Since the width of the N-type Inp layer and the single ion implantation depth satisfy the following triangular relationship: width=2*d*cosθ, the maximum width of the N-type Inp layer can be calculated based on the limit implantation depth control capability of the ion implantation equipment, thus converting the requirement for the limit implantation depth of the ion implantation equipment into the requirement for the width of the N-type Inp layer.

[0020] In some embodiments, a method for fabricating a laser chip is provided, using a mask layer as a mask, etching downwards at a first position of the contact layer to above the first active layer, etching downwards at a second position of the contact layer to below the conductive layer, and etching downwards at a third position of the contact layer to below the second active layer, including:

[0021] Using the mask layer as a mask, the first position of the contact layer is etched downwards to above the first active layer, the second position of the contact layer is etched downwards to the interior of the N-type Inp layer, and the third position of the contact layer is etched downwards to the interior of the N-type Inp layer.

[0022] The above technical solution has the following beneficial effects: using the mask layer as a mask for downward etching, etching downwards at the first position of the contact layer to the top of the first active layer, etching downwards at the second position of the contact layer to the interior of the N-type Inp layer, and etching downwards at the third position of the contact layer to the interior of the N-type Inp layer, so as to determine whether the second position of the contact layer is etched to the bottom of the conductive layer and whether the third position of the contact layer is etched to the bottom of the second active layer.

[0023] In some embodiments, a method for fabricating a laser chip is provided, which uses a mask layer and a passivation layer as masks to etch downwards from the middle position of an N-type Inp layer to below the N-type Inp layer, including:

[0024] Using the mask layer and passivation layer as masks, the N-type Inp layer is etched downwards to the interior of the substrate at the middle position.

[0025] The above technical solution has the following advantages: using the mask layer and passivation layer as a mask, the N-type Inp layer is etched downwards to the interior of the substrate at the middle position, so as to determine whether the middle position of the N-type Inp layer is etched to the bottom of the N-type Inp layer.

[0026] In some embodiments, a method for fabricating a laser chip is provided, which further includes, before the first element is implanted into the N-type Inp layer at an oblique angle:

[0027] Remove the mask layer and passivation layer, and apply a protective layer;

[0028] The protective layer is photoresist.

[0029] The above technical solution has the following advantages: it removes the mask layer and passivation layer, and coats a protective layer to protect the areas of the chip that do not require ion implantation. The protective layer is photoresist, which is easy to remove, thus exposing the areas of the chip that require ion implantation.

[0030] In some embodiments, a method for fabricating a laser chip is provided, which, after the first element is implanted into the N-type Inp layer at an oblique angle, further includes:

[0031] Remove the protective layer and etch away the contact layer above the P-type Inp layer doped with the first element;

[0032] A first positive electrode is grown on a contact layer above a P-type Inp layer above the first active layer, and a second positive electrode is grown on a contact layer above a P-type Inp layer above the second active layer.

[0033] The above technical solution has the following beneficial effects: The protective layer is removed, and the contact layer above the P-type Inp layer doped with the first element is etched away, so that the contact layer above the P-type Inp layer above the first active layer and the contact layer above the P-type Inp layer above the second active layer are separated. A first positive electrode is grown on the contact layer above the P-type Inp layer above the first active layer, so that the electrical signal received by the first positive electrode can be transmitted sequentially through the contact layer and the P-type Inp layer to the first active layer; a second positive electrode is grown on the contact layer above the P-type Inp layer above the second active layer, so that the electrical signal received by the second positive electrode can be transmitted sequentially through the contact layer and the P-type Inp layer to the second active layer.

[0034] In some embodiments, a laser chip is provided, comprising:

[0035] Substrate;

[0036] A first N-type Inp layer is located above the substrate;

[0037] A first electrically insulating layer is located above the substrate, with one end connected to the first N-type Inp layer; wherein the first electrically insulating layer is an N-type Inp layer doped with a first element;

[0038] The second N-type Inp layer is located above the substrate, with one end connected to the other end of the first electrically isolated layer;

[0039] The first active layer is located above the first N-type Inp layer;

[0040] A conductive layer is located above the first electrically isolated layer, with one end connected to the first active layer;

[0041] The second active layer is located above the second N-type Inp layer, and one end is connected to the other end of the conductive layer.

[0042] The first P-type Inp layer is located above the first active layer;

[0043] The second electrical isolation layer is located above the conductive layer, and one end is connected to the first P-type Inp layer; the second electrical isolation layer is a P-type Inp layer doped with the first element;

[0044] The second P-type Inp layer is located above the second active layer, and one end is connected to the other end of the second electrical isolation layer.

[0045] The contact layer is located above the first P-type Inp layer, the second electrical isolation layer, and the second P-type Inp layer.

[0046] The above technical solution has the following beneficial effects: A first N-type Inp layer, a first electrically isolated layer, and a second N-type Inp layer are disposed above the substrate from left to right. One end of the first electrically isolated layer is connected to the first N-type Inp layer, and the other end is connected to the second N-type Inp layer. The first electrically isolated layer is an N-type Inp layer doped with a first element. The first element forms deep-level defects in the N-type Inp layer, preventing charge carriers from passing through it. A first active layer is disposed above the first N-type Inp layer, emitting light. A conductive layer is disposed above the first electrically isolated layer, with one end connected to the first active layer to conduct the light emitted by the first active layer. A second active layer is disposed above the second N-type Inp layer, with one end connected to the other end of the conductive layer, so that the second active layer receives and modulates the light transmitted by the conductive layer. A first P-type Inp layer is disposed above the first active layer. The first P-type Inp layer and the first N-type Inp layer form a PN junction, enabling the first active layer to emit light. A second electrically isolated layer is disposed above the conductive layer, with one end of the second electrically isolated layer connected to one end of the first P-type Inp layer. A second P-type Inp layer is disposed above the second active layer, with one end of the second P-type Inp layer connected to the other end of the second electrically isolated layer. The second electrically isolated layer is a P-type Inp layer doped with a first element, which forms deep-level defects in the P-type Inp layer, preventing charge carriers from passing through the second electrically isolated layer. The second P-type Inp layer and the second N-type Inp layer form a PN junction, enabling the second active layer to modulate light. Contact layers are disposed above the first P-type Inp layer, the second electrically isolated layer, and the second P-type Inp layer to facilitate the transmission of received electrical signals to the first P-type Inp layer, the second electrically isolated layer, and the second P-type Inp layer.

[0047] In some embodiments, a laser chip is provided, wherein the contact layer includes:

[0048] The first contact layer is located above the first P-type Inp layer and is connected to the first P-type Inp layer; a first positive electrode is disposed above the first contact layer and is connected to the first contact layer.

[0049] The second contact layer is located above the second P-type Inp layer and is connected to the second P-type Inp layer; a second positive electrode is disposed above the second contact layer and is connected to the second contact layer; the second contact layer is not connected to the first contact layer, and the first positive electrode is not connected to the second positive electrode.

[0050] The above technical solution has the following beneficial effects: The contact layer includes a first contact layer and a second contact layer. The first contact layer is located above and connected to the first P-type Inp layer. The second contact layer is located above and connected to the second P-type Inp layer. The first contact layer and the second contact layer are not connected to avoid crosstalk between the electrical signals received by the first contact layer and the electrical signals received by the second contact layer. A first positive electrode is disposed above the first contact layer and is connected to the first contact layer so that the electrical signal received by the first positive electrode is transmitted to the first P-type Inp layer through the first contact layer. A second positive electrode is disposed above the second contact layer and is connected to the second contact layer so that the electrical signal received by the second positive electrode is transmitted to the second P-type Inp layer through the second contact layer. The first positive electrode and the second positive electrode are not connected to avoid crosstalk between the electrical signals received by the first positive electrode and the electrical signals received by the second positive electrode. Attached Figure Description

[0051] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a partial structural diagram of an optical communication system according to some embodiments;

[0053] Figure 2 This is a partial structural diagram of a host computer according to some embodiments;

[0054] Figure 3 This is a structural diagram of an optical module according to some embodiments;

[0055] Figure 4 An exploded view of an optical module according to some embodiments;

[0056] Figure 5 This is an assembly diagram of an optical transceiver and an optical fiber adapter according to some embodiments;

[0057] Figure 6 This is a structural diagram of a light-emitting component according to some embodiments;

[0058] Figure 7 This is a cross-sectional view of a light-emitting component provided according to some embodiments;

[0059] Figure 8 This is a structural diagram of a laser chip according to some embodiments;

[0060] Figure 9 This is a cross-sectional view of a laser chip along an x-ray according to some embodiments;

[0061] Figure 10 This is a cross-sectional view of a laser chip along the y-line according to some embodiments;

[0062] Figure 11 This is a flowchart illustrating a method for fabricating a laser chip according to some embodiments;

[0063] Figure 12 Provided according to some embodiments Figure 11 A partial cross-sectional view of f in the figure;

[0064] Figure 13 Provided according to some embodiments Figure 11 A partial cross-sectional view of g in the image;

[0065] Figure 14 Provided according to some embodiments Figure 11 A partial cross-sectional view of h in the diagram;

[0066] Figure 15 Provided according to some embodiments Figure 11 A partial cross-sectional view of i in the diagram;

[0067] Figure 16 Provided according to some embodiments Figure 11 A partial cross-sectional view of j in the diagram;

[0068] Figure 17 Provided according to some embodiments Figure 11 A local cross-sectional view of k in the diagram;

[0069] Figure 18 Provided according to some embodiments Figure 11 A partial cross-sectional view of l in the image;

[0070] Figure 19 Provided according to some embodiments Figure 11 A partial cross-sectional view of m in the diagram;

[0071] Figure 20 Provided according to some embodiments Figure 11 A local cross-sectional view of n in the diagram. Detailed Implementation

[0072] The embodiments of this disclosure will now be described clearly and in detail with reference to the accompanying drawings. However, the described embodiments are merely some, and not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0073] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and inclusive, meaning "including, but not limited to"; the terms "first" and "second" should not be construed as indicating or implying relative importance or indicating an upper limit on the number; the term "multiple" means two or more; the term "connection" should be interpreted broadly, for example, "connection" can be a fixed connection, a detachable connection, or an integral part, and can be a direct connection or an indirect connection through an intermediate medium; the use of the terms "applicable to" or "configured to" implies open and inclusive language, which does not exclude applicability to or configuration to devices performing additional tasks or steps; descriptions such as "parallel," "perpendicular," "identical," "consistent," and "aligned" are not limited to absolute mathematical theoretical relationships, but also include acceptable error ranges arising in practice, and differences based on the same design concept but due to manufacturing reasons.

[0074] In optical communication technology, to establish information transmission between information processing devices, information is loaded onto light, and the speed of light propagation is used to transmit the information. This light carrying information is called an optical signal. When optical signals are transmitted in optical information transmission equipment, optical power loss can be reduced, enabling long-distance transmission of optical signals. At the same time, the cost of optical information transmission equipment such as optical fibers is lower than that of electrical information transmission equipment such as copper wires. Therefore, optical communication technology can achieve high-speed, long-distance, and low-cost information transmission.

[0075] Information processing equipment typically includes optical network units (ONUs), gateways, routers, switches, mobile phones, computers, servers, tablets, televisions, etc., while optical information transmission equipment typically includes optical fibers and optical waveguides. Information processing equipment can only recognize and process electrical signals, while optical communication technology uses optical signals for transmission, requiring optical modules to convert between optical and electrical signals.

[0076] An optical module enables the conversion between optical signals and electrical signals between information processing equipment and optical information transmission equipment. In some embodiments, at least one of the optical signal input or output terminals of the optical module is connected to an optical fiber, and at least one of the electrical signal input or output terminals of the optical module is connected to an optical network terminal. A first optical signal from the optical fiber is transmitted to the optical module, which converts the first optical signal into a first electrical signal and transmits the first electrical signal to the optical network terminal. A second electrical signal from the optical network terminal is transmitted to the optical module, which converts the second electrical signal into a second optical signal and transmits the second optical signal to the optical fiber.

[0077] Since multiple information processing devices can transmit information via electrical signals, at least one of these devices needs to be directly connected to the optical module, rather than all of them. Here, the information processing device directly connected to the optical module is also referred to as the host computer of the optical module. Furthermore, the optical signal input or output terminal of the optical module is called the optical port, and the electrical signal input or output terminal is called the electrical port.

[0078] Figure 1 This is a partial structural diagram of an optical communication system according to some embodiments. Figure 1 As shown, the optical communication system mainly includes a remote information processing device 1000, a local information processing device 2000, a host computer 100 for optical modules, an optical module 200, an optical fiber 101, and a network cable 103. Among them, the optical fiber 101 is an optical information transmission device, and the network cable 103 is an electrical information transmission device.

[0079] In some embodiments, one end of the optical fiber 101 extends toward the remote information processing device 1000, and the other end of the optical fiber 101 is connected to the optical module 200 through the optical port of the optical module 200. The optical signal can undergo total internal reflection in the optical fiber 101, and the propagation of the optical signal in the direction of total internal reflection can almost maintain the original optical power. The optical signal undergoes multiple total internal reflections in the optical fiber 101 to transmit the optical signal from the remote information processing device 1000 to the optical module 200, or to transmit the optical signal from the optical module 200 to the remote information processing device 1000, thereby realizing long-distance information transmission based on low power loss.

[0080] The optical communication system includes one or more optical fibers 101. In some embodiments, the optical fiber 101 is detachably connected to the optical module 200; in some embodiments, the optical fiber 101 is non-detachably connected to the optical module 200.

[0081] The host computer 100 is configured to provide data signals to the optical module 200, or receive data signals from the optical module 200, or monitor or control the working status of the optical module 200.

[0082] The host computer 100 includes a housing for accommodating the optical module 200, and an optical module interface 102 disposed on the housing. The optical module 200 is inserted into the housing through the optical module interface 102 to establish a unidirectional or bidirectional electrical signal connection between the host computer 100 and the optical module 200.

[0083] The host computer 100 also includes an external power interface that can connect to an electrical signal network. In some embodiments, the external power interface includes a Universal Serial Bus (USB) interface or a network cable interface 104. The network cable interface 104 is configured to connect a network cable 103 to establish a unidirectional or bidirectional electrical signal connection between the host computer 100 and the network cable 103.

[0084] One end of the network cable 103 is connected to the local information processing device 2000, and the other end is connected to the host computer 100, so as to establish an electrical signal connection between the local information processing device 2000 and the host computer 100 through the network cable 103. In some embodiments, a third electrical signal emitted by the local information processing device 2000 is transmitted to the host computer 100 through the network cable 103. The host computer 100 generates a second electrical signal based on the third electrical signal. The second electrical signal from the host computer 100 is transmitted to the optical module 200. The optical module 200 converts the second electrical signal into a second optical signal and transmits the second optical signal to the optical fiber 101. The second optical signal is transmitted in the optical fiber 101 to the remote information processing device 1000.

[0085] In some embodiments, a first optical signal from a remote information processing device 1000 is transmitted through an optical fiber 101, and the first optical signal from the optical fiber 101 is transmitted to an optical module 200. The optical module 200 converts the first optical signal into a first electrical signal, and transmits the first electrical signal to a host computer 100. The host computer 100 generates a fourth electrical signal based on the first electrical signal and transmits the fourth electrical signal to a local information processing device 2000.

[0086] In some embodiments, the optical module is a tool for converting optical signals to electrical signals. During the conversion process, the information does not change, but the encoding or decoding method of the information changes.

[0087] In addition to optical network terminals, the host computer 100 also includes optical line terminals (OLTs), optical network equipment (ONTs), or data center servers.

[0088] Figure 2 This is a partial structural diagram of a host computer according to some embodiments. To clearly show the connection relationship between the optical module 200 and the host computer 100, Figure 2 Only the structure of the host computer 100 related to the optical module 200 is shown. For example... Figure 2As shown, in some embodiments, the host computer 100 further includes a PCB circuit board 105 disposed in the receiving cavity, and a cage 106 disposed on the surface of the PCB circuit board 105; the optical module 200 is inserted into the cage 106 and fixed by the cage 106.

[0089] In some embodiments, a heat sink 107 is provided on the cage 106 to dissipate heat for the optical module; in some embodiments, the heat sink 107 has protruding structures such as fins to increase the heat dissipation area.

[0090] In some embodiments, an electrical connector is provided inside the cage 106, which is configured to connect to the electrical port of the optical module 200.

[0091] In some embodiments, the optical module 200 is inserted into the cage 106 of the host computer 100, and the cage 106 fixes the optical module 200. The heat generated by the optical module 200 is conducted to the cage 106 and then diffused through the heat sink 107.

[0092] In some embodiments, the optical module 200 is inserted into the cage 106 of the host computer 100, and the electrical port of the optical module 200 is connected to the electrical connector inside the cage 106, thereby establishing an electrical signal connection between the optical module 200 and the host computer 100.

[0093] In some embodiments, the optical port of the optical module 200 is connected to the optical fiber 101, thereby enabling the optical module 200 to establish an optical signal connection with the optical fiber 101.

[0094] Figure 3 This is a structural diagram of an optical module according to some embodiments. Figure 4 This is an exploded view of an optical module according to some embodiments. Figure 3 and Figure 4 As shown, in some embodiments, the optical module 200 includes a shell, which comprises an upper shell 201 and a lower shell 202. The upper shell 201 covers the lower shell 202, forming two openings 204 and 205, one of which is an electrical port and the other is an optical port. In some embodiments, the shell forms an opening that serves as both an electrical port and an optical port.

[0095] In some embodiments, the upper housing 201 and the lower housing 202 are made of metal materials, which facilitates electromagnetic shielding and heat dissipation.

[0096] The assembly method of combining the upper housing 201 and the lower housing 202 facilitates the installation of the circuit board 300, the light emitting component 400, the light receiving component 500, etc. into the housing. The upper housing 201 and the lower housing 202 can encapsulate and protect the above-mentioned devices.

[0097] The direction of the line connecting the two openings 204 and 205 can be consistent with or inconsistent with the length direction of the optical module 200. For example, opening 204 is located at the end of the optical module 200. Figure 3 The opening 205 is also located at the end of the optical module 200 (right end). Figure 3 (The left end). Alternatively, opening 204 is located at the end of optical module 200, while opening 205 is located on the side of optical module 200.

[0098] In some embodiments, the lower housing 202 includes a base plate 2021 and two lower side plates 2022 located on both sides of the base plate 2021 and perpendicular to the base plate 2021; the upper housing 201 includes a cover plate 2011, which covers the two lower side plates 2022 of the lower housing 202 to form the aforementioned housing.

[0099] In some embodiments, the lower housing 202 includes a base plate 2021 and two lower side plates 2022 located on both sides of the base plate 2021 and perpendicular to the base plate 2021; the upper housing 201 includes a cover plate 2011 and two upper side plates located on both sides of the cover plate 2011 and perpendicular to the cover plate 2011. The two upper side plates and the two lower side plates 2022 are combined to realize that the upper housing 201 covers the lower housing 202.

[0100] like Figure 3 and Figure 4 As shown, in some embodiments, the optical module includes a circuit board 300 disposed within a housing. The circuit board 300 includes circuit traces, electronic components, and chips, etc. The electronic components and chips are connected according to the circuit design through the circuit traces to realize functions such as power supply, electrical signal transmission, and grounding. Electronic components may include, for example, capacitors, resistors, transistors, and metal-oxide-semiconductor field-effect transistors (MOSFETs). Chips may include microcontroller units (MCUs), laser driver chips, transimpedance amplifiers (TIAs), limiting amplifiers (LAs), clock and data recovery chips (CDRs), power management chips, and digital signal processing (DSP) chips.

[0101] In some embodiments, the circuit board includes a rigid circuit board, which, due to its relatively rigid material, can also serve a load-bearing function, such as being able to stably support the aforementioned electronic components and chips; the rigid circuit board can also be inserted into an electrical connector in the cage 106 of the host computer 100.

[0102] In some embodiments, the circuit board further includes a flexible circuit board, which can be used independently or in conjunction with a rigid circuit board.

[0103] In some embodiments, the circuit board further includes gold fingers formed on its end surfaces, the gold fingers consisting of a plurality of independent pins. (Circuit board 300VS circuit board; reference numerals are strongly indicative and should be consistent with the form shown in the figures. If the concept has more embodiments, it is not recommended to introduce reference numerals; in relation to the attached figures...) Figure 1 In the embodiments described herein, it is recommended to introduce reference numerals.

[0104] In some implementations, the gold fingers are located on the surface of one side of the circuit board 300 (e.g., Figure 4 (as shown on the upper surface); In some implementations, the gold fingers are set on the upper and lower surfaces of the circuit board 300 to provide a greater number of pins, thereby adapting to situations where the number of pins is large.

[0105] In some implementations, the gold fingers of the circuit board extend from the electrical port and are inserted into the electrical connector of the host computer 100; the circuit board is inserted into the cage 106, and the gold fingers are connected to the electrical connector inside the cage 106. The gold fingers are configured to establish an electrical connection with the host computer, enabling electrical connection functions such as power supply, grounding, two-wire synchronous serial (Inter-Integrated Circuit, I2C) signal transmission, and data signal transmission.

[0106] In some embodiments, the optical module 200 further includes an unlocking component 600 located outside its housing. The unlocking component 600 is configured to establish a fixed connection between the optical module 200 and the host computer, or to release the fixed connection between the optical module 200 and the host computer.

[0107] For example, the unlocking component 600 is located on the outside of the two lower side plates 2022 of the lower housing 202, and includes a locking component that matches the cage 106 of the host computer 100. When the optical module 200 is inserted into the cage 106, the locking component of the unlocking component 600 fixes the optical module 200 in the cage 106; when the unlocking component 600 is pulled, the locking component of the unlocking component 600 moves accordingly, thereby changing the connection relationship between the locking component and the host computer, so as to release the fixation between the optical module 200 and the host computer, thereby allowing the optical module 200 to be pulled out of the cage 106.

[0108] In some embodiments, the optical module includes a light emitting component 400, such as... Figure 3 and Figure 4 As shown. The light emitting component 400 is used to emit a second light signal.

[0109] In some embodiments, the optical module includes an optical receiving component 500, such as... Figure 3 and Figure 4 As shown, the optical receiving unit 500 is used to receive the first optical signal and convert the first optical signal into an electrical signal.

[0110] In some embodiments, at least one of the light emitting component 400 or the light receiving component 500 is located on the side of the circuit board 300 away from the gold fingers.

[0111] In some embodiments, the light emitting component 400 and the light receiving component 500 are physically separated from the circuit board 300, and then electrically connected to the circuit board 300 through corresponding flexible circuit boards or electrical connectors.

[0112] In some embodiments, at least one of the light emitting component or the light receiving component may be directly disposed on the circuit board 300. For example, at least one of the light emitting component or the light receiving component may be disposed on the surface of the circuit board 300 or the side of the circuit board 300.

[0113] Figure 5 This is an assembly diagram of an optical transceiver and fiber optic adapter according to some embodiments. Figure 5 As shown, in some embodiments, the first end of the light receiving component 500 may be connected to the light emitting component 400 so that the light receiving component 500 can receive the second light signal emitted by the light emitting component 400.

[0114] like Figure 5 As shown, in some embodiments, an optical fiber adapter 700 may be disposed within the housing of the optical module 200. The optical fiber adapter 700 may be connected to the second end of the optical receiver 500 so that an externally input first optical signal is input to the optical receiver 500 through the optical fiber adapter 700.

[0115] In some embodiments, the first end and the second end of the light receiving component 500 may be disposed at both ends of the light receiving component 500 along the length direction of the light receiving component 500.

[0116] The first end of the optical receiver 500 can be connected to the optical transmitter 400, and the second end of the optical receiver 500 can be connected to the fiber optic adapter 700. The light output direction of the optical transmitter 400 faces the fiber optic adapter 700, so that the transmitted optical signal emitted by the optical transmitter 400 is first transmitted to the optical receiver 500, then transmitted through the optical receiver 500 to the fiber optic adapter 700, and finally output through the fiber optic adapter 700. The optical receiver 500 and the optical transmitter 400 share the fiber optic adapter 700, and thus the uplink and downlink optical signals of the optical module share the same optical fiber 101.

[0117] like Figure 5 As shown, in some embodiments, the optical receiving component 500 may include a first cavity 510. One end of the first cavity 510 may be connected to the optical transmitting component 400. The other end of the first cavity 510 may be connected to the fiber optic adapter 700, so that the first cavity 510 can receive a first optical signal input from the fiber optic adapter 700 (i.e., receive optical signal). One end of the first cavity 510 may be connected to the optical transmitting component 400, and the other end of the first cavity 510 may be connected to one end of the fiber optic adapter 700, so that the transmitted optical signal emitted by the optical transmitting component 400 is first transmitted to the first cavity 510, then transmitted through the first cavity 510 to the fiber optic adapter 700, and finally output through the fiber optic adapter 700.

[0118] like Figure 5 As shown, in some embodiments, the optical receiving component 500 may include an optical receiving assembly 520. The optical receiving assembly 520 may be connected to the first cavity 510 so that an externally input first optical signal is input to the first cavity 510 through the fiber optic adapter 700, and then transmitted to the optical receiving assembly 520 through the first cavity 510.

[0119] like Figure 5 As shown, in some embodiments, the first cavity 510 has a first light-transmitting hole. An optical fiber adapter 700 can be connected to the first light-transmitting hole to connect the optical fiber adapter 700 to the first cavity 510.

[0120] like Figure 5 As shown, in some embodiments, the first cavity 510 has a second light-transmitting aperture. The light-receiving component 520 can be connected to the second light-transmitting aperture to connect the light-receiving component 520 to the first cavity 510.

[0121] like Figure 5 As shown, in some embodiments, the first cavity 510 has a third light-transmitting aperture. The light-emitting component 400 can be connected to the third light-transmitting aperture to connect the light-emitting component 400 to the first cavity 510.

[0122] Figure 6 This is a structural diagram of a light emitting component provided according to some embodiments. Figure 7 This is a cross-sectional view of a light-emitting component provided according to some embodiments. For example... Figure 6 and Figure 7 As shown, in some embodiments, the light emitting component 400 may include a socket 410. A laser chip 450 is disposed on the top surface of the socket 410, and the laser chip 450 emits light signals.

[0123] In some embodiments, the light emitting component 400 may include a cap 420. The cap 420 covers the base 410.

[0124] In some embodiments, the light emitting component 400 may include a lens 440. The lens 440 is used to collimate the light signal emitted by the laser chip 450, so that the light signal is collimated from divergent light to parallel light, thereby reducing transmission loss.

[0125] In some embodiments, the light emitting component 400 may include a pin 430. The pin 430 extends upward from the bottom of the socket 410 until it extends beyond the top of the socket 410. One end of the pin 430 is connected to the circuit board 300 via a flexible circuit board to achieve an electrical connection between the pin 430 and the circuit board 300. The other end of the pin 430 extends beyond the top of the socket 410 and is wire-connected to the pad where the laser chip 450 is located to achieve an electrical connection between the pin and the laser chip 450, thereby transmitting electrical signals from the circuit board 300 to the pad where the laser chip 450 is located via the pin 430.

[0126] Figure 8 This is a structural diagram of a laser chip according to some embodiments. Figure 9 This is a cross-sectional view of a laser chip along an x-ray according to some embodiments. Figure 10 This is a cross-sectional view along the y-line of a laser chip according to some embodiments. Figure 8 , Figure 9 and Figure 10 As shown, in some embodiments, the laser chip 450 may include a substrate 451.

[0127] In some embodiments, an N-type InP layer 452 may be disposed above the substrate 451. The N-type InP layer 452 is an N-type doped semiconductor, such as generally doped Si or S.

[0128] In some embodiments, a first electrical isolation layer 452a may be disposed above the substrate 451. The first electrical isolation layer 452a can separate the N-type InP layer 452, so that the N-type InP layer 452 is divided into a first N-type InP layer 4521 and a second N-type InP layer 4522. That is, one end of the first electrical isolation layer 452a is connected to the first N-type InP layer 4521, and the other end of the first electrical isolation layer 452a is connected to the second N-type InP layer 4522.

[0129] The first electrically isolated layer 452a is an N-type InP layer doped with a first element. The first element forms deep-level defects in the N-type InP layer 452, causing carrier recombination in the first electrically isolated layer 452a. This results in a very high resistivity of the first electrically isolated layer 452a, preventing carriers from passing through it to enter the first N-type InP layer 4521 or the second N-type InP layer 4522. For example, the first element can be boron, helium, or iron. The first electrically isolated layer 452a can be formed by ion implantation.

[0130] In some implementations, a first active layer 453a may be disposed above the N-type InP layer 452. The first active layer 453a may be located above the first N-type InP layer 4521 and be in contact with the first N-type InP layer 4521. The first active layer 453a may emit light of a specific wavelength.

[0131] The first active layer 453a can be a first quantum well layer. The first quantum well layer can be disposed above the first N-type Inp layer 4521 and connected to the surface of the first N-type Inp layer 4521. The first quantum well layer is generally made of InGaAsP or InAlGaAs multilayer quantum well material to enable it to emit light.

[0132] The first active layer 453a may include a grating layer. The grating layer may be disposed above and connected to the first quantum well layer. The grating layer is used to select light of a specific wavelength from the light emitted from the first quantum well layer. The grating layer may be a Bragg grating. By changing the current injected into the grating layer, the effective refractive index of the grating layer can be changed, thereby changing the resonant lasing wavelength of the grating layer, thus achieving wavelength selection.

[0133] In some embodiments, a second active layer 453b may be disposed above the N-type InP layer 452. The second active layer 453b may be located above the second N-type InP layer 4522 and be in contact with the second N-type InP layer 4522. The second active layer 453b may absorb light.

[0134] The second active layer 453b can be a second quantum well layer. The second quantum well layer can be disposed above the second N-type Inp layer 4522 and connected to the surface of the second N-type Inp layer. The second quantum well layer is generally made of InGaAsP or InAlGaAs multilayer quantum well material to absorb light and achieve light modulation. A quantum well is formed in a normal semiconductor material by inserting a narrow bandgap material between two wide bandgap materials to increase the bandgap and thus restrict the movement of electrons and holes.

[0135] In some embodiments, a conductive layer 453 may be disposed above the first electrical isolation layer 452a and may be in contact with the conductive layer 453. One end of the conductive layer 453 may be connected to the first active layer 453a. The other end of the conductive layer 453 may be connected to the second active layer 453b. The conductive layer 453 can transmit light. The material of the conductive layer 453 is generally indium gallium arsenide phosphide.

[0136] One end of the conductive layer 453 can be connected to the first active layer 453a, and the other end of the conductive layer 453 can be connected to the second active layer 453b, so that the light emitted by the first active layer 453a is transmitted through the conductive layer 453 to the second active layer 453b and absorbed by the second active layer 453b.

[0137] In some embodiments, a P-type Inp layer 454 may be disposed above both the first active layer 453a and the second active layer 453b, and contacted and connected to the first active layer 453a and the second active layer 453b. The P-type Inp layer 454 is a P-type doped semiconductor, such as a doped divalent element. For example, the P-type Inp layer 454 may include a first P-type Inp layer 4541 and a second P-type Inp layer 4542, where the first P-type Inp layer 4541 may be disposed above the first active layer 453a, and the second P-type Inp layer 4542 may be disposed above the second active layer 453b.

[0138] In some embodiments, a second electrical isolation layer 454a may be disposed above the conductive layer 453 and may be in contact with the conductive layer 453. One end of the second electrical isolation layer 454a may be connected to the first P-type Inp layer 4541. The other end of the second electrical isolation layer 454a may be connected to the second P-type Inp layer 4542. The second electrical isolation layer 454a is a P-type Inp layer doped with a first element.

[0139] The first element forms deep-level defects in the P-type Inp layer, causing carrier recombination in the second electrically isolated layer 454a. This results in a high resistivity of the second electrically isolated layer 454a, preventing carriers from entering the first P-type Inp layer 4541 or the second P-type Inp layer 4542. For example, the first element can be boron, zinc, or iron. The second electrically isolated layer 454a can be formed by ion implantation.

[0140] In some embodiments, a contact layer 455 may be disposed above the first P-type Inp layer 4541, the second electrically isolated layer 454a, and the second P-type Inp layer 4542, and the contact layer 455 may be in contact with the first P-type Inp layer 4541, the second electrically isolated layer 454a, and the second P-type Inp layer 4542, so that the contact layer 455 transmits the received electrical signal to the first P-type Inp layer 4541, the second electrically isolated layer 454a, and the second P-type Inp layer 4542. The contact layer 455 may be a highly doped P-type InGaAs material to achieve good ohmic contact with the electrode metal.

[0141] In some embodiments, contact layer 455 may include a first contact layer 4551 and a second contact layer 4552. The first contact layer 4551 may be located above and connected to the first P-type Inp layer 4541. The second contact layer 4552 may be located above and connected to the second P-type Inp layer 4542. The first contact layer 4551 and the second contact layer 4552 are not connected to avoid crosstalk between the electrical signals received by the first contact layer 4551 and the second contact layer 4552.

[0142] In some embodiments, an electrode layer 457 may be disposed above the contact layer 455 and contacted and connected to the electrode layer 457. For example, a first positive electrode 4573 may be disposed above the first contact layer 4551 and contacted and connected to the first positive electrode 4573. A second positive electrode 4576 may be disposed above the second contact layer 4552 and contacted and connected to the second positive electrode 4576.

[0143] The first positive electrode 4573 and the second positive electrode 4576 are not connected to avoid crosstalk between the electrical signals received by the first positive electrode 4573 and the second positive electrode 4576.

[0144] The light-emitting region comprises a substrate 451, a first N-type InP layer 4521, a first active layer 453a, a first P-type InP layer 4541, and a first contact layer 4551. The first P-type InP layer 4541 and the first N-type InP layer 4521 form a PN junction. During PN junction formation, the concentration difference of charge carriers induces diffusion. The result of this diffusion is that the first P-type InP layer 4541 contains holes and negative ions, while the first N-type InP layer 4521 contains electrons and positive ions. Based on the principle of charge, holes are driven downwards into the first quantum well layer, and electrons are driven upwards into the first quantum well layer. Within the first quantum well layer, stimulated emission causes the discrete electron-hole pairs to recombine, generating photons. This effectively converts electrically injected charge carriers into photons and generates gain light. The photons generated by recombination within the first quantum well layer are reflected by the resonant cavity or distributed feedback grating to form positive feedback, thereby generating lasing light.

[0145] The modulation region comprises a substrate 451, a second N-type InP layer 4522, a second active layer 453b, a second P-type InP layer 4542, and a second contact layer 4552. The second P-type InP layer 4542 and the second N-type InP layer 4522 form a PN junction. When light reaches the second quantum well layer, a photovoltaic effect occurs, generating electron-hole pairs. Without an applied electric field, the band gap is greater than the photon's energy, preventing absorption and allowing low-loss transmission. However, as the applied electric field increases, the bandgap tilts, reducing the energy difference between the conduction and valence bands to less than the photon's energy. Light then absorbs photons, generating electron-hole pairs, thus altering the light intensity—i.e., modulating the light. Conversely, when the applied electric field decreases or becomes zero, the bandgap recovers, the band gap widens, and light can pass through the material with low loss, reducing absorption.

[0146] The substrate 451, the first electrical isolation layer 452a, the conductive layer 453, and the second electrical isolation layer 454a constitute the conductive region.

[0147] In some embodiments, the laser chip 450 may include a first support region. The first support region may be located on one side of the light-emitting region. The first support region may house a first positive electrode pad 4571 and a first negative electrode pad 4572. The first positive electrode pad 4571 may be connected to a first positive electrode 4573.

[0148] The first support area may have a first through-hole extending from the top to the first N-type InP layer. A first negative electrode is disposed within the first through-hole, with one end connected to a first negative pad 4572 and the other end connected to the first N-type InP layer. A positive driving current can be applied to the first positive pad 4571, and the first negative pad 4572 can be grounded. The positive driving current sequentially passes through the first positive pad 4571, the first positive electrode 4573, and the contact layer 455 before entering the P-type InP layer 454.

[0149] In some embodiments, the laser chip 450 may include a second support region. The second support region may be located on one side of the modulation region. The second support region may house a second positive electrode pad 4574 and a second negative electrode pad 4575. The second positive electrode pad 4574 may be connected to a second positive electrode 4576.

[0150] The second support area may have a second through-hole, which extends from the top to the second N-type InP layer. A second negative electrode is disposed within the second through-hole, with one end of the second negative electrode connected to the second negative electrode pad 4575 and the other end connected to the second N-type InP layer.

[0151] The second positive pad 4574 can be used to add a first high-frequency signal, and the second negative pad 4575 can be used to add a second high-frequency signal. The first high-frequency signal can pass through the second positive pad 4574, the second positive electrode 4576, and the contact layer 455 in sequence to enter the P-type Inp layer 454. The second high-frequency signal can pass through the second negative pad 4575 and the second negative electrode in sequence to enter the N-type Inp layer 452.

[0152] Both the first high-frequency signal and the second high-frequency signal are radio frequency signals. The first high-frequency signal and the second high-frequency signal have the same amplitude, the same frequency, and opposite phase, so as to form a differential driving form to drive the modulation area to work.

[0153] In some embodiments, the laser chip 450 may include a first trench 461. The first trench 461 may be located between the light-emitting region and the first support region. The first trench 461 may extend from the top to above the first active layer 453a.

[0154] In some embodiments, the laser chip 450 may include a second trench 462. The second trench 462 may be located between the modulation region and the second support region. The second trench 462 may extend from the top to above the second N-type Inp layer.

[0155] In some embodiments, a third trench 463 may be provided between the first trench 461 and the second trench 462. The third trench 463 may extend from the top to below the second N-type Inp layer, that is, above the substrate 451. The third trench 463 may also include the area between the first support region and the second support region.

[0156] In some embodiments, the laser chip 450 may include a passivation layer 456 to protect the laser chip 450. The passivation layer 456 may be disposed at the bottom and sides of the first trench 461 and extend to a first support region on the other side of the first trench 461. The passivation layer 456 may be disposed at the bottom and sides of the second trench 462 and extend to a second support region on the other side of the second trench 462. The passivation layer 456 may be disposed at the bottom and sides of a third trench. The passivation layer 456 may be disposed between the first positive electrode 4573 and the second positive electrode 4576.

[0157] The first positive electrode pad 4571 can be disposed above the passivation layer 456 above the first support region. The first negative electrode pad 4572 can be disposed above the passivation layer 456 above the first support region, and is in contact with the first N-type Inp layer through the first metal in the first through hole.

[0158] The second positive electrode pad 4574 can be disposed above the passivation layer 456 above the second support region. The second negative electrode pad 4575 can be disposed above the passivation layer 456 above the second support region, and is in contact with the second N-type Inp layer through the second metal in the second through hole.

[0159] In some embodiments, the first electrically insulating layer 452a is formed by ion implantation. However, the ion implantation depth is limited by the maximum energy of the ion implantation device. For conventional InP-based lasers, the thickness from the top surface to the semi-insulating substrate is >4 μm. If the conventional top-implantation method is used, the ion implantation depth of the first electrically insulating layer 452a cannot meet the requirements.

[0160] To address this issue, in some embodiments, the area requiring ion implantation (i.e., the N-type Inp layer) is first exposed by two etching processes, and then ions are implanted into the N-type Inp layer by tilted ion implantation, thereby transforming the N-type Inp layer into a first electrically isolated layer 452a. The ion implantation depth of the first electrically isolated layer 452a meets the requirements.

[0161] Figure 11 This is a flowchart illustrating a method for fabricating a laser chip according to some embodiments. Figure 11 As shown, in some embodiments, the method for fabricating the laser chip includes:

[0162] S100: An N-type Inp layer is grown above the substrate. A first active layer, a conductive layer, and a second active layer are grown above the N-type Inp layer. One end of the conductive layer is connected to the first active layer, and the other end of the conductive layer is connected to the second active layer. A P-type Inp layer, a contact layer, and a mask layer are grown sequentially above the first active layer, the conductive layer, and the second active layer.

[0163] S101: An N-type Inp layer, a first quantum well layer, and a grating layer are sequentially grown on the substrate.

[0164] An N-type Inp layer, a first quantum well layer, and a grating layer are sequentially grown on a substrate using MOCVD (metal-organic chemical vapor deposition) epitaxial growth technology to form a substrate wafer for primary epitaxy. At this stage, the grating layer does not have a grating pattern.

[0165] A protective layer is uniformly coated on a substrate wafer. A grating pattern is fabricated on the protective layer using holographic exposure. The grating pattern is then transferred from the protective layer to the grating layer using wet etching or dry etching. Finally, the protective layer on the substrate wafer surface is removed, forming a grating layer with the grating pattern. The structure obtained after step S101 is as follows: Figure 11 As shown in 'a'. Figure 11As shown in Figure 'a', the first position of the grating layer has a grating pattern, while the second and third positions of the grating layer do not. One end of the second position can be connected to the first position, and the other end of the second position can be connected to the third position.

[0166] The first quantum well layer and the grating layer constitute the first active layer, which can emit light of a specific wavelength so that the laser chip can emit light of a specific wavelength.

[0167] S102: Etch downwards at the second and third positions of the grating layer to below the first quantum well layer.

[0168] Using a wet etching process, the second and third positions of the grating layer are etched downwards to below the first quantum well layer, exposing the second and third positions of the N-type Inp layer. The structure obtained after S102 is as follows. Figure 11 As shown in b in the figure.

[0169] S103: Conductive layers are grown at the second and third positions of the N-type Inp layer.

[0170] Conductive layers are grown at the second and third positions of the N-type Inp layer using MOCVD epitaxy. These conductive layers can conduct light. The structure obtained after S103 is shown below. Figure 11 As shown in c in the figure.

[0171] S104: Etch down to the N-type Inp layer at the third position of the conductive layer.

[0172] A wet etching process is used to etch down to the N-type Inp layer at the third position of the conductive layer, exposing the third position of the N-type Inp layer. The structure obtained after S104 is as follows. Figure 11 As shown in d.

[0173] S105: A second quantum well layer is grown at the third position of the N-type Inp layer.

[0174] A second quantum well layer is epitaxially grown at the third position of the N-type Inp layer using MOCVD. This second quantum well layer is the second active layer. The second active layer can modulate light, enabling the laser chip to be modulated. The structure obtained after step S105 is shown below. Figure 11 As shown in e.

[0175] S106: A P-type Inp layer is grown above the first active layer, the conductive layer, and the second active layer, and a contact layer is grown above the P-type Inp layer.

[0176] A P-type Inp layer is epitaxially grown over the first active layer, the conductive layer, and the second active layer using MOCVD. The P-type Inp layer and the N-type Inp layer form a PN junction, enabling the first active layer to emit light of a specific wavelength and the second active layer to modulate the light.

[0177] A contact layer is grown above the P-type Inp layer using MOCVD, allowing electrical signals to be transmitted to the P-type Inp layer through the contact layer. The structure obtained after step S106 is as follows: Figure 11 As shown in f in the figure.

[0178] like Figure 11 As shown in f, an N-type Inp layer is disposed above the substrate. A first active layer, a conductive layer, and a second active layer are disposed sequentially above the N-type Inp layer. The first active layer, the conductive layer, and the second active layer are located in the same layer. One end of the conductive layer is connected to the first active layer, and the other end of the conductive layer is connected to the second active layer. A P-type Inp layer is disposed above the first active layer, the conductive layer, and the second active layer. A contact layer is disposed above the P-type Inp layer.

[0179] The first active layer, along with the corresponding N-type Inp layer, P-type Inp layer, and contact layer, forms the light-emitting preset region. The conductive layer, along with the corresponding N-type Inp layer, P-type Inp layer, and contact layer, forms the conductive preset region. The second active layer, along with the corresponding N-type Inp layer, P-type Inp layer, and contact layer, forms the modulation preset region.

[0180] The first position is set between each layer of the laser chip, the second position is set between each layer of the laser chip, and the third position is set between each layer of the laser chip.

[0181] Figure 12 Provided according to some embodiments Figure 11 A partial cross-sectional view of f in the figure. Figure 12 for Figure 11 The cross-sectional view of the conduction pre-set region of f in the diagram. (See diagram below.) Figure 11 and Figure 12 As shown, the conductive pre-placement area is provided with a substrate 451, an N-type Inp layer 452, a conductive layer 453, a P-type Inp layer 454 and a contact layer 455 from bottom to top.

[0182] S107: A mask layer is grown above the contact layer.

[0183] The mask layer 470 can be a Si3N4 mask. The Si3N4 mask is epitaxially grown over the contact layer 455 using MOCVD. The width of the mask layer 470 is smaller than the width of the contact layer 455. The structure obtained after step S107 is as follows... Figure 11 As shown in g in the figure.

[0184] Figure 13Provided according to some embodiments Figure 11 A partial cross-sectional view of g in the diagram. Figure 13 for Figure 11 The cross-sectional view of the conduction pre-set region of g in the diagram. (See diagram below.) Figure 11 and Figure 13 As shown, the conductive pre-placement area is provided with a substrate 451, an N-type Inp layer 452, a conductive layer 453, a P-type Inp layer 454, a contact layer 455, and a mask layer 470 from bottom to top. The widths of the substrate 451, the N-type Inp layer 452, the conductive layer 453, the P-type Inp layer 454, and the contact layer 455 can be greater than the width of the mask layer 470.

[0185] The first chip structure was formed by etching using mask layer 470 as a mask.

[0186] S200: Using the mask layer as a mask, etch downwards at the first position of the contact layer to above the first active layer, at the second position of the contact layer to below the conductive layer, and at the third position of the contact layer to below the second active layer.

[0187] Using a mask layer as a mask, an ICP dry etching process is used to etch downwards from the first position of the contact layer to above the first active layer to form a light-emitting region. That is, using a mask layer as a mask, an ICP dry etching process is used to etch downwards from the light-emitting pre-position to above the first active layer to form a light-emitting region. At the second position of the contact layer, the process is etched downwards to below the conductive layer. At the third position of the contact layer, the process is etched downwards to below the second active layer to form a modulation region. That is, using a mask layer as a mask, an ICP dry etching process is used to etch downwards from the modulation pre-position to below the second active layer to form a modulation region, thereby forming the first chip structure.

[0188] S201: Using the mask layer as a mask, first etch downwards at the first position of the contact layer to above the first active layer to form the light-emitting area; then etch downwards at the third position of the contact layer to below the second active layer; then etch downwards at the second position of the contact layer to below the N-type Inp layer.

[0189] A first trench 461 in the light-emitting region extends from the top to above the active layer, a second trench 462 in the modulation region extends from the top to above the second N-type Inp layer, and a third trench 463 between the first trench 461 and the second trench 462 extends from the top to below the second N-type Inp layer. The mask layer may include a first sub-mask layer, a second sub-mask layer, and a third sub-mask layer. The first sub-mask layer serves as a mask for etching the first position of the contact layer, the second sub-mask layer serves as a mask for etching the second position of the contact layer, and the third sub-mask layer serves as a mask for etching the third position of the contact layer. Etching downwards using the mask layer as a mask can first block the second and third positions of the contact layer, allowing only the first position of the contact layer to be etched. That is, using the first sub-mask layer as a mask, etching downwards from the first position of the contact layer to above the active layer forms the light-emitting region. The first and second positions of the contact layer are then masked, and only the third position of the contact layer is etched. That is, using the third sub-mask layer as a mask, the third position of the contact layer is etched downwards to above the N-type Inp layer 452 to form the modulation region. Then, the first and third positions of the contact layer are masked, and only the second position of the contact layer is etched. That is, using the second sub-mask layer as a mask, the second position of the contact layer is etched downwards to below the N-type Inp layer 452. The structure of the first chip structure obtained after S200 is as follows. Figure 11 As shown in l in the figure.

[0190] Alternatively, S202: Using the mask layer as a mask, first etch downwards at the first position of the contact layer to above the first active layer to form a light-emitting region; then simultaneously etch downwards at the second and third positions of the contact layer so that the second position of the contact layer is etched to below the conductive layer, and the third position of the contact layer is etched downwards to below the second active layer to form a modulation region.

[0191] Using the mask layer as a mask for etching downwards, first etching the first position of the contact layer, and then simultaneously etching the second and third positions of the contact layer, can reduce etching time.

[0192] The first trench 461 of the light-emitting region extends from the top to above the active layer, the second trench 462 of the modulation region extends from the top to above the second N-type Inp layer, and the third trench between the first trench 461 and the second trench 462 extends from the top to below the second N-type Inp layer. The mask layer may include a first sub-mask layer and a second sub-mask layer. The first sub-mask layer serves as a mask for etching the first position of the contact layer, and the second sub-mask layer serves as a mask for etching the second and third positions of the contact layer. Etching downwards using the mask layer as a mask can first block the second and third positions of the contact layer, etching only the first position of the contact layer. That is, using the first sub-mask layer as a mask, etching downwards from the first position of the contact layer to above the first active layer to form the light-emitting region. Then, blocking the first position of the contact layer again, etching only the second and third positions of the contact layer. That is, using the second sub-mask layer as a mask, etching downwards from the second and third positions of the contact layer to above the N-type Inp layer 452 to form the modulation region. The structure of the first chip structure obtained after S200 is as follows: Figure 11 As shown in h.

[0193] The etching continues downwards using the second sub-mask layer as a mask, allowing the second position of the contact layer to be etched below the N-type Inp layer 452, thus avoiding misalignment errors.

[0194] In some embodiments, the mask layer is used as a mask to etch downwards, and the second position of the contact layer is etched downwards into the interior of the N-type Inp layer, and the third position of the contact layer is etched downwards into the interior of the N-type Inp layer, so as to determine whether the second position of the contact layer is etched below the conductive layer and whether the third position of the contact layer is etched below the second active layer.

[0195] Figure 14 Provided according to some embodiments Figure 11 A partial cross-sectional view of h in the diagram. Figure 14 for Figure 11 The cross-sectional view of the conduction pre-set region of h in the diagram. (See diagram below.) Figure 11 and Figure 14 As shown, the conductive pre-set area of ​​the first chip structure is sequentially disposed from bottom to top as a substrate 451, an N-type Inp layer 452, a conductive layer 453, a P-type Inp layer 454, a contact layer 455, and a mask layer 470. The widths of the conductive layer 453, the P-type Inp layer 454, the contact layer 455, the mask layer 470, and the first sub-N-type Inp layer are equal. The width of the first sub-N-type Inp layer is smaller than the width of the second sub-N-type Inp layer, meaning that etching downwards using the mask layer as a mask extends into the interior of the N-type Inp layer 452. The first sub-N-type Inp layer is located above the second sub-N-type Inp layer.

[0196] S300: A passivation layer is deposited on the surface of the first chip structure to form a second chip structure.

[0197] The first chip structure is the etched chip. That is, a passivation layer is deposited on the surface of the etched chip to form the second chip structure.

[0198] A passivation layer is deposited on the surface of a first chip structure using chemical vapor deposition to form a second chip structure. The passivation layer can be silicon dioxide (SiO2). The passivation layer protects the first chip structure. The structure of the second chip structure obtained after step S300 is as follows. Figure 11 As shown in i in the diagram.

[0199] Figure 15 Provided according to some embodiments Figure 11 A partial cross-sectional view of i in the diagram. Figure 15 for Figure 11 The cross-sectional view of the conduction preset region of i in the diagram. (See diagram below.) Figure 11 and Figure 15 As shown, the conductive pre-placement area of ​​the second chip structure is provided with a substrate 451, an N-type Inp layer 452, a conductive layer 453, a P-type Inp layer 454, a contact layer 455, a mask layer 470, and a passivation layer 456 from bottom to top. The passivation layer 456 can cover the mask layer 470, the side of the mask layer 470, the side of the contact layer 455, the side of the P-type Inp layer 454, the side of the conductive layer 453, the side of the first sub-N-type Inp layer, and the top of the second sub-N-type Inp layer.

[0200] S400: The upper surface of the passivation layer at the middle position is etched without a mask to the bottom of the passivation layer to form a third chip structure.

[0201] The upper surface of the passivation layer at the middle position of the second chip structure is etched without a mask to the area below the passivation layer using reactive ion etching (RIE) to form the third chip structure. The middle position of the passivation layer is located within the projection area of ​​the second position of the contact layer, meaning the middle position of the passivation layer corresponds to the second position of the contact layer. The structure of the third chip structure obtained after S400 is as follows. Figure 11 As shown in j in the figure.

[0202] Figure 16 Provided according to some embodiments Figure 11 A partial cross-sectional view of j in the diagram. Figure 16 for Figure 11 The cross-sectional view of the conduction preset region of j in the diagram. (See also...) Figure 11 and Figure 16As shown, the conductive pre-placement area of ​​the third chip structure is provided with a substrate 451, an N-type Inp layer 452, a conductive layer 453, a P-type Inp layer 454, a contact layer 455, and a mask layer 470 from bottom to top. The passivation layer 456 can cover the side of the mask layer 470, the side of the contact layer 455, the side of the P-type Inp layer 454, the side of the conductive layer 453, and the side of the first sub-N-type Inp layer.

[0203] S500: Using a mask layer and a passivation layer as a mask, the fourth chip structure is formed by etching downwards from the middle position of the N-type Inp layer to below the N-type Inp layer.

[0204] Using a mask layer and a passivation layer as masks, an ICP dry etching process is used to etch downwards into the substrate from the middle position of the N-type Inp layer in the third chip structure, forming a fourth chip structure. This facilitates determining whether the middle position of the N-type Inp layer has been etched below the N-type Inp layer. Specifically, the middle position of the N-type Inp layer is located within the projection area of ​​the passivation layer at the second position of the contact layer; that is, the middle position of the N-type Inp layer corresponds to the second position of the contact layer. The structure of the fourth chip structure obtained after S500 is as follows: Figure 11 As shown in k in the figure.

[0205] Figure 17 Provided according to some embodiments Figure 11 A local cross-sectional view of k in the diagram. Figure 17 for Figure 11 The cross-sectional diagram of the conduction preset region of k in the diagram. (See also...) Figure 11 and Figure 17 As shown, the conductive pre-set area of ​​the fourth chip structure is provided with a substrate 451, an N-type Inp layer 452, a conductive layer 453, a P-type Inp layer 454, a contact layer 455, and a mask layer 470 from bottom to top. The passivation layer 456 can cover the side of the mask layer 470, the side of the contact layer 455, the side of the P-type Inp layer 454, the side of the conductive layer 453, and the side of the first sub-N-type Inp layer. The width of the second sub-N-type Inp layer is equal to the width of the first sub-substrate. The width of the first sub-substrate is smaller than the width of the second sub-substrate. The first sub-substrate is located above the second sub-substrate.

[0206] S600: Remove the mask layer and passivation layer of the fourth chip structure to form the fifth chip structure.

[0207] The structure of the fifth chip structure obtained after S600 is as follows: Figure 11 As shown in l in the figure.

[0208] Figure 18 Provided according to some embodiments Figure 11 A partial cross-sectional view of l in the figure. Figure 18 for Figure 11The cross-sectional view of the conduction pre-set region of l in the diagram. (See diagram below.) Figure 11 and Figure 18 As shown, the conductive pre-placement area of ​​the fifth chip structure is provided with a substrate 451, an N-type Inp layer 452, a conductive layer 453, a P-type Inp layer 454 and a contact layer 455 from bottom to top.

[0209] S700: A protective layer is coated on top of the fifth chip structure to form the sixth chip structure.

[0210] A protective layer is coated on top of the fifth chip structure using chemical vapor deposition to protect areas of the chip that do not require ion implantation, forming the sixth chip structure. The structure of the sixth chip structure obtained after S700 is as follows. Figure 11 As shown by m in the figure, but ion implantation has not yet been performed at this time. Figure 11 As shown in m, the surface of the conductive pre-placement region of the sixth chip structure is exposed, that is, the area of ​​the chip that needs ion implantation is exposed.

[0211] In some embodiments, the protective layer may be photoresist. Photoresist is easy to remove, exposing the conductive pre-placement region, which facilitates subsequent tilted ion implantation of the conductive pre-placement region.

[0212] S800: The first element is implanted into the N-type Inp layer and the P-type Inp layer at an inclined angle to form the seventh chip structure.

[0213] That is, the first element is implanted into the conduction pre-positioning region of the sixth chip structure at an inclined angle, which means that the first element is implanted into the N-type Inp layer and the P-type Inp layer of the sixth chip structure at an inclined angle to form the seventh chip structure.

[0214] The N-type Inp layer below the first active layer and the N-type Inp layer below the second active layer are not doped with the first element, while the N-type Inp layer below the conduction layer is doped with the first element, which gives the N-type Inp layer below the conduction layer the characteristic of electrical isolation, thereby isolating the charge carriers of the N-type Inp layer in the light-emitting region from the charge carriers of the N-type Inp layer in the modulation region.

[0215] The P-type Inp layer above the first active layer and the P-type Inp layer above the second active layer are not doped with the first element, while the P-type Inp layer above the conduction layer is doped with the first element, which gives the P-type Inp layer above the conduction layer the characteristic of electrical isolation, thereby separating the charge carriers of the P-type Inp layer in the light-emitting region from the charge carriers of the P-type Inp layer in the modulation region.

[0216] The first element is injected into the conduction pre-positioning region of the sixth chip structure at an inclined angle. The requirement for the implantation depth limit of the ion implantation equipment is converted into the control of the width of the N-type Inp layer in the conduction pre-positioning region, so that the ion implantation depth of the N-type Inp layer can meet the requirements.

[0217] Figure 19 Provided according to some embodiments Figure 11 A partial cross-sectional view of m in the diagram. Figure 19 for Figure 11 The cross-sectional view of the conduction pre-set region of m in the diagram. (See diagram below.) Figure 11 and Figure 19 As shown, the surface of the conductive pre-positioned region of the sixth chip structure is exposed. An ion implanter can implant the first element at an angle onto one side of the conductive pre-positioned region of the sixth chip structure, that is, onto one side of the N-type Inp layer and the P-type Inp layer of the sixth chip structure. The ion implanter can also implant the first element at an angle onto the other side of the conductive pre-positioned region of the sixth chip structure, that is, onto the other side of the N-type Inp layer and the P-type Inp layer of the sixth chip structure. Implanting the first element at an angle onto both sides of the conductive pre-positioned region of the sixth chip structure can increase the concentration of the first element in the N-type Inp layer of the conductive pre-positioned region.

[0218] like Figure 11 and Figure 19 As shown, the width of the N-type Inp layer in the conductive pre-positioning region of the sixth chip structure and the depth of a single ion implantation satisfy the following trigonometric relationship: width = 2 * d * cosθ. Where width is the maximum width of the N-type Inp layer in the conductive pre-positioning region, d is the depth of a single ion implantation, and θ is the tilt angle. The maximum width of the N-type Inp layer in the conductive pre-positioning region is also the maximum width of the N-type Inp layer.

[0219] Since the width of the N-type Inp layer in the conduction pre-positioning region and the single ion implantation depth satisfy the following trigonometric relationship: width=2*d*cosθ, the maximum width of the N-type Inp layer in the conduction pre-positioning region can be calculated based on the limit implantation depth control capability of the ion implantation equipment. This converts the requirement for the limit implantation depth of the ion implantation equipment into the requirement for the width of the N-type Inp layer in the conduction pre-positioning region, thereby facilitating precise control of the ion implantation depth.

[0220] In some embodiments, the tilt angle θ can be 0° to 60°, so that the ion implanter can implant into the N-type Inp layer of the conductive pre-positioning region of the sixth chip structure at a tilt angle.

[0221] In some embodiments, the tilt angle θ can be 0° to 45° and 45° to 60°, but not including 0° and 45°, so that the first element is not implanted along the lattice direction of the N-type Inp layer, reducing the tunneling effect and making it easier to control the implantation depth of the first element in the N-type Inp layer.

[0222] After step S800, a seventh chip structure is formed, which includes a first electrical isolation layer and a second electrical isolation layer. The first electrical isolation layer is obtained by transforming the N-type Inp layer of the conductive pre-setting region of the sixth chip structure, and the second electrical isolation layer is obtained by transforming the P-type Inp layer of the conductive pre-setting region of the sixth chip structure. After steps S107-S800, the conductive pre-setting region becomes the conductive region.

[0223] S900: The seventh chip structure removes the protective layer and etches away the contact layer above the P-type Inp layer doped with the first element to form the eighth chip structure.

[0224] Remove the protective layer and etch away the contact layer above the P-type Inp layer doped with the first element, so that the contact layer above the P-type Inp layer above the first active layer and the contact layer above the P-type Inp layer above the second active layer are separated.

[0225] The structure of the eighth chip obtained after S900 is as follows: Figure 11 As shown in n. Figure 11 As shown in n, the first contact layer of the light-emitting region and the second contact layer of the modulation region in the eighth chip structure are not connected.

[0226] Figure 20 Provided according to some embodiments Figure 11 A local cross-sectional view of n in the diagram. Figure 20 for Figure 11 A cross-sectional view of the conduction region of n in the diagram. (See diagram below.) Figure 11 and Figure 20 As shown, the conductive region of the eighth chip structure is provided with a substrate 451, a first electrical isolation layer 452a, a conductive layer 453, and a second electrical isolation layer 454a from bottom to top.

[0227] S1000: A first positive electrode is grown on the contact layer above the P-type Inp layer above the first active layer, and a second positive electrode is grown on the contact layer above the P-type Inp layer above the second active layer, forming a ninth chip structure.

[0228] First, a passivation layer is deposited on top of the eighth chip structure, and then the passivation layer is etched to expose the contact layer of the light-emitting region and the contact layer of the modulation region. Then, a first positive electrode is grown on the first contact layer of the light-emitting region and a second positive electrode is grown on the second contact layer of the modulation region.

[0229] A first positive electrode is grown on the first contact layer, so that the electrical signal received by the first positive electrode can be transmitted sequentially through the contact layer and the P-type Inp layer to the first active layer; a second positive electrode is grown on the second contact layer, so that the electrical signal received by the second positive electrode can be transmitted sequentially through the contact layer and the P-type Inp layer to the second active layer.

[0230] The structure of the ninth chip structure obtained after S1000 is as follows: Figure 11 As shown in o. Figure 11 As shown in o, the first positive electrode and the second positive electrode are not connected to avoid crosstalk between the electrical signals of the first positive electrode and the second positive electrode.

[0231] Figure 9 for Figure 11 A cross-sectional view of the conduction region of o in the diagram. (See diagram below.) Figure 11 and Figure 9 As shown, the conductive region of the ninth chip structure is provided with a substrate 451, a first electrical isolation layer 452a, a conductive layer 453, a second electrical isolation layer 454a, and a passivation layer 456 from bottom to top. The passivation layer 456 can cover the top of the second electrical isolation layer 454a, the side of the second electrical isolation layer 454a, the side of the conductive layer 453, the side of the first electrical isolation layer 452a, and the top of the substrate 451.

[0232] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for fabricating a laser chip, characterized in that, include: An N-type Inp layer is grown above a substrate. A first active layer, a conductive layer, and a second active layer are grown above the N-type Inp layer. One end of the conductive layer is connected to the first active layer, and the other end of the conductive layer is connected to the second active layer. A P-type Inp layer, a contact layer, and a mask layer are grown sequentially above the first active layer, the conductive layer, and the second active layer. Using a mask layer as a mask, the contact layer is etched downwards to above the first active layer at a first position, downwards to below the conductive layer at a second position, and downwards to below the second active layer at a third position to form an etched chip; After etching, a passivation layer is deposited on the chip surface, and the upper surface of the passivation layer at the middle position is etched without a mask to the bottom of the passivation layer. The middle position of the passivation layer is located in the projection area of ​​the contact layer within the passivation layer. Using a mask layer and a passivation layer as a mask, the N-type Inp layer is etched downwards to below the N-type Inp layer at the middle position of the N-type Inp layer. The middle position of the N-type Inp layer is located in the projection area of ​​the N-type Inp layer of the second position of the contact layer. The first element is implanted into the N-type Inp layer and the P-type Inp layer at an angle. The N-type Inp layer below the first active layer and the second active layer is not doped with the first element. The N-type Inp layer below the conductive layer is doped with the first element. The P-type Inp layer above the first active layer and the second active layer is not doped with the first element. The P-type Inp layer above the conductive layer is doped with the first element.

2. The preparation method according to claim 1, characterized in that, The first element is implanted into the N-type Inp layer and the P-type Inp layer at an oblique angle, including: The first element is implanted into one side of the N-type Inp layer and the P-type Inp layer at an oblique angle; The first element is implanted at an angle into the N-type Inp layer and the other side of the P-type Inp layer.

3. The preparation method according to claim 1, characterized in that, The tilt angle is 0° to 45° and 45° to 60°, but does not include 0° and 45°.

4. The preparation method according to claim 1, characterized in that, The width of the N-type Inp layer and the depth of a single ion implantation satisfy the following triangular relationship: width = 2 * d * cosθ, where width is the maximum width of the N-type Inp layer, d is the depth of a single ion implantation, and θ is the tilt angle.

5. The preparation method according to claim 1, characterized in that, Using a mask layer as a mask, etching downwards at a first position of the contact layer to above the first active layer, etching downwards at a second position of the contact layer to below the conductive layer, and etching downwards at a third position of the contact layer to below the second active layer, including; Using the mask layer as a mask, the contact layer is etched downwards to above the first active layer at the first position, downwards to the interior of the N-type Inp layer at the second position, and downwards to the interior of the N-type Inp layer at the third position.

6. The preparation method according to claim 1, characterized in that, Using the mask layer and passivation layer as masks, etching is performed downwards from the middle position of the N-type Inp layer to below the N-type Inp layer, including: Using a mask layer and a passivation layer as a mask, the N-type Inp layer is etched downwards into the interior of the substrate at the middle position.

7. The preparation method according to claim 1, characterized in that, Before the first element is implanted into the N-type Inp layer at an angle, the procedure further includes: Remove the mask layer and passivation layer, and apply a protective layer; The protective layer is photoresist.

8. The preparation method according to claim 7, characterized in that, After the first element is implanted into the N-type Inp layer and the P-type Inp layer at an oblique angle, the process further includes: Remove the protective layer and etch away the contact layer above the P-type Inp layer doped with the first element; A first positive electrode is grown on a contact layer above a P-type Inp layer above the first active layer, and a second positive electrode is grown on a contact layer above a P-type Inp layer above the second active layer.

9. A laser chip, fabricated using the method described in any one of claims 1-8, characterized in that, include: Substrate; A first N-type Inp layer is located above the substrate; A first electrically insulating layer is located above the substrate, with one end connected to the first N-type Inp layer; wherein the first electrically insulating layer is an N-type Inp layer doped with a first element; The second N-type Inp layer is located above the substrate, with one end connected to the other end of the first electrically isolated layer; The first active layer is located above the first N-type Inp layer; A conductive layer is located above the first electrically isolated layer, with one end connected to the first active layer; The second active layer is located above the second N-type Inp layer, and one end is connected to the other end of the conductive layer. The first P-type Inp layer is located above the first active layer; The second electrical isolation layer is located above the conductive layer, and one end is connected to the first P-type Inp layer; the second electrical isolation layer is a P-type Inp layer doped with the first element; The second P-type Inp layer is located above the second active layer, and one end is connected to the other end of the second electrical isolation layer. The contact layer is located above the first P-type Inp layer, the second electrical isolation layer, and the second P-type Inp layer.

10. The laser chip according to claim 9, characterized in that, The contact layer includes: A first contact layer is located above the first P-type Inp layer and is connected to the first P-type Inp layer; a first positive electrode is disposed above the first contact layer and is connected to the first contact layer. The second contact layer is located above the second P-type Inp layer and is connected to the second P-type Inp layer; a second positive electrode is disposed above the second contact layer and is connected to the second contact layer; the second contact layer is not connected to the first contact layer, and the first positive electrode is not connected to the second positive electrode.

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