A thyristor switch type controllable surge arrester and a control method thereof

Abstract

This invention provides a thyristor-controlled surge arrester and its control method. By constructing a dual-channel voltage processing algorithm based on morphological filtering and adaptive Kalman filtering, it achieves rapid and reliable judgment of power frequency overvoltage. The controllable surge arrester provided by this invention is installed at the phase-to-phase position of the protected transmission line and includes a nonlinear voltage limiting branch, a main protection circuit, an energy extraction and voltage division module, and a control and detection module. The nonlinear voltage limiting branch includes a first varistor and a first parallel capacitor connected in parallel with it. The main protection circuit consists of a positive thyristor conduction branch and a negative thyristor conduction branch. The two conduction branches are connected in antiparallel and in series with the nonlinear voltage limiting branch to achieve bidirectional controlled conduction of the positive and negative half-cycles of the power frequency overvoltage at both ends of the controllable part of the thyristor-controlled surge arrester. Electrically isolated thyristor gate triggering control is achieved through a pulse transformer and an isolation triggering circuit.

Description

Technical Field

[0001] This invention relates to the field of surge arrester technology, specifically to a thyristor-controlled surge arrester and its control method. Background Technology

[0002] Traditional metal oxide surge arresters, as the main equipment for overvoltage protection, are limited in their protection level by the inherent characteristics of the nonlinear resistive materials themselves. To ensure long-term stability under continuous system operating voltage, surge arresters must be designed with a low charge rate. This usually means selecting valve plates with a higher reference voltage, but the side effect is that the residual voltage under overvoltage impulses increases accordingly, making it difficult to meet the increasingly stringent deep voltage limiting requirements. This contradiction constitutes a performance ceiling that traditional surge arrester technology has difficulty overcoming.

[0003] To overcome this limitation, the concept of controllable surge arresters emerged. Its basic principle is to introduce a controllable switching unit to dynamically adjust the equivalent impedance structure of the surge arrester under normal operation and overvoltage conditions. Under normal operating conditions, the switch is open, and the system voltage is shared by the entire surge arrester unit, including the additional impedance, thereby significantly reducing the charge rate of the core metal oxide resistor and extending its lifespan. When a dangerous overvoltage is detected, the control unit drives the switch to close rapidly, short-circuiting part of the impedance, instantly increasing the equivalent protection level of the surge arrester and achieving a lower residual voltage output. This "dual-mode" operating concept is considered the most effective way to resolve the contradiction between deep voltage limiting and long-term reliability.

[0004] However, the practical application of controllable surge arresters highly depends on the performance and reliability of the controllable switching elements themselves. Currently, the main technical approaches all have their inherent defects. Gas discharge gaps have the advantages of fast conduction speed and simple structure, and provide good protection under lightning impulse overvoltage conditions. However, their breakdown voltage is affected by various random factors such as gas pressure, electrode spacing, temperature, and electrode surface condition, exhibiting significant dispersion characteristics, meaning the breakdown voltage follows a probability distribution rather than a deterministic value. When the power frequency overvoltage amplitude is low (such as the scenario in this solution, a power frequency overvoltage of 1.1 to 1.3 times the rated voltage generated by a 35kV collector line), the discharge gap often fails to break down reliably, leading to protection failure or inconsistent operation, making it difficult to meet the requirements of controllable protection.

[0005] Mechanical switch-type protection devices achieve overvoltage isolation through relay or circuit breaker operation. Their operating time is usually 10ms to 50ms or more, which is difficult to meet the requirements for fast overvoltage limiting. They are usually only used as backup in multi-level protection.

[0006] In contrast, thyristor-type controllable surge arresters achieve controlled conduction through semiconductor devices, offering advantages such as precisely settable operating voltage, good repeatability, and no dispersion, making them particularly suitable for precise limiting of power frequency overvoltages. However, the operating delay of this type of device is no longer determined by the physical breakdown process, but mainly depends on the calculation speed and accuracy of voltage detection, signal processing, and control algorithms. Most existing technologies employ amplitude calculation methods based on Fourier transforms or fixed filters, resulting in a calculation delay of at least half to one power frequency cycle. Furthermore, they are susceptible to voltage spikes and high-frequency interference, limiting the accuracy and timeliness of thyristor-type controllable surge arresters.

[0007] Therefore, how to shorten the time delay required from the moment the actual voltage measurement reaches the threshold to the judgment process confirming that the power frequency overvoltage has reached and will definitely exceed the threshold, while ensuring anti-interference capability and operational accuracy, has become one of the key technical bottlenecks restricting the performance improvement of such devices. Summary of the Invention

[0008] This invention aims to address the technical deficiencies of existing technologies by providing a thyristor-controlled surge arrester and its control method. By constructing a dual-channel voltage processing algorithm based on morphological filtering and adaptive Kalman filtering, it achieves rapid and reliable judgment of power frequency overvoltage, thereby reducing the time delay required from the moment the actual voltage measurement instantaneous value reaches the threshold to the judgment process confirming that the power frequency overvoltage has reached and will definitely exceed the threshold, thus improving the accuracy and timeliness of overvoltage detection.

[0009] This invention discloses a thyristor-controlled surge arrester, installed at the phase-to-phase position of the protected transmission line, comprising a nonlinear voltage limiting branch, a main protection circuit, an energy extraction and voltage divider module, and a control and detection module. The nonlinear voltage limiting branch includes a first varistor and a first parallel capacitor connected in parallel with it.

[0010] The main protection circuit consists of a positive thyristor conduction branch and a negative thyristor conduction branch. The two conduction branches are connected in anti-parallel with the nonlinear voltage limiting branch in series. The power frequency overvoltage at both ends of the controllable part of the thyristor switching type controllable surge arrester is bidirectionally controlled to conduct during the positive and negative half-cycles. Each conduction branch includes at least one high-voltage, high-current thyristor, and the thyristor gate triggering control is electrically isolated through a pulse transformer and an isolation triggering circuit.

[0011] The energy harvesting and voltage divider module includes an energy harvesting branch consisting of a second parallel capacitor and a second varistor connected in series. The second parallel capacitor and the first parallel capacitor together form an auxiliary capacitor voltage divider structure. The second varistor is connected in series at the lower end of the second parallel capacitor to harvest energy. The second varistor is connected in parallel with the isolation transformer. The voltage on the second varistor is isolated and then input into the rectifier bridge to provide energy for the energy storage capacitor connected afterward.

[0012] The control and detection module includes a signal conditioning circuit, a central processing module, an isolation drive circuit, a power supply module, and a capacitor voltage divider group. The voltage sampling capacitor voltage divider group is used to collect the voltage signal across the thyristor-controlled surge arrester in real time as the input of the control algorithm. The signal conditioning circuit includes a buffer amplifier, the input of which is connected to the capacitor voltage divider group. It is used to perform impedance transformation and amplitude conditioning on the divided voltage signal. The conditioned voltage signal is sent to the high-speed analog-to-digital converter module for sampling, and the sampled voltage is input to the central processing module at a set sampling frequency. The central processing module uses a dual-channel voltage analysis algorithm to determine whether the voltage meets the conduction conditions and the polarity of the voltage. If the set conduction conditions are met, the central processing module issues a command according to the polarity of the overvoltage. After the command is processed by the isolation drive circuit, it drives the corresponding positive drive MOSFET or negative drive MOSFET to conduct, thereby executing the corresponding protection action. The power supply module provides the required low-voltage DC power.

[0013] Preferably, the forward thyristor conduction branch is used to handle positive half-wave overvoltage, including an energy harvesting and storage circuit, an isolation trigger circuit, and a conduction execution circuit. The energy harvesting and storage circuit includes a forward rectifier bridge and a forward energy storage capacitor. The forward rectifier bridge rectifies the AC power output from the isolation transformer into DC power and stores it in the forward energy storage capacitor.

[0014] The isolation trigger circuit includes a forward drive MOSFET and a forward pulse transformer. The forward drive MOSFET acts as an electronic switch to control the discharge of the forward energy storage capacitor, and the forward pulse transformer realizes high and low voltage electrical isolation and energy transfer.

[0015] The conduction execution circuit includes a positive secondary side rectification and current limiting circuit, a positive thyristor valve group, and a positive voltage equalization and absorption circuit. The output of the positive pulse transformer secondary side is shaped by the positive secondary side rectification and current limiting circuit and then triggers the positive thyristor valve group. The valve group is composed of multiple thyristors connected in series, and each thyristor is connected in parallel with a positive voltage equalization and absorption circuit at both ends.

[0016] Preferably, the negative thyristor conduction branch is used to handle negative half-wave overvoltage, including an energy harvesting and storage circuit, an isolation trigger circuit, and a conduction execution circuit. The energy harvesting and storage circuit includes a negative rectifier bridge and a negative energy storage capacitor. The negative rectifier bridge rectifies the AC power output from the isolation transformer into DC power and stores it in the negative energy storage capacitor.

[0017] The isolation trigger circuit includes a negative drive MOSFET and a negative pulse transformer. The negative drive MOSFET acts as an electronic switch to control the discharge of the negative energy storage capacitor, and the negative pulse transformer realizes high and low voltage electrical isolation and energy transfer.

[0018] The conduction execution circuit includes a negative secondary side rectification and current limiting circuit, a negative thyristor valve group, and a negative voltage equalization and absorption circuit. The output of the negative pulse transformer secondary side is shaped by the negative secondary side rectification and current limiting circuit and then triggers the negative thyristor valve group. The valve group is composed of multiple thyristors connected in series, and each thyristor is connected in parallel with a negative voltage equalization and absorption circuit at both ends.

[0019] Preferably, the central processing module includes a microcontroller, a digital signal processor, or a programmable logic device, which executes the following logic:

[0020] Digital filtering; Construct parallel morphological filtering channels and adaptive Kalman filtering channels to perform digital filtering processing on the input sampled voltage signal;

[0021] Eigenvalue calculation: Based on the filtered voltage signal, eigenvalues ​​are calculated and updated in real time, namely the instantaneous voltage value and the effective voltage value;

[0022] Polarity and threshold discrimination: The polarity of the voltage is determined based on the sign of the instantaneous voltage value; a co-criterion is adopted, that is, the instantaneous voltage value > threshold A and the effective voltage value > threshold B.

[0023] Preferably, the dual-channel voltage analysis algorithm includes a morphological filtering channel and an adaptive Kalman filtering channel. The morphological filtering channel performs nonlinear time-domain operations on the input sampled voltage signal to extract voltage abrupt changes, steep transition edges, and power frequency features, which are used to quickly determine whether the system has entered a power frequency overvoltage state.

[0024] The Kalman filter channel is based on I / Q orthogonal state and modeled with a rotation matrix. It recursively estimates the fundamental voltage component and outputs the real-time power frequency effective value. When the morphological filter channel detects abrupt changes exceeding a set threshold, the microcontroller dynamically adjusts the process noise covariance matrix parameters of the Kalman filter. After obtaining the voltage effective value and voltage polarity judgment result, the microcontroller generates a conduction signal according to the preset power frequency overvoltage action threshold and duration criterion. The signal is then controlled by the positive or negative drive MOSFET to turn on the corresponding power MOSFET, so that the energy in the positive or negative energy storage capacitor is coupled to the gate of the corresponding thyristor through the positive or negative pulse transformer, thereby achieving electrical isolation triggering between the high-voltage side and the low-voltage control side.

[0025] Preferably, the dual-channel voltage analysis algorithm includes the following steps:

[0026] 1) Morphological switching filtering is used to remove glitches and spikes in voltage signals. It uses the following formula:

[0027] ,

[0028] ,

[0029] ,

[0030] ,

[0031] In the formula, k represents the current discrete sampling time, which is the time base for the entire time-domain processing flow. The original sampling voltage is L, and the length of the structuring element is L. This is the result of performing a minimum value operation on the original sampled signal within a sliding window of length L. To The sequence is then subjected to a sliding window expansion operation to retrieve the maximum value. To perform the maximum value operation again, The final output of the morphological filtering cascade link is obtained by modifying the previous stage. The sequence is subjected to a minimum value operation within a sliding window;

[0032] 2) Kalman estimation; from Extract the best consistent estimate of the power frequency sine wave to obtain the estimated instantaneous value. and estimated amplitude We employ I / Q orthogonal states and model them using rotation matrices:

[0033] Define a two-dimensional state vector:

[0034] In the formula, The state at time k is... To correspond to the sine component, For the corresponding cosine orthogonal components;

[0035] The discrete rotational state equation and measurement equation are as follows:

[0036] ,

[0037] ,

[0038] ,

[0039] ,

[0040] ,

[0041] In the formula, This is the rotation state transition matrix; For the measurement matrix, For process noise, To measure noise, For measured values, take the morphological output. ;

[0042] Kalman prediction:

[0043] ,

[0044] ,

[0045] In the formula, For prior state estimation; This is a posterior estimate from the previous time step. For the prior error covariance, Let $\frac{ ... The process noise covariance matrix;

[0046] Innovation and innovation covariance:

[0047] ,

[0048] ,

[0049] In the formula, Innovation means measuring residuals. To innovate covariance, To measure the noise variance;

[0050] 3) Innovation gating; constructing normalized innovation statistics:

[0051] ,

[0052] In the formula, For normalized innovation, For innovation standard deviation;

[0053] Given threshold The update strategy is as follows:

[0054] ,

[0055] , ,

[0056] In the formula, To innovate the gating threshold, , These are the posterior state estimate and the posterior covariance, respectively.

[0057] When satisfied At that time, the Kalman gain and update are as follows:

[0058] ,

[0059] ,

[0060] ,

[0061] In the formula, For Kalman gain, It is the identity matrix;

[0062] Instantaneous and magnitude estimates are obtained from the posterior state:

[0063] ,

[0064] ,

[0065] In the formula, To estimate the instantaneous voltage, , For the two components of the posterior state, To estimate the amplitude;

[0066] 4) Slope consistency constraint;

[0067] right Calculate the difference derivative:

[0068] In the formula, It is an approximation of the discrete derivative;

[0069] Construct the normalized slope ratio:

[0070] ,

[0071] In the formula, As a slope consistency index, It is the power frequency angular frequency. To prevent the lower limit of the denominator from being too small;

[0072] Define the criteria for valid sample points:

[0073] ,

[0074] In the formula, for Threshold, This represents the logical AND operation;

[0075] 5) ARM pre-enable, amplitude unlocked to avoid premature false triggering;

[0076] Set the instantaneous overvoltage threshold. And give the amplitude unlock threshold:

[0077] In the formula, Unlock the amplitude threshold for ARM. This is the proportionality coefficient. The threshold is used to determine the instantaneous threshold crossing.

[0078] Using consecutive points Confirm unlock:

[0079] ,

[0080] In the formula, To unlock the counter, To unlock the icon, To confirm the number of consecutive points;

[0081] , Enables final detection;

[0082] 6) Enable logic and final threshold decision;

[0083] To obtain the shortest detection delay, the final decision voltage is selected as follows: In the formula,

[0084] For the final detection voltage, Output for morphological preprocessing;

[0085] Set a release threshold. And set the final number of confirmed points as In the formula,

[0086] The delayed release threshold, This is the number of points confirmed for exceeding the threshold.

[0087] Preferably, step 6 of the dual-channel voltage analysis algorithm further includes:

[0088] Step 6.1, Forward channel IO1;

[0089] Define positive candidate conditions: In the formula, Positive threshold crossing candidate; Enable detection; This serves as a marker for valid sample points; To detect voltage; This is the input threshold;

[0090] right Continuous counting:

[0091] ,

[0092] In the formula, For positive confirmation counter, To confirm the number of points, To maintain a positive state;

[0093] Positive hold release condition with hysteresis:

[0094] In the formula,

[0095] Indicates logical NOT. Represents logical OR, The release threshold;

[0096] The output is defined as: In the formula, The output level is requested for forward conduction;

[0097] Step 6.2, Negative channel IO2;

[0098] Define negative candidate conditions:

[0099] In the formula, This is a negative threshold candidate. This represents the negative input threshold.

[0100] right Continuous counting:

[0101] In the formula: For negative confirmation counters, To maintain a negative state;

[0102] Negative hold release condition:

[0103] In the formula, This is the negative release threshold;

[0104] The output is defined as: In the formula, To request the output level for negative conduction;

[0105] To prevent simultaneous conduction of positive and negative signals, a mutual exclusion constraint is applied:

[0106]

[0107] In the formula, the mutual exclusion constraint is used to ensure that only one direction is allowed to output 1 at any given time.

[0108] Preferably, the thyristor turns off naturally at the AC zero-crossing point.

[0109] Another aspect of the present invention discloses a control method for a thyristor-controlled surge arrester, comprising the following steps:

[0110] The system collects the power frequency overvoltage across the thyristor-controlled surge arrester; buffers, amplifies, and performs analog-to-digital conversion on the voltage signal; performs morphological filtering and adaptive Kalman filtering in parallel; determines whether a power frequency overvoltage has occurred based on the filtering results; and triggers the corresponding polarity thyristor to conduct when the operating conditions are met.

[0111] Preferably, when performing morphological filtering and adaptive Kalman filtering in parallel, the bandwidth of the Kalman filter is increased when a voltage change is detected, and decreased in steady state.

[0112] Compared with the prior art, the beneficial effects of the present invention are:

[0113] This invention discloses a thyristor-controlled surge arrester. First, by adopting a dual-channel parallel voltage analysis architecture, the device not only has the ability to estimate the amplitude of power frequency voltage in real time with high accuracy, but also improves the reaction capability from sensing the occurrence of power frequency overvoltage to making a judgment. It effectively reduces the time delay that must occur from the instantaneous value of the actual voltage measurement reaching the threshold to confirming that the power frequency overvoltage has reached and will definitely exceed the threshold. It improves the long delay problem of the traditional single Fourier algorithm in the process of detecting power frequency overvoltage, and fundamentally breaks through the technical bottleneck that the action speed of the thyristor-controlled surge arrester is limited by the algorithm cycle.

[0114] Secondly, this invention utilizes dual-channel analysis of morphological filtering and Kalman filtering, enabling the control system to quickly obtain the actual instantaneous voltage value, the predicted instantaneous voltage value, and the effective value. Furthermore, it makes judgments based on the subsequently set conduction conditions, significantly shortening the time delay required from the actual measured instantaneous voltage value reaching the threshold to confirming that the power frequency overvoltage has reached and will definitely exceed the threshold. This achieves accurate and timely conduction control of 1.1 to 1.3 times the power frequency overvoltage, and also avoids the failure to operate caused by the breakdown dispersion of the gas discharge gap.

[0115] It adopts a composite design of energy-harvesting branch and auxiliary capacitor voltage divider structure, which enables the device to automatically harvest energy to complete the power supply and trigger energy accumulation of the control system when overvoltage occurs without external high-voltage side power supply. This improves the system's independent operation capability and engineering adaptability. At the same time, by reasonably configuring the capacitor voltage divider ratio, it effectively improves the voltage distribution of the thyristor branch, reduces the pressure stress of individual devices, and improves the overall withstand voltage level and long-term operational reliability. Through the dual thyristor conduction branch structure with independent positive and negative polarity control, the device can accurately selectively conduct power frequency overvoltages at different half-cycles at both ends of the controllable part of the thyristor-controlled surge arrester, avoiding unnecessary full-cycle short-circuit impacts, reducing energy loss during overvoltage discharge and the degree of disturbance to the grid operation, which is conducive to improving the operational stability of transmission lines and substation equipment.

[0116] In summary, without significantly increasing hardware complexity, this invention introduces an advanced dual-channel adaptive signal processing algorithm, enabling the thyristor-controlled surge arrester to simultaneously possess advantages such as timeliness, accuracy, anti-interference, and engineering feasibility. It is particularly suitable for application scenarios in new power systems with a high proportion of power electronic equipment, complex grid transient characteristics, and strict requirements for power frequency overvoltage protection. Attached Figure Description

[0117] Figure 1 This is a circuit structure diagram of an embodiment of the present invention;

[0118] Figure 2 The waveform diagram is obtained by testing the algorithm implemented using MATLAB code in this invention.

[0119] Figure 3 for Figure 2 The initial conduction delay time during the test;

[0120] Figure 4 for Figure 2 The number of premature triggers, the number of missed triggers, and the distribution of response times in the test.

[0121] Explanation of reference numerals in the attached figures:

[0122] 1. Nonlinear voltage limiting branch; 11. First varistor; 12. First parallel capacitor;

[0123] 2. Energy extraction and voltage divider module; 21. Second parallel capacitor; 22. Second varistor; 23. Isolation transformer;

[0124] 3. Forward thyristor conduction branch; 31. Forward rectifier bridge; 32. Forward energy storage capacitor; 33. Forward drive MOSFET; 34. Forward pulse transformer; 35. Forward secondary side rectifier current limiting circuit; 36. Forward thyristor valve group; 37. Forward voltage equalization absorption circuit;

[0125] 4. Negative thyristor conduction branch; 41. Negative rectifier bridge; 42. Negative energy storage capacitor; 43. Negative drive MOSFET; 44. Negative pulse transformer; 45. Negative secondary side rectifier current limiting circuit; 46. Negative thyristor valve group; 47. Negative voltage equalization absorption circuit;

[0126] 5. Control and detection module; 51. Signal conditioning circuit; 52. Central processing module; 53. Isolation drive circuit; 54. Power supply module; 55. Capacitor voltage divider group. Detailed Implementation

[0127] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0128] like Figures 1-4 As shown, this invention illustrates a specific embodiment: One aspect of the invention discloses a thyristor-controlled surge arrester, installed at the phase-to-phase position of the protected transmission line, comprising a nonlinear voltage limiting branch 1, a main protection circuit, an energy extraction and voltage divider module 2, and a control and detection module 5. The nonlinear voltage limiting branch 1 includes a first varistor 11 and a first parallel capacitor 12 connected in parallel with it.

[0129] The main protection circuit consists of a positive thyristor conduction branch 3 and a negative thyristor conduction branch 4. The two conduction branches are connected in anti-parallel with the nonlinear voltage limiting branch 1 in series. They enable bidirectional controlled conduction of the positive and negative half-cycles of the power frequency overvoltage at both ends of the controllable part of the thyristor switching type controllable surge arrester. Each conduction branch includes at least one high-voltage, high-current thyristor, and the thyristor gate trigger control is electrically isolated through a pulse transformer and an isolation trigger circuit.

[0130] The energy harvesting and voltage divider module 2 includes an energy harvesting branch consisting of a second parallel capacitor 21 and a second varistor 22 connected in series. The second parallel capacitor 21 and the first parallel capacitor 12 together form an auxiliary capacitor voltage divider structure. The second varistor 22 is connected in series at the lower end of the second parallel capacitor 21 to harvest energy. The second varistor 22 is connected in parallel with the isolation transformer 23. The voltage on the second varistor 22 is isolated and then input into the rectifier bridge to provide energy for the energy storage capacitor connected after it.

[0131] The control and detection module 5 includes a signal conditioning circuit 51, a central processing module 52, an isolation drive circuit 53, a power supply module 54, and a capacitor voltage divider group 55. The voltage sampling capacitor voltage divider group 55 is used to collect the voltage signal across the thyristor-controlled surge arrester in real time as the input of the control algorithm. The signal conditioning circuit 51 includes a buffer amplifier, the input of which is connected to the capacitor voltage divider group 55. It is used to perform impedance transformation and amplitude conditioning on the divided voltage signal. The conditioned voltage signal is sent to the high-speed analog-to-digital converter module for sampling, and the sampled voltage is obtained at a set sampling frequency and input to the central processing module 52. The central processing module 52 uses a dual-channel voltage analysis algorithm to determine whether the voltage meets the conduction conditions and the polarity of the voltage. If the set conduction conditions are met, the central processing module 52 issues a command according to the polarity of the overvoltage. After the command is processed by the isolation drive circuit 53, it drives the corresponding positive drive MOSFET 33 or negative drive MOSFET 43 to conduct, thereby executing the corresponding protection action. The power supply module 54 provides the required low-voltage DC power.

[0132] like Figure 1 As shown, the nonlinear voltage limiting branch 1 is the upper part of the surge arrester, and the voltage dividing module 2 is located in the middle of the surge arrester. The entire surge arrester is connected across the phases of the high-voltage line.

[0133] Preferably, the forward thyristor conduction branch 3 is used to handle positive half-wave overvoltage, including an energy harvesting and storage circuit, an isolation trigger circuit, and a conduction execution circuit. The energy harvesting and storage circuit includes a forward rectifier bridge 31 and a forward energy storage capacitor 32. The forward rectifier bridge 31 rectifies the AC power output from the isolation transformer 23 into DC power and stores it in the forward energy storage capacitor 32.

[0134] The isolation trigger circuit includes a forward drive MOSFET 33 and a forward pulse transformer 34. The forward drive MOSFET 33 acts as an electronic switch to control the discharge of the forward energy storage capacitor 32, and the forward pulse transformer 34 realizes high and low voltage electrical isolation and energy transfer.

[0135] The conduction execution circuit includes a positive secondary side rectification and current limiting circuit 35, a positive thyristor valve group 36, and a positive voltage equalization and absorption circuit 37. The output of the positive pulse transformer 34 on the secondary side is shaped by the positive secondary side rectification and current limiting circuit 35 and then triggers the positive thyristor valve group 36. This valve group is composed of multiple thyristors connected in series, and each thyristor is connected in parallel with a positive voltage equalization and absorption circuit 37 at both ends.

[0136] Preferably, the negative thyristor conduction branch 4 is used to handle negative half-wave overvoltage, including an energy harvesting and storage circuit, an isolation trigger circuit, and a conduction execution circuit. The energy harvesting and storage circuit includes a negative rectifier bridge 41 and a negative energy storage capacitor 42. The negative rectifier bridge 41 rectifies the AC power output from the isolation transformer 23 into DC power and stores it in the negative energy storage capacitor 42.

[0137] The isolation trigger circuit includes a negative drive MOSFET 43 and a negative pulse transformer 44. The negative drive MOSFET 43 acts as an electronic switch to control the discharge of the negative energy storage capacitor 42, and the negative pulse transformer 44 realizes high and low voltage electrical isolation and energy transfer.

[0138] The conduction execution circuit includes a negative secondary side rectifier and current limiting circuit 45, a negative thyristor valve group 46, and a negative voltage equalization and absorption circuit 47. The output of the secondary side of the negative pulse transformer 44 is shaped by the negative secondary side rectifier and current limiting circuit 45 and then triggers the negative thyristor valve group 46. This valve group is composed of multiple thyristors connected in series, and each thyristor is connected in parallel with a negative voltage equalization and absorption circuit 47 at both ends.

[0139] Preferably, the central processing module 52 includes a microcontroller, a digital signal processor, or a programmable logic device, which executes the following logic:

[0140] Digital filtering; Construct parallel morphological filtering channels and adaptive Kalman filtering channels to perform digital filtering processing on the input sampled voltage signal;

[0141] Eigenvalue calculation: Based on the filtered voltage signal, eigenvalues ​​are calculated and updated in real time, namely the instantaneous voltage value and the effective voltage value;

[0142] Polarity and threshold discrimination: The polarity of the voltage is determined based on the sign of the instantaneous voltage value; a co-criterion is adopted, that is, the instantaneous voltage value > threshold A and the effective voltage value > threshold B.

[0143] Preferably, the dual-channel voltage analysis algorithm includes a morphological filtering channel and an adaptive Kalman filtering channel. The morphological filtering channel performs nonlinear time-domain operations on the input sampled voltage signal to extract voltage abrupt changes, steep transition edges, and power frequency features, which are used to quickly determine whether the system has entered a power frequency overvoltage state.

[0144] The Kalman filter channel is based on I / Q orthogonal state and modeled with a rotation matrix. It recursively estimates the fundamental voltage component and outputs the real-time power frequency effective value. When the morphological filter channel detects abrupt changes exceeding a set threshold, the microcontroller dynamically adjusts the process noise covariance matrix parameters of the Kalman filter. After obtaining the voltage effective value and voltage polarity judgment result, the microcontroller generates a conduction signal according to the preset power frequency overvoltage action threshold and duration criterion. The signal is then controlled by the positive or negative drive MOSFET 43 to turn on the corresponding power MOSFET, so that the energy in the positive or negative energy storage capacitor 42 is coupled to the gate of the corresponding thyristor through the positive or negative pulse transformer 44, thereby achieving electrical isolation triggering between the high-voltage side and the low-voltage control side.

[0145] Preferably, the dual-channel voltage analysis algorithm includes the following steps:

[0146] 1) Morphological opening and closing filtering is used to remove glitches and spikes from voltage signals. This part is used to first separate "narrow glitches" from the original instantaneous voltage: glitches usually have a small number of durations and large amplitudes, which can directly lead to instantaneous threshold misjudgments. Morphological opening operation significantly suppresses "narrow positive glitches," while closing operation significantly suppresses "narrow negative glitches." Combining "opening first and then closing" can suppress both positive and negative spikes simultaneously and maintain extremely low delay within a small window, thus providing a measurement sequence that is closer to the true power frequency components for subsequent estimation and discrimination. It uses the following formula:

[0147] ,

[0148] ,

[0149] ,

[0150] ,

[0151] In the formula, k represents the current discrete sampling time, which is the time base for the entire time-domain processing flow. The original sampling voltage is L, and the length of the structuring element is L. The result of performing the minimum value operation on the original sampled signal within a sliding window of length L is that the physical effect of this step is "peak clipping", which can forcibly remove the positive spike interference at the top of the waveform, but the side effect is that it causes the waveform profile of the normal signal to shrink inward. To The sequence performs the sliding window expansion operation again, which constitutes a complete mathematical morphology "opening operation". Its function is to restore the normal waveform width that has been eroded and shrunken. Since the previous spikes have been completely removed, they cannot be recovered, thus achieving perfect filtering of positive spikes. To perform the maximum value operation again, this step is the first part of the morphological "closing operation," which can smooth out the negative spikes at the bottom of the waveform. Through this series of cascaded operations, the final output signal of the algorithm retains the original steep edges of the power frequency waveform while completely eliminating bidirectional high-frequency transient interference. The final output of the morphological filtering cascaded link marks the completion of the mathematical morphology "closing operation" process, achieved through the previous stage. The sequence is subjected to a minimum value operation within a sliding window;

[0152] 2) Kalman estimation; from Extract the best consistent estimate of the power frequency sine wave to obtain the estimated instantaneous value. and estimated amplitude By employing I / Q orthogonal states and modeling with a rotation matrix, a recursive estimation with low latency, interpretability, and low computational cost can be achieved under the premise of fixed power frequency and high sampling rate.

[0153] Define a two-dimensional state vector:

[0154] In the formula, The state at time k is... To correspond to the sine component, For the corresponding cosine orthogonal components;

[0155] The discrete rotational state equation and measurement equation are as follows:

[0156] ,

[0157] ,

[0158] ,

[0159]

[0160]

[0161] In the formula, This is the rotation state transition matrix; For the measurement matrix, For process noise, To measure noise, For measured values, take the morphological output. ;

[0162] Kalman prediction:

[0163]

[0164]

[0165] In the formula, For prior state estimation; This is a posterior estimate from the previous time step. For the prior error covariance, Let $\frac{ ... The process noise covariance matrix;

[0166] Innovation and innovation covariance:

[0167] ,

[0168] ,

[0169] In the formula, Innovation means measuring residuals. To innovate covariance, To measure the noise variance;

[0170] 3) Innovation gating; constructing normalized innovation statistics:

[0171]

[0172] In the formula, For normalized innovation, For innovation standard deviation;

[0173] Given threshold The update strategy is as follows:

[0174]

[0175] , ,

[0176] In the formula, To innovate the gating threshold, , These are the posterior state estimate and the posterior covariance, respectively.

[0177] When satisfied At that time, the Kalman gain and update are as follows:

[0178] ,

[0179] ,

[0180] ,

[0181] In the formula, For Kalman gain, It is the identity matrix;

[0182] Instantaneous and magnitude estimates are obtained from the posterior state:

[0183] ,

[0184] ,

[0185] In the formula, To estimate the instantaneous voltage, , For the two components of the posterior state, To estimate the amplitude;

[0186] 4) Slope consistency constraint;

[0187] right Calculate the difference derivative:

[0188] In the formula, It is an approximation of the discrete derivative;

[0189] Construct the normalized slope ratio:

[0190] ,

[0191] In the formula, As a slope consistency index, It is the power frequency angular frequency. To prevent the lower limit of the denominator from being too small;

[0192] Define the criteria for valid sample points:

[0193] ,

[0194] In the formula, for Threshold, This represents the logical AND operation;

[0195] 5) ARM pre-enable, amplitude unlock, to avoid premature false triggering. This part is used to limit the detection "sensitive area" to an amplitude range close to the overvoltage threshold: when the amplitude is significantly lower than the threshold, any occasional spikes should not trigger a conduction request. "Unlocking" is achieved through continuous acknowledgment by Araw; only when the estimated amplitude remains close to the threshold for an extended period is entry into the final over-threshold decision path allowed, thus significantly reducing the probability of premature false triggering.

[0196] Set the instantaneous overvoltage threshold. And give the amplitude unlock threshold:

[0197] In the formula, Unlock the amplitude threshold for ARM. This is the proportionality coefficient. The threshold is used to determine the instantaneous threshold crossing.

[0198] Using consecutive points Confirm unlock:

[0199] ,

[0200] In the formula, To unlock the counter, To unlock the icon, To confirm the number of consecutive points;

[0201] , Enables final detection;

[0202] 6) Enable logic and final threshold violation decision; this part is used to make a final decision on instantaneous threshold violations under the premise of "unlocked + reliable samples". To reduce detection latency, the decision value is selected as... (To avoid filtering lag); to suppress single-point false thresholds, an introduction is made Point-based continuous confirmation; to avoid output interruption caused by jitter near the threshold, hysteresis is introduced: threshold input... With release threshold The separation ensures a stable output level; at the same time, the mutual exclusion of positive and negative channels guarantees a unique conduction direction.

[0203] To obtain the shortest detection delay, the final decision voltage is selected as follows: In the formula,

[0204] For the final detection voltage, Output for morphological preprocessing;

[0205] Set a release threshold. And set the final number of confirmed points as In the formula,

[0206] The delayed release threshold, This is the number of points confirmed for exceeding the threshold.

[0207] This algorithm is designed for real-time detection of instantaneous power frequency overvoltages. It directly determines the instantaneous voltage at a high sampling rate, but to avoid false triggering caused by noise and glitches, a multi-level constraint chain of "preprocessing—estimation—reliability judgment—unlocking—confirmation—hysteresis holding" is introduced. The output consists of two mutually exclusive level signals, indicating either a positive or negative instantaneous over-threshold, and hysteresis is used to stably hold and release the conduction request. The algorithm comprises six steps:

[0208] Morphological opening and closing filtering: De-spiking peaks ).

[0209] Kalman estimation (filtering): Estimating the power frequency uniformity component ( ) and amplitude ( ).

[0210] Innovative gating: Identify outliers (glitch / anomaly) and reject their updates to the KF.

[0211] Slope Consistency Constraint (Surge Criterion) ): Reject sudden changes that do not conform to the law of power frequency change.

[0212] ARM pre-enable: Triggering is only allowed when the amplitude is close to the threshold to avoid premature triggering.

[0213] Enable logic and final threshold decision (final decision): continuous confirmation + hysteresis hold + dual IO output.

[0214] Compared to common measurement algorithms, this algorithm offers a superior trade-off between delay and reliability: methods that only compare instantaneous thresholds offer fast response times but are sensitive to noise and glitches, making them prone to false alarms in the field; methods based on sliding RMS / RMS or integer statistics provide good noise resistance but require sufficient sample accumulation, leading to significantly increased action delays and insufficient sensitivity to short-term overvoltages; amplitude criteria relying solely on single-path filtering / estimation may exhibit significant biases during transient disturbances or when estimations fail to converge. In contrast, this dual-channel scheme suppresses glitches through consistency constraints, enhances output stability through hysteresis maintenance, and achieves rapid decision-making without requiring long-window statistics. Test results demonstrate a significant reduction in false alarms and enhanced output stability, while also significantly shortening the detection and output control delays. This makes it more suitable for power frequency overvoltage applications where high protection action speed is required.

[0215] The usability of the algorithm was basically verified using MATLAB software. The focus was on testing whether the device could stably and promptly generate a conduction control level output under typical field conditions of "gradually changing power frequency amplitude, superimposed measurement noise, and random glitches." The test used a 50Hz power frequency sine wave as the reference signal, with a sampling frequency of 20kHz. The voltage amplitude was initially maintained at 1.0 pu, and then increased linearly to 1.6 pu after a set delay to simulate the process of power frequency overvoltage gradually developing from a normal state to an abnormal state. To closely approximate the actual measurement environment, zero-mean Gaussian noise was superimposed on the test signal, and random glitches with amplitudes much higher than the fundamental frequency were injected with a low probability to cover non-ideal factors such as sampling anomalies and transient switching interference, thereby verifying the device's ability to suppress occasional interference and control the risk of false triggering.

[0216] The test outputs include: ideal power frequency voltage (as a reference true value), input voltage with noise and glitches, recorded curves of key internal quantities, and positive and negative conduction request levels (IO1 / IO2). The moment the ideal signal first instantaneously crosses the set threshold is used as the reference starting point, and the moment the device first outputs the conduction request level is used as the action moment. The difference between the two is defined as the response time index, used to measure the timeliness of detection and control output. The level output uses hold-type logic to adapt to the driving requirements of power devices such as MOSFETs: the output is held after the overvoltage condition is met and confirmed; the output is reset after the voltage drops back to the release condition to avoid frequent switching caused by jitter near the threshold. Through the above signal construction and index definition, the device's operational accuracy, noise and glitches resistance, and output control stability under gradual overvoltage scenarios can be verified simultaneously within the same test framework.

[0217] The following are waveforms obtained from a single test and an example of the initial conduction delay time, such as... Figures 2-3 As shown, to quantify the effect of improving response speed, a Monte Carlo repeated trial method was used to statistically evaluate the algorithm's response, with the number of repetitions Nsim=200. In each trial, noise and glitch sequences were independently generated and input into the same detector. Two types of trigger times were recorded: the first time the detector outputs an I / O (to determine if there is a false action before the threshold is crossed), and the second time the detector outputs an I / O after the reference threshold crossing time (to calculate the response time of the correct action). Based on this, three statistical indicators were defined: the number of premature triggers (the first I / O action occurs before the ideal signal crosses the threshold, representing the risk of false action), the number of missed triggers (failure to generate an action after the threshold crossing within the observation window, representing the risk of insufficient sensitivity or overly tight gating), and the response time distribution. The results are as follows: Figure 4 As shown.

[0218] As can be seen from the test waveforms and repeated test results, under the condition of gradually increasing power frequency amplitude and superimposed noise and random glitches, this dual-channel detection method demonstrates significant advantages: First, this scheme can effectively suppress false threshold crossings caused by single-point glitches, sampling anomalies, or switching transients. The fundamental reason is that the triggering is not determined by a single instantaneous sampling, but is simultaneously constrained by the consistency of the estimation channel and the amplitude pre-enabling threshold. This naturally shields the situation where "glitch only raises the instantaneous value but is difficult to synchronously drive the estimated quantity / amplitude state," statistically manifested as a significant reduction in the probability of erroneous operation, thereby improving the reliability and safety margin of protection actions.

[0219] Secondly, with zero missed triggers and the number of valid samples equaling the total number of trials, the algorithm consistently completes the action output after a true threshold breach occurs, indicating that the threshold setting and confirmation mechanism achieve a reasonable balance between robustness and triggerability. This is particularly crucial for protection applications: both false triggers and failures to trigger must be avoided; these statistical results probabilistically verify the engineering usability of this scheme in balancing these two aspects.

[0220] More importantly, this solution significantly reduces algorithm latency while ensuring low false triggering and zero missed triggering. The average response time is approximately 0.1657 ms, with a standard deviation of approximately 0.0939 ms, indicating that the action latency is in the sub-millisecond range with low dispersion and stable and consistent output timing. Compared with common "measurement-based" overvoltage criteria, this result has direct engineering significance: measurement-based methods often require a sufficient window length to achieve stable decision-making, naturally introducing millisecond-level or even longer waiting times; while this solution "pre-implements" anti-interference capability through dual-channel consistency and pre-enabling mechanisms, without relying on increasing the statistical window to gain robustness. Therefore, even under interference, it can complete the decision with very few confirmation points, thus significantly compressing the overall detection and output control latency. This characteristic of "low latency without sacrificing reliability" is precisely what is needed in scenarios with high protection action speed requirements (such as fast bypass, fast clamping, or fast switching of protection devices).

[0221] Furthermore, from an output perspective, the I / O provided in this solution is a level-holding conduction request, and a hysteresis condition ensures that it will not repeatedly turn on and off near the threshold due to noise jitter. This feature makes the output more "drive-friendly" and adaptable to the control requirements of power devices such as MOSFETs: once the action condition is met, it is stably set, and then reset after falling back to the release threshold, thereby reducing the risk of thermal shock and electromagnetic interference caused by frequent switching and improving the long-term operational stability of the system.

[0222] Based on the waveform phenomena and statistical indicators, it can be concluded that the dual-channel solution implemented in this paper exhibits extremely low false action rate, zero missed action rate, significantly shortened response delay and small fluctuation under strong noise and glitch interference conditions, and stable and controllable output. Therefore, it has better overall performance and engineering applicability than traditional single-channel instantaneous threshold criteria or long window measurement algorithms under complex field conditions.

[0223] Preferably, step 6 of the dual-channel voltage analysis algorithm further includes:

[0224] Step 6.1, Forward channel IO1;

[0225] Define positive candidate conditions: In the formula, Positive threshold crossing candidate; Enable detection; This serves as a marker for valid sample points; To detect voltage; This is the input threshold;

[0226] right Continuous counting:

[0227] ,

[0228] In the formula, For positive confirmation counter, To confirm the number of points, To maintain a positive state;

[0229] Positive hold release condition with hysteresis:

[0230] In the formula,

[0231] Indicates logical NOT. Represents logical OR, The release threshold;

[0232] The output is defined as: In the formula, The output level is requested for forward conduction;

[0233] Step 6.2, Negative channel IO2;

[0234] Define negative candidate conditions:

[0235] In the formula, This is a negative threshold candidate. This represents the negative input threshold.

[0236] right Continuous counting:

[0237] In the formula: For negative confirmation counters, To maintain a negative state;

[0238] Negative hold release condition:

[0239] In the formula, This is the negative release threshold;

[0240] The output is defined as: In the formula, To request the output level for negative conduction;

[0241] To prevent simultaneous conduction of positive and negative signals, a mutual exclusion constraint is applied:

[0242]

[0243] In the formula, the mutual exclusion constraint is used to ensure that only one direction is allowed to output 1 at any given time.

[0244] Preferably, the thyristor turns off naturally at the AC zero-crossing point.

[0245] Another aspect of the present invention discloses a control method for a thyristor-controlled surge arrester, comprising the following steps:

[0246] The system acquires the voltage signal across the power frequency overvoltage terminals of the thyristor-controlled surge arrester; buffers, amplifies, and performs analog-to-digital conversion on the voltage signal; performs morphological filtering and adaptive Kalman filtering in parallel; determines whether a power frequency overvoltage has occurred based on the filtering results; and triggers the corresponding polarity thyristor to conduct when the operating conditions are met.

[0247] Preferably, when performing morphological filtering and adaptive Kalman filtering in parallel, the bandwidth of the Kalman filter is increased when a voltage change is detected, and decreased in steady state.

[0248] The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention. These changes involve related technologies well known to those skilled in the art, and all of them fall within the protection scope of the present invention.

[0249] Many other changes and modifications can be made without departing from the concept and scope of this invention. It should be understood that this invention is not limited to the specific embodiments, and the scope of this invention is defined by the appended claims.

Claims

1. A thyristor-controlled surge arrester, installed between phases of the protected transmission line, characterized in that, It includes a nonlinear voltage limiting branch (1), a main protection circuit, an energy harvesting and voltage dividing module (2), and a control and detection module (5). The nonlinear voltage limiting branch (1) includes a first varistor (11) and a first parallel capacitor (12) connected in parallel with it. The main protection circuit consists of a positive thyristor conduction branch (3) and a negative thyristor conduction branch (4). The two conduction branches are connected in antiparallel with the nonlinear voltage limiting branch (1) to conduct bidirectional controlled conduction of the positive and negative half-cycles of the power frequency overvoltage at both ends of the controllable part of the thyristor switch-type controllable surge arrester. Each conduction branch includes at least one high-voltage high-current thyristor and achieves electrically isolated thyristor gate trigger control through a pulse transformer and an isolation trigger circuit. The energy harvesting and voltage divider module (2) includes an energy harvesting branch consisting of a second parallel capacitor (21) and a second varistor (22) connected in series. The second parallel capacitor (21) and the first parallel capacitor (12) together form an auxiliary capacitor voltage divider structure. The second varistor (22) is connected in series at the lower end of the second parallel capacitor (21) to harvest energy. The second varistor (22) is connected in parallel with the isolation transformer (23) to isolate the voltage on the second varistor (22) and input it into the rectifier bridge to provide energy for the energy storage capacitor connected afterward. The control and detection module (5) includes a signal conditioning circuit (51), a central processing module (52), an isolation drive circuit (53), a power supply module (54), and a capacitor voltage divider group (55). The voltage sampling capacitor voltage divider group (55) is used to collect the voltage signal across the thyristor-controlled surge arrester in real time as the input of the control algorithm. The signal conditioning circuit (51) includes a buffer amplifier, the input of which is connected to the capacitor voltage divider group (55). It is used to perform impedance transformation and amplitude conditioning on the divided voltage signal. The conditioned voltage signal is sent to the high-speed analog-to-digital converter module for sampling. The sampling voltage is obtained at the set sampling frequency and input to the central processing module (52). The central processing module (52) uses a dual-channel voltage analysis algorithm to determine whether the voltage meets the conduction conditions and the polarity of the voltage. If the set conduction conditions are met, the central processing module (52) issues an instruction according to the polarity of the overvoltage. After the instruction is processed by the isolation drive circuit (53), it drives the corresponding positive drive MOSFET (33) or negative drive MOSFET (43) to conduct, thereby performing the corresponding protection action. The power supply module (54) provides the required low-voltage DC power.

2. The thyristor-controlled surge arrester according to claim 1, characterized in that, The forward thyristor conduction branch (3) is used to handle positive half-wave overvoltage, including an energy harvesting and storage circuit, an isolation trigger circuit, and a conduction execution circuit. The energy harvesting and storage circuit includes a forward rectifier bridge (31) and a forward energy storage capacitor (32). The forward rectifier bridge (31) rectifies the AC output of the isolation transformer (23) into DC and stores it in the forward energy storage capacitor (32). The isolation trigger circuit includes a forward drive MOSFET (33) and a forward pulse transformer (34). The forward drive MOSFET (33) acts as an electronic switch to control the discharge of the forward energy storage capacitor (32), and the forward pulse transformer (34) realizes high and low voltage electrical isolation and energy transfer. The conduction execution circuit includes a positive secondary side rectifier current limiting circuit (35), a positive thyristor valve group (36), and a positive voltage equalization absorption circuit (37). The output of the positive pulse transformer (34) is shaped by the positive secondary side rectifier current limiting circuit (35) and then triggers the positive thyristor valve group (36). The valve group is composed of multiple thyristors connected in series, and each thyristor is connected in parallel with a positive voltage equalization absorption circuit (37) at both ends.

3. A thyristor-controlled surge arrester according to claim 2, characterized in that, The negative thyristor conduction branch (4) is used to handle negative half-wave overvoltage, including an energy harvesting and storage circuit, an isolation trigger circuit, and a conduction execution circuit. The energy harvesting and storage circuit includes a negative rectifier bridge (41) and a negative energy storage capacitor (42). The negative rectifier bridge (41) rectifies the AC power output from the isolation transformer (23) into DC power and stores it in the negative energy storage capacitor (42). The isolation trigger circuit includes a negative drive MOSFET (43) and a negative pulse transformer (44). The negative drive MOSFET (43) acts as an electronic switch to control the discharge of the negative energy storage capacitor (42), and the negative pulse transformer (44) realizes high and low voltage electrical isolation and energy transfer. The conduction execution circuit includes a negative secondary side rectifier current limiting circuit (45), a negative thyristor valve group (46), and a negative voltage equalization absorption circuit (47). The output of the secondary side of the negative pulse transformer (44) is shaped by the negative secondary side rectifier current limiting circuit (45) and then triggers the negative thyristor valve group (46). The valve group is composed of multiple thyristors connected in series, and each thyristor is connected in parallel with a negative voltage equalization absorption circuit (47) at both ends.

4. A thyristor-controlled surge arrester according to claim 3, characterized in that, The central processing module (52) includes a microcontroller, a digital signal processor, or a programmable logic device, which performs the following logic: Digital filtering; Construct parallel morphological filtering channels and adaptive Kalman filtering channels to perform digital filtering processing on the input sampled voltage signal; Eigenvalue calculation; Based on the filtered voltage signal, the characteristic values, namely the instantaneous voltage value and the effective voltage value, are calculated and updated in real time. Polarity and threshold discrimination: The polarity of the voltage is determined based on the sign of the instantaneous voltage value; a co-criterion is adopted, that is, the instantaneous voltage value > threshold A and the effective voltage value > threshold B.

5. A thyristor-controlled surge arrester according to any one of claims 1-4, characterized in that, The dual-channel voltage analysis algorithm includes a morphological filtering channel and an adaptive Kalman filtering channel. The morphological filtering channel performs nonlinear time-domain operations on the input sampled voltage signal to extract voltage abrupt changes, steep transition edges, and power frequency features, which are used to quickly determine whether the system has entered a power frequency overvoltage state. The Kalman filter channel is based on I / Q orthogonal state and modeled with a rotation matrix. It recursively estimates the fundamental voltage component and outputs the real-time power frequency effective value. When the morphological filter channel detects a sudden change feature exceeding the set threshold, the microcontroller dynamically adjusts the process noise covariance matrix parameter of the Kalman filter. After obtaining the voltage effective value and voltage polarity judgment result, the microcontroller generates a conduction signal according to the preset power frequency overvoltage action threshold and duration criterion. The signal is controlled by the positive or negative drive MOSFET (43) to turn on the corresponding power MOSFET, so that the energy in the positive or negative energy storage capacitor (42) is coupled to the corresponding thyristor gate through the positive or negative pulse transformer (44), thereby realizing the electrical isolation trigger between the high voltage side and the low voltage control side.

6. A thyristor-controlled surge arrester according to claim 5, characterized in that, The dual-channel voltage analysis algorithm includes the following steps: 1) Morphological switching filtering is used to remove glitches and spikes in voltage signals. It uses the following formula: ， ， ， ， In the formula, k represents the current discrete sampling time, which is the time base for the entire time-domain processing flow. The original sampling voltage is L, and the length of the structuring element is L. This is the result of performing a minimum value operation on the original sampled signal within a sliding window of length L. To The sequence is then subjected to a sliding window expansion operation to retrieve the maximum value. To perform the maximum value operation again, The final output of the morphological filtering cascade link is obtained by modifying the previous stage. The sequence is subjected to a minimum value operation within a sliding window; 2) Kalman estimation; from Extract the best consistent estimate of the power frequency sine wave to obtain the estimated instantaneous value. and estimated amplitude We employ I / Q orthogonal states and model them using rotation matrices: Define a two-dimensional state vector: In the formula, The state at time k is... To correspond to the sine component, For the corresponding cosine orthogonal components; The discrete rotational state equation and measurement equation are as follows: ， ， ， ， ， In the formula, This is the rotation state transition matrix; For the measurement matrix, For process noise, To measure noise, For measured values, take the morphological output. ; Kalman prediction: ， ， In the formula, For prior state estimation; This is a posterior estimate from the previous time step. For the prior error covariance, The posterior error covariance of the previous time step. The process noise covariance matrix; Innovation and innovation covariance: ， ， In the formula, Innovation means measuring residuals. To innovate covariance, To measure the noise variance; 3) Innovation gating; constructing normalized innovation statistics: ， In the formula, For normalized innovation, Standard deviation for innovation; Given threshold The update strategy is as follows: ， ， , In the formula, To innovate the gating threshold, , These are the posterior state estimate and the posterior covariance, respectively. When satisfied At that time, the Kalman gain and update are as follows: , ， ， In the formula, For Kalman gain, It is the identity matrix; Instantaneous and magnitude estimates are obtained from the posterior state: ， ， In the formula, To estimate the instantaneous voltage, , For the two components of the posterior state, To estimate the amplitude; 4) Slope consistency constraint; right Calculate the difference derivative: In the formula, It is an approximation of the discrete derivative; Construct the normalized slope ratio: ， In the formula, As a slope consistency index, It is the power frequency angular frequency. To prevent the lower limit of the denominator from being too small; Define the criteria for valid sample points: ， In the formula, for Threshold, This represents the logical AND operation; 5) ARM pre-enable, amplitude unlocked to avoid premature false triggering; Set the instantaneous overvoltage threshold. And give the amplitude unlock threshold: In the formula, Unlock the amplitude threshold for ARM. This is the proportionality coefficient. The threshold is used to determine the instantaneous threshold crossing. Using consecutive points Confirm unlock: ， In the formula, To unlock the counter, To unlock the icon, To confirm the number of consecutive points; , Enables final detection; 6) Enable logic and final threshold decision; To obtain the shortest detection delay, the final decision voltage is selected as follows: In the formula, For the final detection voltage, Output for morphological preprocessing; Set a release threshold. And set the final number of confirmed points as In the formula, The delayed release threshold, This is the number of points confirmed for exceeding the threshold.

7. A thyristor-controlled surge arrester according to claim 6, characterized in that, Step 6 of the dual-channel voltage analysis algorithm also includes: Step 6.1, Forward channel IO1; Define positive candidate conditions: In the formula, Positive threshold crossing candidate; Enable detection; This serves as a marker for valid sample points; To detect voltage; This is the input threshold; right Continuous counting: ， In the formula, For positive confirmation counter, To confirm the number of points, To maintain a positive state; Positive hold release condition with hysteresis: In the formula, Indicates logical NOT. Represents logical OR, The release threshold; The output is defined as: In the formula, The output level is requested for forward conduction; Step 6.2, Negative channel IO2; Define negative candidate conditions: In the formula, This is a negative threshold candidate. This represents the negative input threshold. right Continuous counting: In the formula: For negative confirmation counters, To maintain the negative state; Negative hold release condition: In the formula, This is the negative release threshold; The output is defined as: In the formula, To request the output level for negative conduction; To prevent simultaneous conduction of positive and negative signals, a mutual exclusion constraint is applied: ， In the formula, the mutual exclusion constraint is used to ensure that only one direction is allowed to output 1 at any given time.

8. A thyristor-controlled surge arrester according to claim 1, characterized in that, The thyristor turns off naturally at the AC zero-crossing point.

9. A control method for a thyristor-controlled surge arrester, characterized in that, Using a thyristor-controlled surge arrester as described in any one of claims 1-8, the following steps are performed: The system acquires the power frequency overvoltage across the thyristor-controlled surge arrester; buffers, amplifies, and performs analog-to-digital conversion on the voltage signal; and performs morphological filtering and adaptive Kalman filtering in parallel. The filter results are used to determine whether a power frequency overvoltage has occurred; when the operating conditions are met, the corresponding polarity thyristor is triggered to conduct.

10. The control method for a thyristor-controlled surge arrester according to claim 9, characterized in that, When performing morphological filtering and adaptive Kalman filtering in parallel, the bandwidth of the Kalman filter is increased when a voltage change is detected, and decreased in steady state.

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