A dual-path interleaved phase-shifting current sharing control method and system based on FPGA implementation

The dual-path interleaved phase-shifting current sharing control method implemented by FPGA solves the problem of uneven current distribution in the interleaved three-level topology, realizes dynamic current sharing regulation, and improves the stability and efficiency of high-power power conversion system.

CN122137254AInactive Publication Date: 2026-06-02WEIYUAN ENERGY TECHNOLOGY CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
WEIYUAN ENERGY TECHNOLOGY CO LTD
Filing Date
2026-05-07
Publication Date
2026-06-02
Estimated Expiration
Not applicable · inactive patent

AI Technical Summary

Technical Problem

In high-power power conversion systems, uneven current distribution in the interleaved three-level topology leads to local phase arm overheating, device aging, and a decrease in overall reliability. Existing technologies struggle to achieve effective current sharing control under load disturbances and device differences.

Method used

A dual-path interleaved phase-shifting current sharing control method based on FPGA is adopted. The duty cycle correction is calculated by current sampling and PI controller. Combined with the synchronization signal and delay signal, the PWM waveform of the second branch is generated inside the FPGA to realize dynamic current sharing regulation.

Benefits of technology

It significantly improves the system's operational stability and reliability, reduces current ripple, evens out device thermal stress, reduces switching losses, and improves system efficiency.

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Abstract

This invention discloses a dual-path interleaved phase-shift current sharing control method and system based on FPGA. The PWM on the DSP side adopts a rising-falling counting method, setting it low when the rising count reaches the comparison value and high when the falling count returns to the comparison value. The DSP outputs four sets of PWM signals in the first path to the drive circuit, and simultaneously sends two sets of PWM signals from the first branch's upper bridge arm along with the synchronization signal to the FPGA. The control gain (Gain) is sent to the FPGA via SPI communication at intervals of one power frequency cycle. After receiving the above signals, the FPGA generates and outputs four sets of PWM signals in the second branch. Leveraging the FPGA's high-speed parallel processing capabilities, abundant programmable logic and I / O resources, and strict timing determinism, this invention can achieve precise PWM phase-shift control with real-time duty cycle compensation, thereby effectively improving the system's current sharing performance and current ripple characteristics, and enhancing the efficiency and long-term operational reliability of high-power power conversion systems.
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