A filter, a filter manufacturing method, and an integrated circuit

Abstract

This application proposes a filter, a filter fabrication method, and an integrated circuit. The filter includes: a piezoelectric layer group and a substrate group; the piezoelectric layer group and the substrate group define a resonant cavity; the piezoelectric layer group includes a lower electrode, a piezoelectric layer, and an upper electrode; the substrate group includes a lower substrate layer, a dielectric layer, and a blocking layer; the filter also includes a release hole disposed through the lower substrate layer.

Description

Technical Field

[0001] This application relates to the field of filter fabrication technology, and in particular to a filter, a filter fabrication method, and an integrated circuit. Background Technology

[0002] This section is intended to provide background or context for the embodiments of this application as set forth in the claims. The description herein is not to be construed as prior art simply because it is included in this section.

[0003] A double-side bonded bulk acoustic wave (D-BAW) filter is a high-performance radio frequency acoustic device that forms a closed air cavity inside a chip through wafer-level bonding and sacrificial layer release processes. Its core structure includes top and bottom electrodes, a piezoelectric thin film, and a suspended cavity located beneath the piezoelectric stack. This cavity is typically formed by selectively etching a pre-deposited sacrificial layer. In this process, the release orifice serves as the sole channel for etchant entry and byproduct exit; its design and fabrication method directly determine the device's performance, yield, and reliability.

[0004] In existing D-BAW technology, such as Figure 1 As shown, release holes are generally fabricated on the front side of the wafer (i.e., the functional side of the device). Specifically, after patterning the upper electrode and piezoelectric layer, micron-sized vias are created above or around the resonant region using photolithography and dry etching to connect to the sacrificial layer below. However, this front-side release hole approach has several insurmountable technical problems: First, the release holes penetrate the functional layer, which can easily lead to electrochemical corrosion. During wet or gas-phase release processes, etching media (such as HF vapor or solution) may remain in the channels, coming into long-term contact with the upper electrode metal (such as Al or Mo), inducing local electrochemical reactions, resulting in electrode degradation and interface delamination, and significantly reducing the long-term reliability of the device.

[0005] Second, the release process is lengthy, posing a risk of leakage and contamination. To ensure complete removal of the sacrificial layer, the etching time needs to be extended. However, prolonged exposure can cause the etching solution to seep from the front release hole onto the chip surface, contaminating surrounding circuits or the packaged area, affecting batch consistency, and even leading to device failure.

[0006] Third, after release, open holes remain on the front side, severely restricting subsequent process integration. Because the release holes are located on the top layer of the device and exposed on the surface, it is difficult to perform subsequent processes such as passivation, rewiring, multilayer interconnection, or wafer-level packaging after the release step. On the one hand, stress concentration is prone to occur at the edge of the hole, leading to film cracking; on the other hand, subsequent deposition or etching processes are difficult to uniformly cover or precisely control in the hole area. Usually, existing processes terminate after release, lacking compatibility with advanced packaging or integration processes.

[0007] Fourth, release holes often need to be placed near the resonant region, and may even partially occupy the effective resonant area. To ensure that the sacrificial layer is fully released, release holes are often densely distributed around the resonant unit, inevitably encroaching on the area that could originally be used for resonance. This not only reduces the effective electromechanical coupling area, but also disrupts the uniformity of the electric field distribution, excites transverse vibrations or edge modes, leading to increased insertion loss, decreased quality factor (Q value), and limiting the improvement of high-frequency performance.

[0008] In summary, the existing D-BAW filter technology for fabricating release holes on the front side has significant drawbacks in terms of reliability, process scalability, and electroacoustic performance.

[0009] Therefore, there is an urgent need to propose a filter and its fabrication method that can solve the above-mentioned technical problems. Summary of the Invention

[0010] This application provides a filter, a filter fabrication method, and an integrated circuit to address at least one technical drawback of the prior art in terms of reliability, process scalability, and electroacoustic performance.

[0011] In a first aspect, this application provides a filter, comprising: a piezoelectric layer group and a substrate group; The piezoelectric layer group and the substrate group define a resonant cavity; The piezoelectric layer assembly includes a lower electrode, a piezoelectric layer, and an upper electrode; the substrate assembly includes a lower substrate layer, a dielectric layer, and a barrier layer. The filter also includes a release hole disposed through the lower substrate layer.

[0012] Furthermore, the area of ​​the release hole is R, 10 μm. 2 <R<500μm 2 ; Furthermore, the number of release holes corresponding to the resonant cavity is N, where N > 5; the release holes are evenly spaced.

[0013] Furthermore, the orthographic projection of the release hole onto the plane of the lower base layer is at least one of a circle, an ellipse, or a square.

[0014] Furthermore, the orthographic projection of the upper electrode onto the piezoelectric layer overlaps with a portion of the piezoelectric layer; the orthographic projection of the lower electrode onto the piezoelectric layer overlaps with a portion of the piezoelectric layer.

[0015] Secondly, this application provides a filter fabrication method for fabricating the filter as described above, the method comprising: A piezoelectric layer assembly is provided, the piezoelectric layer assembly comprising an upper electrode, a piezoelectric layer, and a lower electrode; After depositing and etching a cavity-filling layer on the lower electrode, a substrate assembly is formed, the substrate assembly including a lower barrier layer, a dielectric layer and a lower substrate layer; Etching the substrate assembly from the lower substrate layer to the cavity filling layer forms a release hole; Based on the release hole, the target cavity filling layer is released to form a resonant cavity, and the target cavity filling layer is located in the space defined by the piezoelectric layer group and the substrate group.

[0016] Furthermore, the release hole includes a first release hole and a second release hole that are connected together; the first release hole penetrates the substrate assembly; the depth of the second release hole is X, where X < Y / 2, and Y is the thickness of the target cavity filling layer.

[0017] Furthermore, the method further includes: providing an upper substrate layer; sequentially forming a first electrode layer, a piezoelectric layer, and a second electrode layer based on the upper substrate layer; etching the second electrode layer to form a lower electrode; removing the upper substrate layer and etching the first electrode layer to form the upper electrode, wherein the upper electrode, the piezoelectric layer, and the lower electrode form a piezoelectric layer group.

[0018] Furthermore, the method further includes: before etching the substrate assembly from the lower substrate layer to the cavity filling layer to form a release hole, covering the piezoelectric layer assembly with a protective film; and after releasing the target cavity filling layer based on the release hole to form a resonant cavity, removing the protective film.

[0019] Thirdly, this application provides an integrated circuit that includes the filter as described above.

[0020] This application provides a filter, a filter fabrication method, and an integrated circuit. The filter includes a piezoelectric layer group and a substrate group; the piezoelectric layer group and the substrate group define a resonant cavity; the piezoelectric layer group includes a lower electrode, a piezoelectric layer, and an upper electrode; the substrate group includes a lower substrate layer, a dielectric layer, and a barrier layer; the filter further includes a release hole disposed through the lower substrate layer. This invention, by placing the release hole in a non-front-side area of ​​the wafer and optimizing its layout and density, has the following significant advantages compared to existing D-BAW technology: First, the release holes are no longer located in the functional layer area on the front side of the wafer, avoiding the risk of electrochemical corrosion caused by the release holes penetrating the top electrode and piezoelectric layer. At the same time, since the release process can be completed in a shorter time (by reasonably increasing the density of release holes to improve the etchant diffusion efficiency), the sacrificial layer removal time is effectively shortened, and the leakage and liquid residue problems caused by long-term exposure during wet or gas phase release are significantly reduced.

[0021] Secondly, the absence of any release holes on the front side of the wafer allows it to remain compatible with subsequent standard semiconductor process steps such as photolithography, etching, passivation, or multilayer interconnects after the release process is completed, significantly enhancing process integration capabilities. This feature is particularly helpful in manufacturing complex RF modules such as multiplexers, improving overall yield and product consistency.

[0022] Furthermore, since the release hole completely avoids the resonant region, the effective resonant area can be maximized, which not only improves the electromechanical coupling efficiency and Q value of the device, but also further reduces the chip size of a single filter. This reduces material costs and packaging area while ensuring performance, which is conducive to the miniaturization and mass production economy of highly integrated 5G RF front-end modules.

[0023] In summary, this invention addresses the three major bottlenecks of existing D-BAW release holes—reliability, process compatibility, and area utilization—by focusing on the location, density, and structural design of the release holes. It provides a practical and feasible technical path for the large-scale manufacturing of high-performance, high-yield, and low-cost filters. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a schematic diagram of the structure of a filter in the prior art; Figure 2 This is a schematic diagram of the filter structure provided in this application; Figure 3 A schematic flowchart illustrating the filter fabrication method provided in this application; Figure 4 A schematic diagram of the process structure prepared by the filter fabrication method proposed in this application (I); Figure 5A schematic diagram (II) of the process structure of the filter fabrication method provided in one embodiment of this application. Figure 6 A schematic diagram (III) of the process structure of the filter fabrication method provided in an embodiment of this application; Figure 7 A schematic diagram (IV) of the process structure of the filter fabrication method provided in an embodiment of this application; Figure 8 A schematic diagram (V) of the process structure of the filter fabrication method provided in an embodiment of this application; Figure 9 A schematic diagram (VI) of the process structure of the filter fabrication method provided in an embodiment of this application; Figure 10 This is a top view of a filter provided in an embodiment of this application.

[0026] The same or similar reference numerals in the accompanying drawings represent the same or similar parts.

[0027] 11. Upper electrode; 12. Piezoelectric layer; 13. Lower electrode; 14. Cavity filling layer; 15. Barrier layer; 16. Dielectric layer; 17. Lower substrate layer; 18. Release hole Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0029] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Example 1

[0030] Figure 2 An embodiment of this application provides a filter comprising: a piezoelectric layer group and a substrate group; The piezoelectric layer group and the substrate group define a resonant cavity; The piezoelectric layer assembly includes a lower electrode 13, a piezoelectric layer 12, and an upper electrode 11; the substrate assembly includes a lower substrate layer 17, a dielectric layer 16, and a barrier layer 15. The filter also includes a release hole 18 disposed through the lower substrate layer 17.

[0031] It is important to understand that in practical applications, the resonant cavity is larger than the resonant region. The resonant region is the overlapping area of ​​the projection of the upper electrode 11 onto the plane of the substrate layer 17 and the projection of the lower electrode onto the plane of the substrate layer 17 within the resonant cavity.

[0032] The release hole 18 of the device penetrating the lower substrate layer 17 described in this application can be located at any position in the resonant cavity (i.e., it can be located in the resonant region and the non-resonant region); it overcomes the limitation in the prior art (where the release hole is set to penetrate the upper electrode 11 and the piezoelectric layer 12 of the piezoelectric layer group) that the release hole 18 can only be located in the non-resonant region of the resonant cavity, thereby improving the fabrication yield of the filter and reducing the fabrication complexity.

[0033] Specifically, the material of the upper electrode 11 can be various conductive metal materials, or a combination of multiple conductive metal materials. Optionally, the materials of the upper electrode 11 and the lower electrode 13 include, but are not limited to, molybdenum (Mo), aluminum (Al), copper (Cu), platinum (Pt), tantalum (Ta), tungsten (W), etc.

[0034] Specifically, the material of the piezoelectric layer 12 can be any material with piezoelectric properties. Optionally, the material of the piezoelectric layer 12 includes, but is not limited to, aluminum nitride (AlN), AlN doped with rare earth elements such as scandium, erbium, and lanthanum, zinc oxide (ZnO), or lithium niobate (LiNbO3).

[0035] The filter disclosed in this embodiment changes the prior art's technical solution of placing the release hole 18 on the front side of the wafer; the release hole 18 is no longer opened in the functional layer area on the front side of the wafer, avoiding the risk of electrochemical corrosion caused by the release hole 18 penetrating the upper electrode 11 and the piezoelectric layer 12; at the same time, since the release process can be completed in a shorter time (by reasonably increasing the density of the release hole 18 to improve the etchant diffusion efficiency), the sacrificial layer removal time is effectively shortened, and the leakage and liquid residue problems caused by long-term exposure during wet or gas phase release are significantly reduced.

[0036] In one embodiment, the area of ​​the release hole 18 is R, 10 μm. 2 <R<500μm 2 .

[0037] Specifically, when, 10μm 2 When the value is greater than R, the etching solution exchange efficiency decreases exponentially, and the prolonged release time leads to uncontrollable lateral corrosion; when 500m 2 When the value is less than R, the mechanical strength of the lower substrate 17 decreases, and stress fracture is more likely to occur during subsequent CMP or bonding processes.

[0038] In one embodiment, the number of release holes 18 corresponding to the resonant cavity is N, where N > 5; the release holes 18 are evenly distributed.

[0039] Specifically, if the release holes 18 are too large or too dense, the effective support area of ​​the Frame area (support area / frame area) will be reduced, which will cause the suspended film to collapse or stick after release due to surface tension or residual hardness. If the release holes 18 are too small, although the structure is strong, if the number is insufficient, the density still needs to be increased, which may indirectly weaken the structure.

[0040] This embodiment controls the area of ​​the release hole 18 within the above-mentioned range, ensuring efficient release of the target cavity filling layer while effectively suppressing acoustic energy leakage, maintaining the mechanical stability of the resonant cavity, and facilitating the implementation of subsequent sealing processes, thereby taking into account device performance, reliability, and manufacturing yield.

[0041] In one embodiment, the orthographic projection of the release hole 18 onto the plane containing the lower base layer 17 is at least one of a circle, an ellipse, or a square. For example... Figure 10 The diagram shown illustrates that the release hole 18 is circular.

[0042] Specifically, the orthographic projection of the release hole 18 onto the plane of the lower substrate layer 17 is circular or elliptical to eliminate stress concentration caused by sharp corners and improve the mechanical stability of the suspended structure. At the same time, it is conducive to the uniform implementation of the etching process and the efficient diffusion of the released gas, and facilitates the conformal coverage of the subsequent sealing layer, thereby improving the device yield and long-term reliability.

[0043] Specifically, when the release hole 18 is square, in some design processes based on rectangular frames, squares are easier to align and the layout design is relatively simple; and when using special processes for etching, square holes are easier to control to be vertical.

[0044] It should be understood that this application does not limit the shape of the orthographic projection of the release hole 18 onto the plane where the lower base layer 17 is located, and those skilled in the art can make a reasonable choice based on the actual situation.

[0045] In one embodiment, the orthographic projection of the upper electrode 11 onto the piezoelectric layer 12 overlaps with a portion of the piezoelectric layer 12; the orthographic projection of the lower electrode 13 onto the piezoelectric layer 12 overlaps with a portion of the piezoelectric layer 12.

[0046] like Figure 7 , Figure 8 , Figure 9 and Figure 2 As shown, in one embodiment, the barrier layer 15 includes a first barrier layer and a second barrier layer, the first barrier layer being in contact with the piezoelectric layer 12 and the second barrier layer being in contact with the lower electrode 13. Example 2

[0047] like Figure 3 As shown, this embodiment provides a filter fabrication method for fabricating the filter as described in Embodiment 1. Figures 4-9 as well as Figure 2 This is a schematic diagram of the filter structure for each step of the filter fabrication method, which includes: Step S201: Provide a piezoelectric layer assembly, the piezoelectric layer assembly including an upper electrode 11, a piezoelectric layer 12 and a lower electrode 13; Step S202: After depositing and etching the cavity filling layer 14 on the lower electrode 13, a substrate group is formed, the substrate group including a lower barrier layer 15, a dielectric layer 16 and a lower substrate layer 17. Step S203: Etch the substrate assembly from the lower substrate layer 17 to the cavity filling layer 14 to form a release hole 18; Specifically, during the etching process from the lower substrate layer 17 to the cavity filling layer 14 to form the release hole 18, the etching process typically employs dry etching, such as reactive ion etching (RIE) or inductively coupled plasma etching (ICP). This process provides high selectivity and good directionality to ensure precise stopping on the cavity filling layer without damaging the underlying material. It is important to control the composition and flow rate of the etching gas, the RF power, the pressure, and the etching time to avoid over-etching or under-etching, and to ensure the smoothness and perpendicularity of the sidewalls of the release hole 18. Furthermore, the etching endpoint needs to be monitored to ensure the positional and dimensional accuracy of the release hole.

[0048] Step S204: Release the target cavity filling layer based on the release hole 18 to form a resonant cavity, wherein the target cavity filling layer is located in the space defined by the piezoelectric layer group and the substrate group.

[0049] Specifically, the material of the target cavity filling layer can be PSG or BPSG, etc.

[0050] In one embodiment, the resonant cavity is formed by releasing the target cavity filling layer based on the release hole 18, including: when the material of the cavity filling layer 18 is PSG (phosphosilicate glass) or BPSG (borophosphosilicate glass), the cavity filling layer (target filling layer) in the resonant space is released through the release hole 18 by a vapor phase HF etching process.

[0051] In one embodiment, the release hole 18 includes a first release hole 18 and a second release hole 18 that are connected together; the first release hole 18 penetrates the substrate group; the depth of the second release hole 18 is X, where X < Y / 2, and Y is the thickness of the target cavity filling layer.

[0052] In one embodiment, the method further includes: providing an upper substrate layer; sequentially forming a first electrode layer, a piezoelectric layer 12, and a second electrode layer based on the upper substrate layer; etching the second electrode layer to form a lower electrode 13; removing the upper substrate layer and etching the first electrode layer to form the upper electrode 11, wherein the upper electrode 11, the piezoelectric layer 12, and the lower electrode 13 form a piezoelectric layer group.

[0053] Specifically, the first electrode layer and the second electrode layer refer to the entire deposited electrode layer, that is, the orthogonal projection of the first electrode layer and the second electrode layer on the plane where the lower substrate layer 17 is located coincides with the lower substrate layer 17; the first electrode layer and the second electrode layer proposed in this application are intermediate products for forming the upper electrode and the lower electrode, that is, after etching away a portion of the first electrode layer and the second electrode layer, the corresponding upper electrode and the lower electrode are formed.

[0054] In one embodiment, the method further includes: covering the piezoelectric layer group with a protective film before etching the substrate group from the lower substrate layer 17 to the cavity filling layer 14 to form the release hole 18; and removing the protective film after releasing the target cavity filling layer based on the release hole 18 to form a resonant cavity. Example 3

[0055] This embodiment provides an integrated circuit that includes the filter as described in Embodiment 1.

[0056] In one embodiment, the filter can be prepared by the filter preparation method described in Example 2, or it can be prepared by a method different from that described in Example 2.

[0057] The present invention has provided a detailed description of a filter, a filter preparation method, and an integrated circuit. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

[0058] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0059] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that elements inherent to a process, method, article, or apparatus that comprises a list of elements, or elements inherent to such processes, methods, articles, or apparatus, are also included. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0060] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A filter, characterized in that, The filter comprises: a piezoelectric layer group and a substrate group; The piezoelectric layer group and the substrate group define a resonant cavity; The piezoelectric layer assembly includes a lower electrode, a piezoelectric layer, and an upper electrode; the substrate assembly includes a lower substrate layer, a dielectric layer, and a barrier layer. The filter also includes a release hole disposed through the lower substrate layer.

2. The filter according to claim 1, characterized in that, The area of ​​the release hole is R, 10 μm. 2 <R<500μm 2 .

3. The filter according to claim 1 or 2, characterized in that, The number of release holes corresponding to the resonant cavity is N, where N > 5; the release holes are evenly spaced.

4. The filter according to claim 3, characterized in that, The orthographic projection of the release hole onto the plane of the lower base layer is at least one of a circle, an ellipse, or a square.

5. The filter according to claim 4, characterized in that, The orthographic projection of the upper electrode onto the piezoelectric layer overlaps with a portion of the piezoelectric layer; the orthographic projection of the lower electrode onto the piezoelectric layer overlaps with a portion of the piezoelectric layer.

6. A method for fabricating a filter, characterized in that, The method for preparing a filter according to any one of claims 1 to 5 comprises: A piezoelectric layer assembly is provided, the piezoelectric layer assembly comprising an upper electrode, a piezoelectric layer, and a lower electrode; After depositing and etching a cavity-filling layer on the lower electrode, a substrate assembly is formed, the substrate assembly including a lower barrier layer, a dielectric layer and a lower substrate layer; Etching the substrate assembly from the lower substrate layer to the cavity filling layer forms a release hole; Based on the release hole, the target cavity filling layer is released to form a resonant cavity, and the target cavity filling layer is located in the space defined by the piezoelectric layer group and the substrate group.

7. The filter fabrication method according to claim 6, characterized in that, The release hole includes a first release hole and a second release hole that are connected together; The first release hole penetrates the substrate assembly; The depth of the second release hole is X, where X < Y / 2, and Y is the thickness of the target cavity filling layer.

8. The filter fabrication method according to claim 6 or 7, characterized in that, The method further includes: Provide an upper base layer; A first electrode layer, a piezoelectric layer, and a second electrode layer are sequentially formed based on the upper substrate layer; The second electrode layer is etched to form the lower electrode; The upper substrate layer is removed and the first electrode layer is etched to form the upper electrode. The upper electrode, the piezoelectric layer, and the lower electrode form a piezoelectric layer group.

9. The filter fabrication method according to claim 8, characterized in that, The method further includes: From the time the substrate assembly is etched from the lower substrate layer to the time the cavity filling layer forms the release hole, a protective film is applied to the piezoelectric layer assembly; After the target cavity filling layer is released based on the release hole to form a resonant cavity, the protective film is removed.

10. An integrated circuit, characterized in that, The integrated circuit includes the filter as described in any one of claims 1 to 5.

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