A method for fabricating a low-voltage p-GaN gate HEMT device

Abstract

This invention relates to a method for manufacturing a low-voltage p-GaN gate HEMT device. The method includes providing a p-GaN gate epitaxial structure, forming a silicon dioxide hard mask on its surface and etching to obtain a p-GaN pattern for the gate region; subjecting the exposed AlGaN surface after etching to alkaline and acidic treatments sequentially without forming gate metal; subsequently forming openings in the gate metal pattern using a negative photoresist lift-off process, depositing gate metal, and performing a lift-off process to create a shoulder structure at the gate metal edge corresponding to the unetched p-GaN region. Through this process flow, effective control of the gate edge structure is achieved, reducing the risk of gate leakage and improving device consistency and reliability.

Description

Technical Field

[0001] This invention relates to the technical field of semiconductor device manufacturing, and in particular to a method for manufacturing a low-voltage p-GaN gate HEMT device. Background Technology

[0002] Gallium nitride (GaN) high electron mobility transistors (HEP transistors) have been widely used in power electronics and radio frequency (RF) devices due to their advantages such as high breakdown electric field strength, high carrier mobility, and low switching losses. To meet the application requirements of enhancement-mode devices, employing a p-GaN gate structure to achieve normally-off characteristics has become one of the mainstream technical approaches.

[0003] In p-GaN gate gallium nitride devices, the gate structure is typically formed by selectively etching the p-GaN gate layer to create the gate region pattern, and then depositing gate metal on it to achieve electric field control of the channel. For low-voltage p-GaN gate devices, due to the relatively large total gate length and short spacing between the gate and drain, surface leakage channels are easily formed at the gate edge and its sidewalls. Therefore, controlling the gate leakage current becomes a key factor affecting the switching characteristics and reliability of the device.

[0004] In existing technologies, to reduce leakage current at the gate edge, a self-aligned process is typically used to form a shoulder region of a certain width between the gate metal and the edge of the p-GaN pattern. This type of self-aligned process generally requires first depositing a dielectric layer such as silicon dioxide, then forming a sidewall structure through anisotropic etching, and finally removing excess dielectric layer to obtain the desired shoulder morphology. This process involves numerous steps, places high demands on etching uniformity and dimensional control, and inevitably introduces etching damage into the shoulder region, easily affecting the surface electrical properties of the device. Furthermore, since the size of the shoulder region is mainly indirectly determined by the sidewall etching process of the dielectric layer, its critical size consistency is easily affected by process fluctuations, which is detrimental to the control of device parameter consistency within the wafer.

[0005] On the other hand, after the p-GaN gate layer is etched, the exposed aluminum gallium nitride (AGaN) barrier layer surface usually needs to be cleaned or treated to improve the electrical performance of the gate interface. However, in some existing manufacturing processes, the process sequence of the interface cleaning step and the gate metal formation step is not well arranged. During the cleaning process, the gate metal may be exposed to alkaline or acidic solutions, causing corrosion, dissolution, or migration of the metal, and forming residual contamination on the AGaN barrier layer surface. This increases the risk of gate leakage and affects the long-term stability of the device.

[0006] Therefore, how to rationally organize the process sequence of p-GaN gate etching, interface treatment, and gate metal formation without introducing complex self-aligned dielectric sidewall processes, while reducing gate leakage current, simplifying the manufacturing process, and improving dimensional consistency, remains a pressing technical problem to be solved in the field of p-GaN gate gallium nitride device manufacturing. Summary of the Invention

[0007] The purpose of this invention is to overcome the above-mentioned problems in the prior art and provide a method for manufacturing low-voltage p-GaN gate HEMT devices, so as to simplify the manufacturing process and improve device consistency while reducing gate leakage current.

[0008] To achieve the above objectives, the present invention provides a method for manufacturing a low-voltage p-GaN gate HEMT device, comprising the following steps: S1: Provide a low-voltage p-GaN gate epitaxial structure; the low-voltage p-GaN gate epitaxial structure includes, from bottom to top, a substrate, a GaN channel layer, an AlGaN barrier layer and a p-GaN gate layer; S2: A SiO2 layer is formed on the surface of the p-GaN gate epitaxial structure; S3: The SiO2 layer is patterned by photolithography, and the SiO2 layer is etched using the pattern as a mask to obtain a SiO2 hard mask; S4: Using the SiO2 hard mask as a mask, p-GaN is etched to form the p-GaN pattern of the gate region; S5: Remove the SiO2 hard mask, and sequentially treat the surface of the AlGaN barrier layer exposed after etching with alkaline solution and acidic solution. S6: An opening for forming the gate metal pattern is created using a negative photoresist stripping process; S7: Deposit gate metal TiN to cover the opening and its surrounding area; S8: Perform a stripping process to remove non-gate TiN and form a shoulder structure at the gate metal edge corresponding to the unetched p-GaN region; The shoulder structure is a stepped coverage area of ​​the gate metal on the outer side of the p-GaN pattern edge.

[0009] As a further improvement of the present invention, the process for forming the SiO2 layer in step S2 is plasma-enhanced chemical vapor deposition or low-pressure chemical vapor deposition, and the thickness of the SiO2 layer is 20-200 nm.

[0010] As a further improvement of the present invention, the photolithography in step S3 includes sequentially coating photoresist, soft baking, exposure, development and post-baking. After development, an opening pattern corresponding to the gate region is formed on the SiO2 layer. The etching process of the SiO2 layer in step S3 is reactive ion etching or inductively coupled plasma etching. The etching gas includes one or more of CHF3, CF4, and C5F8 combined with O2.

[0011] As a further improvement of the present invention, the etching process of p-GaN in step S4 is inductively coupled plasma etching, and the etching gas includes one or more of Cl2, BCl3, and SiCl4 combined with Ar.

[0012] As a further improvement of the present invention, the process of removing the hard mask in step S5 includes removing the hard mask using a fluorine-containing wet etching solution, wherein the fluorine-containing wet etching solution is a hydrofluoric acid solution or a buffered oxide etching solution.

[0013] As a further improvement of the present invention, the alkaline solution is one of ammonia solution, tetramethylammonium hydroxide solution or potassium hydroxide solution; the acidic solution is one of hydrochloric acid solution, sulfuric acid solution or citric acid solution.

[0014] As a further improvement of the present invention, the alkaline solution treatment temperature is 20-60°C and the treatment time is 10-300s, and the acidic solution treatment temperature is 20-60°C and the treatment time is 10-300s.

[0015] As a further improvement of the present invention, the negative photoresist stripping process in step S6 includes negative photoresist coating, soft baking, exposure, post-baking, development and hard baking in sequence. After development, an opening for the gate metal pattern is formed, and a reverse-cutting profile is formed on the sidewall of the opening.

[0016] As a further improvement of the present invention, the negative photoresist is a negative photoresist containing epoxy groups or a chemically amplified negative photoresist, and the thickness of the negative photoresist is 0.3 to 3.0 μm.

[0017] As a further improvement of the present invention, the process for depositing gate metal TiN in step S7 is physical vapor deposition, wherein the physical vapor deposition is DC magnetron sputtering or radio frequency sputtering, and the thickness of the deposited TiN is 10-200 nm. The stripping process in step S8 includes immersion in an organic stripping solution combined with ultrasound or spraying, wherein the organic stripping solution includes one or more of N-methylpyrrolidone, dimethyl sulfoxide, or propylene glycol methyl ether acetate.

[0018] The present invention, by adopting the above technical solution, has the following beneficial effects: First, this invention explicitly limits the interface treatment step of the AlGaN barrier layer surface exposed after etching to before gate metal deposition, and adopts a sequential treatment method using alkaline and acidic solutions. This avoids the gate metal being exposed to the chemical solution environment during the cleaning process. This process organization breaks the conventional arrangement in existing manufacturing processes where interface treatment and gate metal overlap or intersect, reducing the possibility of metal dissolving, migrating, and redepositing on the AlGaN surface in alkaline or acidic environments, and suppressing the formation of leakage channels at the gate edge caused by metal residue from the source.

[0019] Secondly, this invention defines the gate metal pattern using a negative photoresist lift-off process. After the gate metal is deposited and lift-off is completed, a shoulder structure corresponding to the unetched p-GaN region naturally forms at the edge of the gate metal. The formation of this shoulder structure does not depend on the sidewall etching process of the dielectric layer, but is determined by the photolithographic pattern and the lift-off boundary. This avoids the etching damage that is inevitably introduced by etching the shoulder region in traditional self-aligned dielectric sidewall processes, thus preserving a more complete material interface state at the edge of the gate region.

[0020] Furthermore, since the shoulder structure is not passively formed through anisotropic etching, but is directly defined by the photolithographic pattern, its geometric dimensions are mainly controlled by the photolithographic resolution and the lift-off process, and are no longer affected by the superposition of dielectric layer thickness, etching selectivity, and etching anisotropic fluctuations. This results in a more predictable size distribution of the gate metal edge structure within the wafer, which helps to reduce the dispersion of electrical parameters between devices caused by differences in the gate edge structure.

[0021] Furthermore, by moving the interface processing step forward and decoupling it from the gate metal formation step, this invention also omits the dielectric layer deposition, sidewall etching, and subsequent removal steps in the traditional self-aligned process. This transforms the gate formation process from a coupled process of multiple depositions, etchings, and removals into a sequential process chain centered on photolithography and lift-off, reducing dependence on the etching process window and improving the repeatability and controllability of the overall process route under mass production conditions. Attached Figure Description

[0022] Figure 1 This is a process flow diagram of the manufacturing method of the low-voltage p-GaN gate HEMT device in Example 1.

[0023] Figure 2 The graph shows a comparison of the drain-to-gate leakage current performance of the low-voltage p-GaN gate HEMT devices prepared in Example 1 and Comparative Example 1. Detailed Implementation

[0024] The following provides a detailed description of specific embodiments of the present invention. It should be understood that the specific embodiments described herein are for illustrative and explanatory purposes only and are not intended to limit the scope of the invention.

[0025] Unless otherwise defined, all scientific and technical terms used in this invention have the same meaning as commonly understood by one of ordinary skill in the art.

[0026] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0027] Unless otherwise specified, all materials and reagents used in the following examples are commercially available.

[0028] The present invention will now be described in detail with reference to specific embodiments, which are intended to understand rather than limit the invention.

[0029] Example 1 refer to Figure 1 This embodiment provides a method for manufacturing a low-voltage p-GaN gate HEMT device, which includes the following steps.

[0030] S1: Provides a low-voltage p-GaN gate epitaxial wafer. The low-voltage p-GaN gate epitaxial structure includes, from bottom to top, a substrate, a GaN channel layer, an AlGaN barrier layer, and a p-GaN gate layer.

[0031] The substrate is a silicon substrate, the AlGaN barrier layer is used to form a two-dimensional electron gas, and the p-GaN gate layer is used to realize the normally-off characteristics of the device.

[0032] S2: A SiO2 layer is deposited on the surface of the p-GaN gate epitaxial structure using plasma-enhanced chemical vapor deposition (PECVD) as a protective layer and hard mask layer for subsequent p-GaN gate etching. The thickness of the SiO2 layer is 20–200 nm. In this embodiment, the thickness is preferably 100 nm.

[0033] S3: Photoresist coating, soft baking, exposure, development, and post-baking processes are sequentially performed on the surface of the SiO2 layer to form a photolithographic pattern corresponding to the gate region on the SiO2 layer. Subsequently, reactive ion etching (RIE) is used to etch the SiO2 layer using a mixture of CHF4 and O2 as the etching gas. After etching, a SiO2 hard mask is obtained.

[0034] S4: Using the SiO2 hard mask obtained in step S3 as the etching mask, the p-GaN gate layer in the exposed area is etched using inductively coupled plasma etching (ICP) process. The etching gas is a mixture of Cl2, BCl3 and Ar.

[0035] The etching endpoint is controlled by pre-calibrating the etching time and rate, and confirmed by plasma emission spectroscopy monitoring during the etching process. The etching process is terminated when the p-GaN gate layer is completely removed and the AlGaN barrier layer surface is exposed.

[0036] S5: After completing the p-GaN gate etching, the residual SiO2 hard mask is removed using buffered oxide etchant (BOE). Subsequently, without depositing gate metal, the surface of the AlGaN barrier layer exposed after p-GaN etching is treated sequentially with tetramethylammonium hydroxide (TMAH) aqueous solution and dilute hydrochloric acid solution.

[0037] The process involves TMAH treatment followed by rinsing with deionized water, then treatment with dilute hydrochloric acid, followed by rinsing again and drying to complete the cleaning and stabilization of the gate interface.

[0038] After the interface treatment is completed, it can be verified by changes in surface contact angle, surface electrical stability, or the uniformity of subsequent gate metal deposition. When no abnormal adhesion or local detachment occurs on the surface of the treated AlGaN barrier layer during the subsequent gate metal deposition process, the interface treatment can be considered to have met the process requirements.

[0039] S6: After interface treatment, an epoxy-based negative photoresist is coated onto the wafer surface. The wafer is then subjected to a series of processes including soft baking, exposure, post-baking, development, and hard baking. After development, an opening for the gate metal pattern is formed. By adjusting the exposure dose and post-baking conditions, the photoresist forms a reverse-cut profile that is wider at the top and narrower at the bottom on the sidewalls of the opening after development.

[0040] S7: A gate metal TiN is deposited on the wafer surface using a DC magnetron sputtering process, so that the TiN covers the gate metal pattern opening and its surrounding area. The thickness of the TiN is 10-200 nm. In this embodiment, the thickness is 50 nm.

[0041] S8: Immerse the wafer with deposited TiN in N-methylpyrrolidone (NMP) and perform a lift-off process using ultrasound to remove the negative photoresist and the TiN in the non-gate region above it, leaving only the TiN gate metal structure in the gate region.

[0042] After stripping, the gate metal forms a stepped overlay structure at its edge corresponding to the unetched p-GaN region outside the edge of the p-GaN pattern, i.e., a shoulder structure.

[0043] Comparative Example 1 This comparative example discloses a method for manufacturing a p-GaN gate HEMT device. The difference between this method and Example 1 is that the gate edge structure is formed using a self-aligned process with a silicon dioxide sidewall spacer (SiO2 spacer), and the interface cleaning step and the gate metal formation step overlap in the process sequence. The specific steps are as follows: (1) The epitaxial structure provides a p-GaN gate epitaxial wafer with the same structure as in Example 1. The p-GaN pattern of the gate region is formed using a silicon dioxide hard mask and a p-GaN etching process, so that the surface of the aluminum gallium nitride barrier layer is exposed after etching. The endpoint of the p-GaN etching is controlled by pre-calibrating the etching time and etching rate, and confirmed by plasma emission spectrum monitoring during the etching process.

[0044] (2) A silicon dioxide dielectric layer is deposited integrally. After forming the gate region p-GaN pattern, a silicon dioxide dielectric layer is deposited integrally on the wafer surface. The silicon dioxide dielectric layer covers the top surface and sidewalls of the gate region p-GaN pattern, as well as the outer surface of the gate region. The silicon dioxide dielectric layer is formed using plasma-enhanced chemical vapor deposition. The thickness of the silicon dioxide dielectric layer is selected to be 50–300 nm so that the sidewall spacer layer formed subsequently has a identifiable sidewall width.

[0045] (3) Anisotropic etching is used to form the SiO2 spacer sidewall spacer layer. The silicon dioxide dielectric layer is anisotropically etched using reactive ion etching or inductively coupled plasma etching. The etching conditions are controlled to have a preferential etching rate for silicon dioxide to remove silicon dioxide on the horizontal surface and retain the silicon dioxide sidewall spacer layer on the sidewall of the p-GaN pattern in the gate region, thereby forming the SiO2 spacer structure. The formation of the SiO2 spacer is determined by the thickness of the silicon dioxide dielectric layer and the degree of anisotropic etching. Those skilled in the art can achieve stable formation of the sidewall spacer layer by adjusting conventional etching processes.

[0046] (4) Interface cleaning and gate metal formation: After the SiO2 spacer is formed, an interface cleaning step is performed on the surface of the etched exposed aluminum gallium nitride barrier layer. Subsequently, gate metal is deposited to cover the gate region and be adjacent to the SiO2 spacer structure, thus completing the gate structure fabrication. The interface cleaning may include alkaline solution treatment and acidic solution treatment, followed by rinsing and drying. The gate metal deposition is formed using a physical vapor deposition process.

[0047] (5) Spacer removal process: After the gate metal deposition is completed and the gate structure is formed, the SiO2 spacer is removed using a fluorine-containing wet etching solution to expose the edge region of the gate area. The fluorine-containing wet etching solution is an aqueous hydrofluoric acid etching solution. By controlling the etching time, the SiO2 spacer is completely removed while the gate metal structure remains unchanged.

[0048] Performance testing To evaluate the drain-to-gate leakage current characteristics of low-voltage p-GaN gate HEMT devices under different manufacturing processes, a low-voltage device with a rated withstand voltage of 40V was selected as the test object. The test was conducted using a semiconductor parameter analyzer, with a fixed bias applied to the device at room temperature and leakage current data collected.

[0049] During the specific testing process, a 40V DC voltage is applied to the drain of the device, while the gate and source are grounded. Under this bias condition, the leakage current between the drain and the gate is measured. Multiple devices within the same wafer are repeatedly tested to obtain the distribution of drain-to-gate leakage current among different devices, thereby comparing the leakage current levels and consistency of devices under different manufacturing process conditions.

[0050] Test results are as follows Figure 2 As shown, in the device fabricated using Comparative Example 1, the drain-to-gate leakage current distribution range is relatively wide, with significant differences in leakage current between different devices, and some devices exhibiting high leakage current values, reflecting a large degree of randomness in the leakage current path at the gate edge and surface under this process condition. In contrast, the device fabricated using the method described in Example 1 has an overall lower drain-to-gate leakage current level, significantly reduced differences in leakage current between devices, and no significantly abnormally increased leakage current phenomenon was observed, indicating that the device has better leakage current consistency within the wafer.

[0051] The above results demonstrate that by limiting the interface treatment step of the AlGaN barrier layer exposed after etching to before gate metal deposition, and by forming the gate metal edge structure through a negative photoresist stripping process, this invention avoids the gate metal from being exposed to the chemical solution environment during interface cleaning, while simultaneously creating a shoulder structure at the gate edge that has not undergone etching damage. This effectively suppresses the formation of leakage channels on the gate surface and at the edges. Therefore, this invention reduces the drain-to-gate leakage level while improving the electrical consistency and reliability of the device under mass production conditions.

[0052] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A method for manufacturing a low-voltage p-GaN gate HEMT device, characterized in that, Includes the following steps: S1: Provide a low-voltage p-GaN gate epitaxial structure; the low-voltage p-GaN gate epitaxial structure includes, from bottom to top, a substrate, a GaN channel layer, an AlGaN barrier layer and a p-GaN gate layer; S2: A SiO2 layer is formed on the surface of the p-GaN gate epitaxial structure; S3: The SiO2 layer is patterned by photolithography, and the SiO2 layer is etched using the pattern as a mask to obtain a SiO2 hard mask; S4: Using the SiO2 hard mask as a mask, p-GaN is etched to form the p-GaN pattern of the gate region; S5: Remove the SiO2 hard mask, and sequentially treat the surface of the AlGaN barrier layer exposed after etching with alkaline solution and acidic solution. S6: An opening for forming the gate metal pattern is created using a negative photoresist stripping process; S7: Deposit gate metal TiN to cover the opening and its surrounding area; S8: Perform a stripping process to remove non-gate TiN and form a shoulder structure at the gate metal edge corresponding to the unetched p-GaN region; The shoulder structure is a stepped coverage area of ​​the gate metal on the outer side of the p-GaN pattern edge.

2. The method for manufacturing a low-voltage p-GaN gate HEMT device according to claim 1, characterized in that, The process for forming the SiO2 layer in step S2 is plasma-enhanced chemical vapor deposition or low-pressure chemical vapor deposition, and the thickness of the SiO2 layer is 20-200 nm.

3. The method for manufacturing a low-voltage p-GaN gate HEMT device according to claim 1, characterized in that, The photolithography in step S3 includes sequentially coating photoresist, soft baking, exposure, development and post-baking. After development, an opening pattern corresponding to the gate region is formed on the SiO2 layer. The etching process of the SiO2 layer in step S3 is reactive ion etching or inductively coupled plasma etching, and the etching gas includes one or more of CHF3, CF4, and C5F8 combined with O2.

4. The method for manufacturing a low-voltage p-GaN gate HEMT device according to claim 1, characterized in that, The etching process for p-GaN in step S4 is inductively coupled plasma etching, and the etching gas includes one or more of Cl2, BCl3, and SiCl4 combined with Ar.

5. The method for manufacturing a low-voltage p-GaN gate HEMT device according to claim 1, characterized in that, The process of removing the hard mask in step S5 includes removing the hard mask using a fluorine-containing wet etching solution, wherein the fluorine-containing wet etching solution is a hydrofluoric acid solution or a buffered oxide etching solution.

6. The method for manufacturing a low-voltage p-GaN gate HEMT device according to claim 1, characterized in that, The alkaline solution is one of ammonia solution, tetramethylammonium hydroxide solution, or potassium hydroxide solution; the acidic solution is one of hydrochloric acid solution, sulfuric acid solution, or citric acid solution.

7. The method for manufacturing a low-voltage p-GaN gate HEMT device according to claim 6, characterized in that, The alkaline solution treatment is carried out at a temperature of 20–60°C for a duration of 10–300 seconds, and the acidic solution treatment is carried out at a temperature of 20–60°C for a duration of 10–300 seconds.

8. The method for manufacturing a low-voltage p-GaN gate HEMT device according to claim 1, characterized in that, The negative photoresist stripping process in step S6 includes sequential negative photoresist coating, soft baking, exposure, post-baking, development, and hard baking. After development, an opening for the gate metal pattern is formed, and a reverse-cut profile is formed on the sidewall of the opening.

9. The method for manufacturing a low-voltage p-GaN gate HEMT device according to claim 1, characterized in that, The negative photoresist is a negative photoresist containing epoxy groups or a chemically amplified negative photoresist, and the thickness of the negative photoresist is 0.3 to 3.0 μm.

10. The method for manufacturing a low-voltage p-GaN gate HEMT device according to claim 1, characterized in that, In step S7, the process for depositing gate metal TiN is physical vapor deposition, which is either DC magnetron sputtering or radio frequency sputtering, and the thickness of the deposited TiN is 10-200 nm. The stripping process in step S8 includes immersion in an organic stripping solution combined with ultrasound or spraying, wherein the organic stripping solution includes one or more of N-methylpyrrolidone, dimethyl sulfoxide, or propylene glycol methyl ether acetate.

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