A high-temperature-resistant SOI MOSFET device and a preparation method thereof

Abstract

This invention relates to the field of semiconductor technology, specifically to a high-temperature resistant SOI MOSFET device and its fabrication method. The key technical points are: the device is vertically arranged from top to bottom with a top silicon layer, a buried oxide layer, and a substrate layer. In the top silicon layer, a source region, a channel region, and a drain region are arranged laterally. The channel region is located between the source region and the drain region. A lightly doped extension region is located between the source region and the channel region, and a lightly doped extension region is located between the channel region and the drain region. A gate structure is located above the channel region, comprising a gate dielectric layer and a gate, with the gate located above the gate dielectric layer. Sidewall structures are located on both sides of the gate. Through multi-parameter collaborative optimization design, the electrical stability and reliability of the SOI MOSFET at an extreme high temperature of 175℃ are significantly improved, effectively suppressing key issues such as threshold voltage drift, increased leakage current, and degradation of breakdown characteristics.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a high-temperature resistant SOI MOSFET device and its fabrication method. Background Technology

[0002] As electronic systems evolve towards higher reliability and environmental adaptability, the stable operation of semiconductor devices in high-temperature environments has attracted widespread attention. In applications such as automotive electronics, aerospace, oil well logging, industrial control, and engine compartments, devices often need to operate stably for extended periods in environments exceeding 150°C, and even reaching 175°C. High-temperature environments place more stringent demands on the electrical performance, reliability, and lifespan of semiconductor devices.

[0003] Traditional bulk silicon MOSFETs are prone to various performance degradation issues under high-temperature conditions. As temperature increases, the internal carrier mobility decreases, leading to reduced conduction capability; simultaneously, the number of thermally excited carriers increases significantly, causing a sharp rise in leakage current during the off-state. Furthermore, high temperatures cause a significant drift in the device's threshold voltage and a decrease in breakdown voltage, thus affecting the device's operational stability and reliability. These problems limit the further application of bulk silicon MOSFETs in high-temperature environments.

[0004] Compared to bulk silicon devices, SOI MOSFETs, due to the introduction of a buried oxide layer (BOX) between the active silicon layer and the substrate, can effectively reduce parasitic capacitance and improve the isolation characteristics of the device, thus offering certain advantages in high-speed, low-power, and special environmental applications. However, existing SOI MOSFET devices still face many challenges under high-temperature operating conditions. For example, the self-heating effect of the device intensifies at high temperatures, the floating body effect is enhanced, and the heat-blocking effect of the buried oxide layer may lead to a further increase in local temperature rise, resulting in problems such as increased leakage current, threshold voltage drift, and unstable breakdown characteristics.

[0005] Existing SOI MOSFET devices struggle to balance low leakage current, stable threshold voltage, and reliable breakdown performance under high-temperature conditions. In particular, at high-temperature environments of approximately 175°C, their electrical parameters often deteriorate significantly, affecting the normal operation of the devices and circuit systems.

[0006] Therefore, there is an urgent need for an SOIMOSFET device that can be used in high-temperature environments and maintain stable electrical performance under high-temperature conditions. Summary of the Invention

[0007] In view of the above-mentioned shortcomings of the existing technology, the present invention provides a high-temperature resistant SOI MOSFET device and its fabrication method, which can effectively solve the problems of severe threshold voltage drift, sharp increase in leakage current and decrease in breakdown voltage caused by self-heating effect, floating body effect and material property degradation in existing SOI MOSFET devices at a high temperature of 175℃, making it difficult to balance electrical performance and high temperature stability.

[0008] To achieve the above objectives, the present invention provides the following technical solution:

[0009] In a first aspect, the present invention provides a high-temperature resistant SOI MOSFET device, comprising:

[0010] The device is provided with a top silicon layer, a buried oxide layer, and a substrate layer in a vertical direction from top to bottom. The top silicon layer is provided with a source region, a channel region, and a drain region in a horizontal direction.

[0011] The channel region is located between the source region and the drain region.

[0012] A lightly doped extension region on the source side is provided between the source region and the channel region, and a lightly doped extension region on the drain side is provided between the channel region and the drain region.

[0013] A gate structure is provided above the channel region. The gate structure includes a gate dielectric layer and a gate, with the gate disposed above the gate dielectric layer.

[0014] The gate is provided with sidewall structures on both sides.

[0015] Through the above technical solution, a complete SOI MOSFET device structure with source region, drain region, channel region, lightly doped extension regions on the source and drain sides, gate structure, and sidewalls is constructed. The buried oxide layer is used to achieve electrical isolation between the top silicon layer and the substrate layer, and the lightly doped extension region alleviates the electric field concentration at the channel edge, making the electric field distribution in the source-drain junction region more uniform, reducing the local electric field peak, thereby delaying the occurrence of breakdown, and improving the leakage current characteristics and breakdown characteristics of the device under high temperature conditions. Through the synergistic effect of the above structures, the SOI MOSFET device of the present invention can effectively suppress threshold voltage drift, reduce saturation current drift, and maintain relatively stable breakdown characteristics under high temperature conditions, thereby achieving reliable operation of the device at a high temperature of approximately 175°C.

[0016] Furthermore, the top silicon layer is made of silicon, with a thickness ranging from 0.15 μm to 0.30 μm, and is entirely p-type background doped with a doping concentration ranging from 5 × 10⁻⁶. 16 cm -3 ~5×10 17 cm -3 ;

[0017] The buried oxide layer is made of silicon oxide material with a thickness ranging from 0.01 μm to 0.2 μm.

[0018] Furthermore, the top silicon layer has a thickness of 0.25 μm and a doping concentration of approximately 1 × 10⁻⁶. 17 cm -3 .

[0019] The above technical solution limits the thickness of the top silicon layer to 0.15 μm to 0.30 μm and performs P-type background doping (concentration 5 × 10⁻⁶). 16 cm -3 ~5×10 17 cm -3 This allows the top silicon layer to form a P-type bulk region, effectively suppressing threshold voltage drift caused by increased intrinsic carrier concentration at high temperatures. At the same time, the buried oxide layer thickness is controlled at 0.01μm~0.2μm, taking into account both electrical isolation and thermal management, ensuring stable electrical characteristics of the channel region under high temperature conditions, and synergistically improving the device's operating stability at 175℃.

[0020] Furthermore, the length of the channel region ranges from 0.5 μm to 1.2 μm;

[0021] Both the source region and the drain region are n. + High-concentration doped region, with arsenic as the dopant, and a peak doping concentration range of 1×10⁻⁶. 19 cm -3 ~1×10 20 cm -3 The junction depth range is 0.10μm to 0.20μm.

[0022] Furthermore, the channel region has a length of 0.8 μm and a peak doping concentration of 5 × 10⁻⁶. 19 cm -3 The junction depth is approximately 0.15 μm.

[0023] The above technical solutions reduce the source-drain contact resistance of the device and improve its conductivity.

[0024] Furthermore, both the source-side lightly doped extension region and the drain-side lightly doped extension region are n-type doped, with a peak concentration range of 1×10⁻⁶. 17 cm -3 ~1×10 18 cm -3 The junction depth is 0.08μm.

[0025] Furthermore, the peak concentration was approximately 8 × 10⁻⁶. 17 cm -3 .

[0026] By using the above technical solutions, a gentle doping gradient is formed between the source / drain and the channel, which can effectively alleviate the electric field concentration at the channel edge and improve the leakage current and breakdown characteristics of the device under high temperature conditions.

[0027] Furthermore, the gate dielectric layer is made of HfO2, a material with a high dielectric constant, and the equivalent oxide layer thickness ranges from 0.04 μm to 0.08 μm.

[0028] The gate is made of polycrystalline silicon and highly doped, with a doping concentration of 1×10⁻⁶. 21 cm -3 .

[0029] Furthermore, the equivalent oxide layer thickness is approximately 0.06 μm.

[0030] The above technical solution employs HfO2, a high-dielectric-constant material, as the gate dielectric layer to enhance the gate's electrostatic control capability over the channel and suppress gate leakage current at high temperatures; simultaneously, it utilizes high-concentration doping (1×10⁻⁶). 21 cm -3 The polysilicon gate ensures that the gate still has low resistance under high temperature conditions.

[0031] Secondly, the present invention also provides a method for fabricating a high-temperature resistant SOI MOSFET device, comprising the following steps:

[0032] S1: Select an SOI wafer including a bottom substrate layer, a middle buried oxide layer and an upper top silicon layer, and use shallow trench isolation or mesa isolation processes to etch and fill the top silicon layer to define the active region.

[0033] S2: P-type impurity ion implantation is performed in the active region to form a background doping concentration of 1×10⁻⁶. 17 cm -3 The P-type body region, i.e., the channel region;

[0034] S3: Deposit HfO2 material on the surface of the top silicon layer to form a gate dielectric layer, deposit and dope a polysilicon layer on the gate dielectric layer, and form the gate through photolithography and etching processes;

[0035] S4: Using the gate as a mask, low-energy ion implantation of N-type impurities is performed on both sides of the gate to form a lightly doped extended region;

[0036] S5: A silicon nitride thin film is deposited on the entire wafer. An anisotropic dry etching process is used to remove the silicon nitride in the flat area, leaving the silicon nitride layer on the gate sidewall to form the sidewall.

[0037] S6: Using the gate and the sidewall as a combined mask, perform high-concentration N2O treatment. + Type Ion implantation forms heavily doped source and drain regions;

[0038] S7: Perform a rapid thermal annealing process to activate and inject impurities and repair lattice damage, followed by a metallization process to bring out the source, drain, gate and substrate electrodes to obtain the device.

[0039] Furthermore, the adjusted thickness of the top silicon layer in step S1 is 0.15 μm to 0.30 μm;

[0040] The P-type impurity implanted in step S2 is boron or boron difluoride, and the doping concentration of the formed P-type body region is 5 × 10⁻⁶. 16 cm -3 ~5×10 17 cm -3 .

[0041] The above technical solution provides a complete fabrication process: starting from the SOI wafer, through active region definition, P-type body region implantation, HfO2 gate dielectric and polysilicon gate formation, LDD implantation, sidewall fabrication, source and drain heavy doping implantation, rapid thermal annealing to metallization of lead electrodes, it achieves precise self-aligned integration of each key structure, ensuring that the device has structural consistency and process repeatability to operate stably at a high temperature of 175℃.

[0042] Furthermore, the equivalent oxide layer thickness of the gate dielectric layer deposited in step S3 is 0.04 μm to 0.08 μm.

[0043] The above technical solution ensures sufficient gate control capability to maintain the drive current, and effectively suppresses the exponentially increasing gate tunneling leakage current at high temperatures through a larger physical thickness, thereby improving the long-term reliability of the device.

[0044] Furthermore, the N-type impurity implanted in step S4 is phosphorus or arsenic, and the dosage of phosphorus or arsenic is controlled so that the peak concentration of the formed lightly doped extension region is 1×10⁻⁶. 17 cm -3 ~1×10 18 cm -3 The junction depth is 0.08μm.

[0045] The above technical solution suppresses the hot carrier effect at high temperatures.

[0046] Furthermore, the high-concentration N-type impurity injected in step S6 is arsenic, and the peak doping concentration of the resulting source and drain regions is 1×10⁻⁶. 19 cm -3 ~1×10 20 cm -3 The junction depth is 0.10μm~0.20μm.

[0047] The technical solution provided by this invention has the following advantages compared with the known prior art:

[0048] 1. This invention significantly improves the electrical stability and reliability of SOI MOSFETs at extreme high temperatures of 175℃ through multi-parameter collaborative optimization design, and effectively suppresses key issues such as threshold voltage drift, increased leakage current and degradation of breakdown characteristics.

[0049] 2. By employing an optimized buried oxide layer thickness of approximately 0.20 μm, this invention effectively suppresses substrate thermal interference and floating body effect while ensuring good electrical isolation, providing a fundamental guarantee for stable device performance at high temperatures;

[0050] 3. This invention enhances the gate's control over the channel by introducing HfO2 high-k gate dielectric to replace traditional SiO2, thereby significantly reducing the threshold voltage drift caused by high temperature (only about 25%) and ensuring the stability of switching characteristics;

[0051] 4. By setting an N-type LDD region with a specific concentration and junction depth between the source / drain and the channel, the present invention effectively alleviates the concentration of the junction electric field, significantly suppresses the leakage current at high temperatures, and unexpectedly increases the breakdown voltage from 51.5V at room temperature to 53V at high temperature. Attached Figure Description

[0052] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0053] Figure 1 This is a schematic diagram of the SOI MOSFET device of the present invention;

[0054] Figure 2 This is a schematic diagram showing the output characteristics of the device at different temperatures according to the present invention;

[0055] Figure 3 This is a schematic diagram illustrating the breakdown characteristics of the device at different temperatures according to the present invention;

[0056] Figure 4 This is a schematic diagram illustrating the effect of different top silicon film thicknesses on the self-heating effect of the device.

[0057] Reference numerals: 1. Sidewall; 2. Gate; 3. Gate dielectric layer; 4. Drain-side lightly doped extension region; 5. Top silicon layer; 6. Substrate layer; 7. Buried oxide layer; 8. Source region; 9. Drain region; 10. Channel region; 11. Source-side lightly doped extension region. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments.

[0059] Unless otherwise stated, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. While only preferred methods and materials are described herein, any methods and materials similar or equivalent to those described herein may be used in the implementation or testing of this invention. All references to this specification are incorporated by way of citation to disclose and describe methods and / or materials associated with those references. In the event of any conflict with any incorporated reference, the content of this specification shall prevail. The terms “comprising,” “including,” “having,” “containing,” etc., as used herein are open-ended terms, meaning that they include but are not limited to. Unless the context clearly indicates otherwise, the expressions “a” and “an” as used herein include plural references. It should be noted that “first,” “second,” etc., are used merely for convenience of description and distinction and should not be construed as indicating or implying relative importance. The term “about” as used herein indicates a range of ±20% of the following numerical value. In some embodiments, the term “about” indicates a range of ±10% of the following numerical value. In some embodiments, the term “about” indicates a range of ±5% of the following numerical value. The invention is further described below with reference to embodiments.

[0060] Example: Refer to Figures 1 to 4 This invention provides a high-temperature resistant SOI MOSFET device and its fabrication method. Through multi-parameter collaborative optimization design, the electrical stability and reliability of SOI MOSFET at extreme high temperature of 175℃ are significantly improved, and key problems such as threshold voltage drift, leakage current increase and breakdown characteristic degradation are effectively suppressed.

[0061] 1. Device structure and composition

[0062] like Figure 1 As shown, this invention provides an SOI MOSFET device structure suitable for operation in high-temperature environments. The device comprises, from top to bottom along the vertical direction, a top silicon layer 5, a buried oxide layer 7, and a substrate layer 6.

[0063] Substrate and Buried Oxide Layer: Substrate 6 is located at the bottom and supports the entire device structure. Buried oxide layer 7 is located between top silicon layer 5 and substrate 6, providing electrical isolation. Buried oxide layer 7 is made of silicon oxide, and its thickness can be set from 0.01 μm to 0.2 μm. In a preferred embodiment of the present invention, its thickness is approximately 0.20 μm. This thickness effectively isolates the electrical coupling between top silicon layer 5 and substrate 6, suppressing the thermal impact of the substrate on the channel region 10 at high temperatures.

[0064] Top silicon layer and active region: The top silicon layer 5 is located above the buried oxide layer 7 and is used to form the active region of the device. The top silicon layer 5 is made of silicon, with a thickness ranging from 0.15 μm to 0.30 μm, preferably about 0.25 μm. The top silicon layer 5 is entirely p-type background doped with a doping concentration ranging from 5 × 10⁻⁶. 16 cm -3 ~5×10 17 cm -3 The preferred concentration is approximately 1×10⁻⁶. 17 cm -3 This is to ensure the stability of the electrical properties of the channel region under high temperature conditions.

[0065] Source, drain, and channel: In the top silicon layer 5, the active region 8, the lightly doped extension region 11 on the source side, the channel region 10, the lightly doped extension region 4 on the drain side, and the drain region 9 are defined sequentially along the lateral direction.

[0066] Channel region 10: Located between source region 8 and drain region 9, its length range is designed to be 0.5μm~1.2μm, with a preferred length of about 0.8μm.

[0067] Source region 8 and drain region 9: both are n + High-concentration doped region, with arsenic (As) as the dopant, and a peak doping concentration range of 1×10⁻⁶. 19 cm -3 ~1×10 20 cm -3 Preferably about 5×10 19 cm -3 The junction depth ranges from 0.10 μm to 0.20 μm, with a preferred depth of approximately 0.15 μm.

[0068] Drain-side lightly doped extension region 4 (LDD region): Located between the source / drain region and the channel region 10, it is n-type doped, with a doping concentration lower than that of the source / drain region, and a peak concentration range of 1×10⁻⁶. 17 cm -3 ~1×10 18 cm -3 Preferably about 8×10¹ 7 cm -3 The junction depth is preferably about 0.08 μm. This structure is used to alleviate electric field concentration at the channel edge and improve high-temperature leakage and breakdown characteristics.

[0069] Gate structure: The gate structure is located above the channel region 10 and includes the gate dielectric layer 3 and the gate 2.

[0070] Gate dielectric layer 3: Employs HfO2, a high dielectric constant material, with an equivalent oxide layer thickness (EOT) ranging from 0.04 μm to 0.08 μm, preferably approximately 0.06 μm. The high dielectric properties of HfO2 reduce gate leakage current and improve threshold stability at high temperatures.

[0071] Gate 2: Located above the gate dielectric layer 3, it is made of polycrystalline silicon and highly doped, with a preferred doping concentration of approximately 1 × 10²¹ cm⁻¹. -3 This is to reduce the gate resistance.

[0072] Sidewall 1: Sidewalls 1, made of silicon nitride, are provided on both sides of the gate 2 to define the lightly doped extension region 4 and the location of source / drain implantation.

[0073] 2. Device working mechanism and high-temperature stability analysis

[0074] This embodiment, in conjunction with the above-described device structure, explains the working mechanism and electrical stability of the SOI MOSFET device of the present invention under high-temperature conditions.

[0075] Under high-temperature conditions, the thermal excitation effect of charge carriers inside semiconductor devices is significantly enhanced, leading to an increase in intrinsic charge carrier concentration, which in turn causes drift in saturation current and threshold voltage. Simultaneously, high temperatures exacerbate self-heating and parasitic effects within the device, impacting its breakdown characteristics and reliability.

[0076] To address the aforementioned issues, this invention employs a collaborative design of key structural parameters in SOI MOSFET devices to suppress the adverse effects of high temperatures on electrical performance at the device structure level.

[0077] 2.1 Mechanism analysis of threshold voltage stability under high temperature conditions

[0078] In traditional SOI MOSFET devices, as the temperature increases, the carrier distribution in the channel region 10 changes, and the influence of interface states and body charge increases, which can easily lead to a significant shift in the threshold voltage with temperature.

[0079] In this invention, by rationally selecting the thickness of the top silicon layer 5 and its background doping concentration, the channel region 10 can maintain a stable potential distribution under high-temperature conditions. The use of an appropriately thick silicon layer structure in the top silicon layer 5 enhances the response capability of the channel region 10 to the gate electric field, thereby reducing the impact of bulk charge changes on the threshold voltage under high-temperature conditions.

[0080] Meanwhile, this invention uses a high-dielectric-constant material as the gate dielectric layer 3, which enhances the gate 2's ability to control the channel's electric field under the same equivalent oxide layer thickness. At high temperatures, the high-dielectric-constant gate dielectric effectively reduces electric field fluctuations at the interface, suppresses threshold voltage drift as temperature increases, and thus improves the stability of the device's threshold voltage.

[0081] 2.2 Analysis of Leakage Current Suppression Mechanism under High Temperature Conditions

[0082] In high-temperature environments, the increase in leakage current mainly stems from the increase in thermally excited charge carriers and the carrier leakage caused by the enhanced electric field in the source-drain junction region. Especially in SOI devices, the floating body effect and the concentration of the electric field in the junction region at high temperatures further exacerbate the leakage problem.

[0083] This invention incorporates a lightly doped source-drain extension region 4 (LDD region) on the drain side between the source region 8, the drain region 9, and the channel region 10. By reducing the electric field intensity at the channel edge, this effectively suppresses the increase in hot carrier injection and leakage current in the source-drain junction region under high-temperature conditions. The LDD region forms a gradient doping structure with the high-concentration source-drain region, resulting in a smoother electric field distribution during lateral carrier transport, thereby improving the device's turn-off characteristics.

[0084] In addition, by reasonably selecting the thickness of the buried oxide layer 7, the electrical coupling between the top silicon layer 5 and the substrate layer 6 can be effectively isolated, reducing the influence of the substrate on the carrier distribution in the top silicon layer 5 under high temperature conditions, and structurally reducing the probability of leakage channel formation in the device under high temperature conditions.

[0085] 2.3 Mechanism analysis of breakdown characteristic stability under high temperature conditions

[0086] The breakdown characteristics of a device under high-temperature conditions are closely related to the electric field distribution and carrier recombination behavior in the source-drain junction region. As the temperature increases, the intrinsic carrier concentration of the material increases, and if the electric field in the source-drain junction region is concentrated, it can easily lead to a decrease in breakdown voltage.

[0087] This invention utilizes LDD structures on both sides of the channel region 10 to achieve a more uniform electric field distribution in the source-drain junction region, reducing local electric field peaks and thus delaying breakdown. Furthermore, the appropriate source-drain doping depth and concentration configuration allows the junction region to maintain a relatively stable space charge distribution under high-temperature conditions, which is beneficial for improving the breakdown stability of the device.

[0088] Meanwhile, the buried oxide layer 7 provides electrical isolation to the top silicon layer 5, limiting the breakdown path mainly to the region of the top silicon layer 5 and preventing the breakdown path from extending to the substrate under high temperature conditions, thereby further enhancing the breakdown reliability of the device under high temperature conditions.

[0089] 2.4 High-Temperature Stability Mechanism of Structural Synergy

[0090] It should be noted that the present invention does not improve high-temperature stability through a single structural parameter, but rather improves the electrical behavior of the device under high-temperature conditions through the synergistic design of multiple structural parameters such as top silicon layer thickness, doping distribution, buried oxide layer thickness, gate dielectric material, and source / drain extension regions.

[0091] Through the synergistic effect of the above structures, the SOI MOSFET device of the present invention can effectively suppress threshold voltage drift, reduce saturation current drift, and maintain relatively stable breakdown characteristics under high temperature conditions, thereby enabling the device to operate reliably in a high temperature environment of about 175°C.

[0092] 3. Simulation methods and high-temperature performance verification

[0093] To verify the electrical performance stability of the SOI MOSFET device of this invention, which is suitable for high-temperature environments, under high-temperature conditions, this embodiment uses Sentaurus TCAD to perform numerical simulation of the device, and compares and analyzes the threshold voltage drift, saturation current drift, and breakdown characteristics of the device under different temperature conditions. The device structure and doping configuration used in the simulation are as in Example 1.

[0094] 3.1 Simulation Model and Boundary Condition Settings

[0095] In the simulation, the device is configured with four electrode ports: source, drain, gate, and substrate. During the simulation, biases can be applied to each electrode according to the testing objectives to extract key indicators such as the device's transfer characteristics, output characteristics, saturation current drift, and breakdown characteristics.

[0096] To accurately describe the effect of temperature on carrier distribution and device electrical characteristics, Fermi statistics are introduced into the physical model, and temperature is set as an adjustable parameter (Temperature=@temp@), thereby enabling comparative evaluation of device performance under different temperature conditions (e.g., room temperature and approximately 175°C).

[0097] 3.2 Physical Model for Simulation of High-Temperature Electrical Characteristics

[0098] For the silicon material region, the simulation employs a composite model and a mobility model that include temperature-dependent terms. Specifically, the mobility model considers vertical electric field-related mobility degradation (Enormal) and high field velocity saturation to reflect the changes in carrier transport characteristics under the combined effects of high temperature and high field.

[0099] Meanwhile, the recombination model employs SRH recombination and considers doping dependence and temperature dependence (SRH (Doping Dependence, Temp Dependence)) to more realistically characterize the minority carrier lifetime variation under high-temperature conditions and its impact on leakage current. Furthermore, to improve the accuracy of intrinsic carrier concentration calculations under high-temperature conditions, an effective intrinsic carrier density model (Old Slotboom) is adopted.

[0100] Simulation and guidance of self-heating effect:

[0101] Building upon existing electrical characteristic simulations, this invention further supplements the thermal-electric coupling simulation. After the fabrication process is determined, simulation tools are used to model the self-heating effect of the device under steady-state operation at 175°C, analyzing the impact of the buried oxide layer thickness on heat dissipation. This allows for further reverse calibration of the selection of the SOI substrate buried oxide layer thickness in step S1, ensuring that the device will not fail due to localized overheating under actual high-temperature conditions.

[0102] Based on the introduction of a self-heating model, this simulation controls variables to set the buried oxide layer thickness to 0.01 μm, 0.0575 μm, and 0.2 μm, respectively, and observes the saturation current under the influence of self-heating and without it. If the drift is large, it indicates that the parameter is greatly affected by self-heating, thus enabling the reverse calibration of the selection of the buried oxide layer thickness of the SOI substrate in step S1.

[0103] The results are as follows Figure 4 As shown, for different buried oxide layer thicknesses, considering the effect of self-heating, the saturation leakage current of SOI MOSFET devices is reduced to a certain extent. Moreover, as the buried oxide layer thickness decreases, the reduction in device saturation leakage current decreases, verifying the optimal substrate buried oxide layer thickness of the present invention.

[0104] By configuring the above model, typical temperature effects such as threshold voltage drift and increased leakage current under high temperature conditions can be reflected at the simulation level, thereby verifying the ability of the device structure of the present invention to suppress the adverse effects of high temperature.

[0105] 4. High-temperature performance verification

[0106] In this invention, the following indicators were extracted and compared at room temperature and 175°C:

[0107] (1) Threshold Voltage: The threshold voltage was extracted under uniform test bias conditions, and the threshold drift at different temperatures was compared. By extracting the threshold voltage of the device under different temperature conditions, the drift of the device threshold voltage with temperature can be obtained. Simulation results show that when the temperature rises from room temperature to about 175°C, although the threshold voltage of the SOI MOSFET device of the present invention changes with temperature, its drift amplitude is effectively suppressed, with a relative change amplitude of about 25%, indicating that the device can still maintain relatively stable gate control characteristics under high temperature conditions. By combining the top silicon layer structure, doping configuration, and the synergistic effect of the high dielectric constant gate dielectric in the embodiment, the device of the present invention effectively reduces the influence of bulk charge and interface state changes on the threshold voltage under high temperature conditions, thereby improving the thermal stability of the threshold voltage.

[0108] (2) Saturation current: The saturation current is extracted under uniform test bias conditions, and the drift of the saturation current at different temperatures is compared; for example... Figure 2 As shown, simulation results indicate that when the temperature rises to approximately 175°C, the saturation current of the device changes to some extent with temperature, with a relative drift of approximately 13.1%. This result demonstrates that although a decrease in carrier mobility is inevitable in high-temperature environments, the present invention's rational configuration of source / drain doping distribution, channel length, and gate dielectric structure allows the device to maintain relatively stable conduction capability under high-temperature conditions, preventing drastic degradation of conduction performance.

[0109] (3) Breakdown Voltage: The breakdown voltage is extracted based on the avalanche model and termination criterion, and the stability of the breakdown voltage under high temperature conditions is compared. By gradually increasing the drain voltage and monitoring the change in drain current, the corresponding drain voltage is extracted as the device breakdown voltage when the drain current reaches a preset threshold. Figure 3 As shown, at room temperature, the breakdown voltage of the SOI MOSFET device of this invention is approximately 51.5 V; when the temperature rises to approximately 175°C, the breakdown voltage of the device does not decrease significantly, but instead increases to approximately 53 V. This result demonstrates that by optimizing the electric field distribution in the source-drain junction region at the structural level and utilizing the constraint effect of the buried oxide layer on the breakdown path, this invention enables the device to maintain stable or even slightly improved breakdown characteristics under high-temperature conditions, thereby significantly improving the reliability and safety margin of the device in high-temperature applications.

[0110] Through the above simulation process and index system, it can be verified that the SOI MOSFET device of the present invention has excellent threshold drift, saturation current drift and more stable breakdown characteristics in a high temperature environment of about 175℃, thereby meeting the reliability requirements of high temperature application scenarios.

[0111] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions will not cause the essence of the corresponding technical solutions to deviate from the protection scope of the technical solutions of the embodiments of the present invention.

Claims

1. A high-temperature resistant SOI MOSFET device, characterized in that, include: The device is provided with a top silicon layer, a buried oxide layer, and a substrate layer in a vertical direction from top to bottom. The top silicon layer is provided with a source region, a channel region, and a drain region in a horizontal direction. The channel region is located between the source region and the drain region. A lightly doped extension region on the source side is provided between the source region and the channel region, and a lightly doped extension region on the drain side is provided between the channel region and the drain region. A gate structure is provided above the channel region. The gate structure includes a gate dielectric layer and a gate, with the gate disposed above the gate dielectric layer. The gate is provided with sidewall structures on both sides.

2. The high-temperature resistant SOI MOSFET device according to claim 1, characterized in that, The top silicon layer is made of silicon, with a thickness ranging from 0.15 μm to 0.30 μm, and is entirely P-type background doped with a doping concentration ranging from 5 × 10⁻⁶. 16 cm -3 ~5×10 17 cm -3 ; The buried oxide layer is made of silicon oxide material with a thickness ranging from 0.01 μm to 0.2 μm.

3. The high-temperature resistant SOI MOSFET device according to claim 1, characterized in that, The length of the channel region ranges from 0.5 μm to 1.2 μm; Both the source region and the drain region are n. + High-concentration doped region, with arsenic as the dopant, and a peak doping concentration range of 1×10⁻⁶. 19 cm -3 ~1×10 20 cm -3 The junction depth range is 0.10μm to 0.20μm.

4. A high-temperature resistant SOI MOSFET device according to claim 1, characterized in that, Both the source-side lightly doped extension region and the drain-side lightly doped extension region are n-type doped, with a peak concentration range of 1×10⁻⁶. 17 cm -3 ~1×10 18 cm -3 The junction depth is 0.08μm.

5. A high-temperature resistant SOI MOSFET device according to claim 1, characterized in that, The gate dielectric layer is made of HfO2, a material with a high dielectric constant, and the equivalent oxide layer thickness ranges from 0.04 μm to 0.08 μm. The gate is made of polycrystalline silicon and highly doped, with a doping concentration of 1×10⁻⁶. 21 cm -3 .

6. A method for fabricating a high-temperature resistant SOI MOSFET device, characterized in that, Includes the following steps: S1: Select an SOI wafer including a bottom substrate layer, a middle buried oxide layer and an upper top silicon layer, and use shallow trench isolation or mesa isolation processes to etch and fill the top silicon layer to define the active region. S2: P-type impurity ion implantation is performed in the active region to form a background doping concentration of 1×10⁻⁶. 17 cm1×10 -3 The P-type body region, i.e., the channel region; S3: Deposit HfO2 material on the surface of the top silicon layer to form a gate dielectric layer, deposit and dope a polysilicon layer on the gate dielectric layer, and form the gate through photolithography and etching processes; S4: Using the gate as a mask, low-energy ion implantation of N-type impurities is performed on both sides of the gate to form a lightly doped extended region; S5: A silicon nitride thin film is deposited on the entire wafer. An anisotropic dry etching process is used to remove the silicon nitride in the flat area, leaving the silicon nitride layer on the gate sidewall to form the sidewall. S6: Using the gate and the sidewall as a combined mask, perform high-concentration N2O treatment. + Type Ion implantation forms heavily doped source and drain regions; S7: Perform a rapid thermal annealing process to activate and inject impurities and repair lattice damage, followed by a metallization process to bring out the source, drain, gate and substrate electrodes to obtain the device.

7. The method for fabricating a high-temperature resistant SOI MOSFET device according to claim 6, characterized in that, The adjusted thickness of the top silicon layer in step S1 is 0.15 μm to 0.30 μm; The P-type impurity implanted in step S2 is boron or boron difluoride, and the doping concentration of the formed P-type body region is 5 × 10⁻⁶. 16 cm -3 ~5×10 17 cm -3 .

8. The method for fabricating a high-temperature resistant SOI MOSFET device according to claim 6, characterized in that, The equivalent oxide layer thickness of the gate dielectric layer deposited in step S3 is 0.04 μm to 0.08 μm.

9. The method for fabricating a high-temperature resistant SOI MOSFET device according to claim 6, characterized in that, The N-type impurity implanted in step S4 is phosphorus or arsenic, and the dosage of phosphorus or arsenic is controlled so that the peak concentration of the lightly doped extension region is 1 × 10⁻⁶. 17 cm1×10 -3 ~1×10 18 cm1×10 -3 The junction depth is 0.08μm.

10. The method for fabricating a high-temperature resistant SOI MOSFET device according to claim 6, characterized in that, The high-concentration N-type impurity injected in step S6 is arsenic, and the peak doping concentration of the resulting source and drain regions is 1×10⁻⁶. 19 cm -3 ~1×10 20 cm -3 The junction depth is 0.10μm~0.20μm.

Images