High light conversion efficiency HJT cell and preparation method thereof
By optimizing the interface passivation structure in HJT cells, including depositing intrinsic amorphous silicon, silicon oxide, and aluminum oxide thin films, and combining them with transparent conductive oxides, the problem of interface recombination between crystalline silicon and amorphous silicon was solved, and a high-efficiency photoelectric conversion efficiency was achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 华能(嘉峪关)新能源有限公司
- Filing Date
- 2024-11-30
- Publication Date
- 2026-06-02
AI Technical Summary
In existing HJT cells, carrier recombination at the interface between crystalline silicon and amorphous silicon leads to a decrease in efficiency, making it difficult to achieve high light conversion efficiency.
Intrinsic amorphous silicon thin films were deposited on the front and back sides of the crystalline silicon substrate of the HJT cell, and silicon oxide and aluminum oxide thin films were deposited on the outside of the substrate by atomic layer deposition. Finally, a transparent conductive oxide thin film was deposited on the outside of the oxide thin film. The thickness of each layer and the deposition process were optimized to reduce the interface recombination rate.
The interface passivation technology significantly improves carrier lifetime and increases the photoelectric conversion efficiency of HJT cells to over 25%, especially in terms of open-circuit voltage and fill factor.
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Figure CN122138470A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of solar cells and relates to a high light conversion efficiency HJT cell and its preparation method. Background Technology
[0002] HJT cells, short for Heterojunction with Intrinsic Thin-layer Battery, are an advanced solar cell technology that utilizes the bandgap at the interface of heterogeneous materials to create a photovoltaic effect. The core of HJT cells lies in their heterojunction structure, which allows the cells to operate at lower temperatures, thereby improving photoelectric conversion efficiency and stability. Due to their high efficiency and low light-induced degradation characteristics, HJT cells are suitable for photovoltaic applications with high efficiency requirements, such as rooftop photovoltaics, photovoltaic agriculture, and building-integrated photovoltaics (BIPV).
[0003] In HJT cells, the interface between crystalline silicon and amorphous silicon is crucial. Carrier recombination at the interface directly leads to a decrease in efficiency. Summary of the Invention
[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a high-efficiency HJT battery and its preparation method, thereby improving the photoelectric conversion efficiency of the battery.
[0005] To achieve the above objectives, the present invention employs the following technical solution: A high-efficiency HJT cell includes a crystalline silicon substrate; An intrinsic amorphous silicon thin film is disposed on the front and back sides of a crystalline silicon substrate; a silicon oxide thin film is disposed on the outer side of the intrinsic amorphous silicon thin film on the front side; an aluminum oxide thin film is disposed on the outer side of the intrinsic amorphous silicon thin film on the back side; and a transparent conductive oxide thin film is disposed on the outer side of both the silicon oxide thin film and the aluminum oxide thin film.
[0006] Preferably, the thickness of the intrinsic amorphous silicon thin film is 3-10 nm.
[0007] Preferably, the thickness of the silicon oxide film is 1-2 nm.
[0008] Preferably, the thickness of the alumina film is 5-10 nm.
[0009] Preferably, the thickness of the transparent conductive oxide film is 10-50 nm.
[0010] A method for fabricating a high-efficiency HJT solar cell includes the following steps: Intrinsic amorphous silicon thin films are deposited on the front and back sides of a crystalline silicon substrate; A silicon oxide film is deposited on the outer side of the intrinsic amorphous silicon film on the front side using an atomic layer deposition process; An aluminum oxide film is deposited on the outer side of the intrinsic amorphous silicon film on the back side using an atomic layer deposition process; Transparent conductive oxide films are deposited on the outer surfaces of both silicon oxide and aluminum oxide films.
[0011] Preferably, the intrinsic amorphous silicon thin film is deposited using a plasma-enhanced chemical vapor deposition process.
[0012] Preferably, the silicon oxide thin film is formed by atomic layer deposition of silicon oxide gas at a temperature below 300°C.
[0013] Preferably, the alumina film is formed by layer-by-layer deposition on a silicon substrate using a chemical precursor of trimethylaluminum and water.
[0014] Preferably, the transparent conductive oxide film is deposited by sputtering or chemical vapor deposition.
[0015] Compared with the prior art, the present invention has the following beneficial effects: This invention utilizes an intrinsic amorphous silicon thin film to significantly reduce the interfacial recombination rate and increase carrier lifetime. The introduction of a silicon oxide passivation layer further enhances the open-circuit voltage (Voc) of the HJT cell, thereby improving the overall photoelectric conversion efficiency. The advantage of silicon oxide passivation lies in its excellent passivation effect and its synergistic effect with the amorphous silicon passivation layer, further improving cell performance. Aluminum oxide passivation significantly improves the open-circuit voltage and fill factor (FF) of the HJT cell, particularly excelling in reducing the surface recombination rate. By optimizing the thickness, doping level, and deposition process of the TCO layer, the photoelectric conversion efficiency of the HJT cell can be further increased to over 25%. Attached Figure Description
[0016] Figure 1 This is a schematic diagram of the HJT battery structure with high light conversion efficiency according to the present invention.
[0017] Wherein: 1-Crystal silicon substrate; 2-Intrinsic amorphous silicon thin film; 3-Silicon oxide thin film; 4-Aluminum oxide thin film; 5-Transparent conductive oxide thin film; 6-Electrode. Detailed Implementation
[0018] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.
[0019] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.
[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terms “installation,” “connection,” and “linkage” should be interpreted broadly, for example, as a fixed connection, a detachable connection, or an integral connection; a mechanical connection, an electrical connection, or a connection that allows communication; a direct connection or an indirect connection via an intermediate medium; or a connection within two elements or an interaction between two elements. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items. Those skilled in the art will understand the specific meaning of the above terms in this invention according to the specific circumstances. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention.
[0021] The following disclosure provides many different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.
[0022] like Figure 1 As shown, the HJT cell structure is built on an N-type single-crystal silicon wafer (c-Si) and exhibits high symmetry. Specifically, its structure includes the following key layers: Substrate layer: Crystalline silicon substrate 1 is an N-type single crystal silicon wafer, which serves as the main area for light absorption.
[0023] Intrinsic amorphous silicon thin film 2 (ia-Si:H): A very thin intrinsic amorphous silicon thin film 2 is deposited on both the front and back sides of an N-type single crystal silicon wafer to passivate silicon surface defects and improve open-circuit voltage.
[0024] Doped layer: Front side: A silicon oxide thin film 3 is deposited to form a PN junction with the N-type silicon wafer.
[0025] Back side: A thin aluminum oxide film is deposited to form a back surface field, which helps in the collection and transport of electrons.
[0026] Transparent conductive oxide film 5 (TCO): TCO films are deposited on both sides of the battery to reduce the series resistance when collecting current and to reduce reflection, thereby improving the utilization rate of light.
[0027] Electrode 6: Finally, a metal electrode 6 is fabricated on the transparent conductive oxide film 5 to complete the construction of the battery structure.
[0028] An intrinsic amorphous silicon thin film 2 is disposed on the front and back sides of a crystalline silicon substrate 1; a silicon oxide thin film 3 is disposed on the outer side of the intrinsic amorphous silicon thin film 2 on the front side; an aluminum oxide thin film 4 is disposed on the outer side of the intrinsic amorphous silicon thin film 2 on the back side; and a transparent conductive oxide thin film 5 is disposed on the outer side of both the silicon oxide thin film 3 and the aluminum oxide thin film 4.
[0029] Interface passivation technology plays a crucial role in improving the efficiency of heterojunction (HJT) solar cells. HJT cells combine the advantages of crystalline silicon solar cells and amorphous silicon thin-film cells. By adding passivation materials to the cell interface layer, interfacial recombination losses are reduced, the effective lifetime of charge carriers is increased, and thus the photoelectric conversion efficiency is improved. The following section will elaborate on how interface passivation can improve the efficiency of HJT cells, covering technical methods, implementation schemes, and the final results.
[0030] The method for fabricating a high-efficiency HJT cell described in this application involves passivating the interfaces in the HJT cell. The goal is to reduce interfacial recombination between crystalline and amorphous silicon, thereby improving carrier lifetime and enhancing photoelectric conversion efficiency. This application performs interface passivation on the HJT cell through the following steps.
[0031] An intrinsic amorphous silicon thin film 2 is deposited on the top and bottom surfaces of a crystalline silicon substrate 1; A silicon oxide film 3 is deposited on the outer side of one of the intrinsic amorphous silicon films 2 by atomic layer deposition. An aluminum oxide film 4 is deposited on the outside of another intrinsic amorphous silicon film 2 using an atomic layer deposition process; A transparent conductive oxide film 5 is deposited on the outside of the silicon oxide film 3 and the aluminum oxide film 4.
[0032] The following is a detailed description of the above process. Amorphous silicon (ia-Si:H) passivation In HJT cells, the passivation of amorphous silicon thin film is carried out using plasma-enhanced chemical vapor deposition (PECVD) process, which deposits a layer of intrinsic amorphous silicon thin film 2 (ia-Si:H) several nanometers thick on the silicon wafer surface. This thin film can effectively passivate the dangling bonds on the crystalline silicon surface and reduce the recombination of charge carriers at the interface.
[0033] Technical challenges: The thickness and deposition conditions of the amorphous silicon thin film have a significant impact on the passivation effect. Excessive thickness leads to increased light absorption, thereby reducing the short-circuit current density (Jsc) of the battery; while insufficient thickness may result in inadequate passivation. Furthermore, the deposition temperature of the amorphous silicon also needs to be properly controlled; excessively high temperatures can cause crystallization of the amorphous silicon, thus losing its passivation effect.
[0034] Implementation plan: First, the silicon wafer surface is pretreated with hydrogen plasma to remove surface oxide layers and contaminants. Then, in a PECVD system, silane (SiH4) and hydrogen (H2) are used as gas sources. By adjusting parameters such as the flow rate of the reactant gases, the chamber temperature, and the deposition time, a uniform and dense intrinsic amorphous silicon thin film is deposited. Finally, the film quality is further improved and the interface state density is reduced through a rapid thermal annealing (RTA) process.
[0035] The specific process is as follows: 1. Silicon Wafer Cleaning: First, the silicon wafer surface is cleaned using standard silicon wafer cleaning processes (such as SC1 and SC2) to remove organic contaminants and oxide layers. This step is crucial because surface contaminants significantly affect subsequent passivation results. A typical SC1 cleaning step uses a mixed solution of deionized water, ammonia (NH4OH), and hydrogen peroxide (H2O2), and cleans at a temperature of 70℃-80℃ for 10-15 minutes.
[0036] 2. Plasma pretreatment: Hydrogen plasma is used to pretreat the silicon wafer surface, removing residual oxide layers and further passivating surface dangling bonds through plasma bombardment. Typical process parameters are: gas flow rate H2 of 50 sccm (standard cubic centimeters / minute), reaction chamber pressure of 0.1-1 Pa, processing time of 60-120 seconds, and RF power of 10-50W.
[0037] 3. Intrinsic Amorphous Silicon Deposition: An intrinsic amorphous silicon thin film 2 (ia-Si:H) is deposited on the silicon wafer surface using plasma-enhanced chemical vapor deposition (PECVD). The specific steps are as follows: Gas source: Silane (SiH4) is used as the gas source, and hydrogen (H2) is used as the carrier gas. Typical gas flow rates are: SiH4 10-50 sccm, H2 50-200 sccm.
[0038] Chamber temperature: Deposition is performed at a low temperature of 200℃ to 250℃. Too high a temperature will cause the amorphous silicon to crystallize, affecting the passivation effect; too low a temperature may lead to a decrease in the quality of the thin film.
[0039] RF power: The RF power is controlled within the range of 5-20 W to ensure the uniformity and density of the thin film growth.
[0040] Thin film thickness control: The deposition time is 5-10 minutes, and the final intrinsic amorphous silicon thin film 2 has a thickness of 5-10 nm. Controlling the film thickness is crucial; too thick a film will increase light absorption, while too thin a film will result in insufficient passivation.
[0041] 4. Rapid Thermal Annealing: After intrinsic amorphous silicon deposition, rapid thermal annealing (RTA) further optimizes the interface passivation effect of the thin film. Typical annealing temperatures are 200°C to 250°C, with a time of 1-5 minutes. RTA can reduce the interface state density, thereby improving carrier lifetime and open-circuit voltage.
[0042] Final results: By optimizing the deposition process of amorphous silicon, the interfacial recombination rate can be significantly reduced and the carrier lifetime can be increased, thereby improving the photoelectric conversion efficiency of HJT cells to over 23%.
[0043] Silicon oxide (SiOx) passivation Silicon oxide passivation is a passivation technology based on oxide materials. By forming a thin silicon oxide layer (typically 1-2 nm) on the surface of crystalline silicon, this oxide layer can effectively reduce interfacial dangling bonds and work together with the intrinsic amorphous silicon thin film 2 to further improve the passivation effect of the interface.
[0044] Technical challenges: The thickness and uniformity of the silicon oxide film 3 have a significant impact on the passivation effect. Excessive thickness leads to increased interfacial resistance, thereby reducing battery efficiency. Therefore, precisely controlling the thickness during film growth is a key technical challenge. Furthermore, silicon oxide itself has low conductivity, which may affect carrier transport, necessitating its use in conjunction with other conductive materials.
[0045] Implementation: Silicon oxide passivation layers can be achieved through various methods, such as thermal oxidation, chemical vapor deposition (CVD), and atomic layer deposition (ALD). Atomic layer deposition (ALD) is the most commonly used because it allows for precise control of the film thickness and can be performed at relatively low temperatures, making it suitable for the process requirements of HJT cells. The optimal thickness for silicon oxide passivation is typically between 1 and 2 nanometers.
[0046] The specific process is as follows: 1. Crystalline silicon surface cleaning and pretreatment: Similar to the amorphous silicon passivation process, the silicon wafer surface is first cleaned according to standard procedures to ensure that there is no contamination or oxide residue.
[0047] 2. Silicon Oxide Deposition: A silicon oxide (SiOx) layer is deposited on the outer side of the intrinsic amorphous silicon thin film 2 on the front side using atomic layer deposition (ALD). ALD is a layer-by-layer deposition technique that allows for precise control of the film thickness and uniformity, and is suitable for depositing thin films at low temperatures. The thickness of the silicon oxide passivation layer is typically controlled at 1-2 nm.
[0048] ALD process gases: The ALD process for silicon oxide uses silicon tetrachloride (SiCl4) and water (H2O) as precursor gases.
[0049] Deposition temperature: Typical deposition temperatures range from 150°C to 200°C. Within this temperature range, dense and uniform silicon oxide films can be obtained without affecting the structure of the silicon wafer.
[0050] Deposition rate: The deposition rate of the ALD process is relatively slow, typically 0.1 nm / cycle, with a typical deposition time of 10-20 minutes, depending on the required silicon oxide layer thickness.
[0051] 3. Annealing treatment: To further improve the passivation effect, heat treatment is performed after deposition. The annealing temperature of the silicon oxide film 3 is relatively low, generally controlled at 200℃-300℃, for 5-10 minutes.
[0052] The final result shows that the introduction of a silicon oxide passivation layer can further improve the open-circuit voltage (Voc) of HJT cells, thereby enhancing the overall photoelectric conversion efficiency. Through process optimization, the efficiency of HJT cells can reach over 24%. The advantage of silicon oxide passivation technology lies in its excellent passivation effect and its ability to form a synergistic effect with amorphous silicon passivation layers, further improving cell performance.
[0053] Alumina (Al2O3) passivation Alumina passivation is particularly suitable for passivating the surface of n-type silicon wafers. Due to its inherent negative charge, Al2O3 thin film can effectively passivate dangling bonds on the silicon surface, especially for n-type silicon wafers, significantly reducing the surface recombination rate and improving the passivation effect.
[0054] Technical challenges: While the negative charge density of the alumina passivation layer helps reduce surface recombination, excessively high charge density can lead to improper bandgap adjustment at the interface, thus affecting carrier separation and transport. Furthermore, the alumina passivation layer needs to be used in conjunction with other transparent conductive oxides (such as ITO) or intrinsic amorphous silicon thin films to ensure good electrical performance.
[0055] Implementation Plan: The deposition of the alumina thin film 4 is typically performed using the ALD process, which involves depositing alumina layer by layer onto the silicon wafer surface using chemical precursors such as trimethylaluminum and water. The ALD process is characterized by uniform and dense film deposition and can be performed at low temperatures (typically below 300°C), making it ideal for HJT cell manufacturing. The typical thickness of the alumina passivation layer is 5-10 nm.
[0056] The specific process is as follows: 1. Silicon wafer cleaning: Similar to the previous two passivation processes, the standard cleaning process for silicon wafers is performed first.
[0057] 2. Alumina Deposition: Alumina (Al2O3) films are deposited using atomic layer deposition (ALD) technology. Alumina has an inherent negative charge, which can passivate dangling bonds on the silicon surface.
[0058] ALD process gases: Trimethylaluminum (TMA) and water (H2O) are used as precursors. TMA reacts with water to produce alumina.
[0059] Deposition temperature: The deposition temperature of alumina is controlled between 150℃ and 250℃. A lower deposition temperature ensures uniform film deposition and maintains good passivation effect.
[0060] Thin film thickness: The thickness of the Al2O3 layer is controlled between 5-10 nm. Too large a thickness may lead to a decrease in carrier mobility, while too small a thickness will affect the passivation effect.
[0061] 3. Heat Treatment: To activate the passivation properties of the alumina layer, subsequent heat treatment is performed after deposition. The annealing temperature is typically 250℃ to 350℃, and the time is 5-10 minutes. Annealing can effectively activate the negative charge density and improve the passivation effect.
[0062] The final results show that the alumina passivation layer significantly improves the open-circuit voltage and fill factor (FF) of HJT cells, especially in reducing the surface recombination rate. By optimizing the alumina deposition parameters and process control, the efficiency of HJT cells can be increased to over 24.5%. The greatest advantage of alumina passivation technology is its suitability for large-scale production and its significant effect on improving cell performance.
[0063] Transparent conductive oxide (TCO) passivation: Transparent conductive oxide (TCO) materials, such as indium tin oxide (ITO) and zinc oxide (ZnO), not only possess excellent conductivity and optical transparency, but also provide a certain degree of passivation for the interface of HJT cells. The TCO layer can reduce light reflection, improve light absorption, and to some extent reduce interfacial recombination losses.
[0064] Technical challenge: The conductivity and transparency of the TCO layer need to be balanced. Excessive conductivity may reduce transparency, affecting the light absorption of the battery; conversely, excessive transparency may lead to decreased conductivity, thereby reducing the battery's fill factor. Therefore, how to introduce appropriate amounts of doping elements (such as aluminum and gallium) into the TCO material to improve its overall performance is a key technical challenge.
[0065] Implementation Scheme: The TCO layer is typically deposited using sputtering or CVD processes. In HJT cells, the TCO layer is mainly located on the top layer of the cell, in contact with the silicon oxide film 3 and the aluminum oxide film 4. By controlling the thickness and optical properties of the TCO layer, good interface passivation can be achieved while ensuring high light transmittance. Furthermore, the doping level of the TCO material also needs to be precisely controlled to achieve optimal conductivity and passivation.
[0066] The specific process is as follows: 1. TCO deposition: TCO materials are usually indium tin oxide (ITO) or zinc oxide (ZnO), which are deposited on the outside of silicon oxide film 3 and aluminum oxide film 4 by magnetron sputtering or chemical vapor deposition (CVD) to improve conductivity and reduce interfacial recombination.
[0067] Sputtering process: Magnetron sputtering is the most commonly used deposition method. In the ITO deposition process, In₂O₃ and SnO₂ targets are typically used, and the process parameters are as follows: Working gas: Argon (Ar) is used as the sputtering gas, with a flow rate of 20-50 sccm.
[0068] Sputtering power: 100-300 W.
[0069] Deposition temperature: room temperature to 200°C.
[0070] Thin film thickness: The thickness of the TCO layer is controlled between 50-150 nm. Too thick a layer will increase light reflection, while too thin a layer will result in insufficient conductivity.
[0071] 2. Doping Treatment: To improve the conductivity of TCO, elements such as aluminum (Al) and gallium (Ga) can be doped in appropriate amounts. The dopant content is adjusted during the deposition process to achieve a balance between high conductivity and light transmittance.
[0072] 3. Post-treatment: After TCO deposition, annealing can be performed to improve the optical and electrical properties of the film. The annealing temperature is usually controlled between 200℃ and 300℃, and the time is 5-10 minutes.
[0073] Final results: By optimizing the thickness, doping level, and deposition process of the TCO layer, the photoelectric conversion efficiency of HJT cells can be further improved to over 25%.
[0074] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.
[0075] It should be understood that the above description is for illustrative purposes and not for limitation. Many embodiments and applications beyond the provided examples will be apparent to those skilled in the art upon reading the above description. Therefore, the scope of this patent should not be determined by reference to the above description, but rather by reference to the foregoing claims and the full scope of their equivalents. For purposes of completeness, all articles and references, including patent applications and publications, are incorporated herein by reference. The omission of any aspect of the subject matter disclosed herein in the foregoing claims is not intended as a waiver of that subject matter, nor should it be construed as an indication that the applicant has not considered that subject matter as part of the disclosed inventive subject matter.
Claims
1. A high-efficiency HJT battery, characterized in that, Including a crystalline silicon substrate (1); An intrinsic amorphous silicon thin film (2) is disposed on the front and back sides of a crystalline silicon substrate (1); a silicon oxide thin film (3) is disposed on the outside of the intrinsic amorphous silicon thin film (2) on the front side; an aluminum oxide thin film (4) is disposed on the outside of the intrinsic amorphous silicon thin film (2) on the back side; and a transparent conductive oxide thin film (5) is disposed on the outside of both the silicon oxide thin film (3) and the aluminum oxide thin film (4).
2. The high light conversion efficiency HJT battery according to claim 1, characterized in that, The thickness of the intrinsic amorphous silicon thin film (2) is 3-10 nm.
3. The high light conversion efficiency HJT battery according to claim 1, characterized in that, The thickness of the silicon oxide thin film (3) is 1-2 nm.
4. The high light conversion efficiency HJT battery according to claim 1, characterized in that, The thickness of the alumina film (4) is 5-10 nm.
5. The high light conversion efficiency HJT battery according to claim 1, characterized in that, The thickness of the transparent conductive oxide film (5) is 10-50 nm.
6. A method for preparing an HJT cell with high light conversion efficiency according to any one of claims 1-5, characterized in that, The process includes the following: Intrinsic amorphous silicon thin films (2) are deposited on the front and back sides of a crystalline silicon substrate (1). A silicon oxide film (3) is deposited on the outer side of the intrinsic amorphous silicon film (2) on the front side by an atomic layer deposition process. An aluminum oxide film (4) is deposited on the outer side of the intrinsic amorphous silicon film (2) on the back side by an atomic layer deposition process. A transparent conductive oxide film (5) is deposited on the outer side of both the silicon oxide film (3) and the aluminum oxide film (4).
7. The method for preparing a high-efficiency HJT cell according to claim 6, characterized in that, Intrinsic amorphous silicon thin films (2) are deposited by plasma-enhanced chemical vapor deposition.
8. The method for preparing a high-efficiency HJT cell according to claim 6, characterized in that, The silicon oxide thin film (3) is formed by atomic layer deposition of silicon oxide gas at a temperature below 300°C.
9. The method for preparing a high-light conversion efficiency HJT cell according to claim 6, characterized in that, Alumina thin films (4) are formed by layer-by-layer deposition on a silicon substrate using chemical precursors of trimethylaluminum and water.
10. The method for preparing a high-efficiency HJT cell according to claim 6, characterized in that, Transparent conductive oxide thin films (5) are deposited by sputtering or chemical vapor deposition processes.