Method of producing a tunnel oxide passivated contact cell
By simplifying the production process of tunnel oxide passivation contact batteries, including texturing, diffusion, etching, deposition and sintering steps, the complex and cumbersome production process is solved, and production efficiency and battery performance are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 华能(临高)新能源有限公司
- Filing Date
- 2024-11-30
- Publication Date
- 2026-06-02
AI Technical Summary
The production process of tunnel oxide passivated contact batteries is complex and cumbersome, with high process requirements, which restricts production efficiency.
Optimize the production process, including texturing, P-type diffusion and etching, deposition of alumina passivation layer and silicon oxide film, annealing of amorphous silicon film, printing of metal gate lines and sintering, simplify process steps and improve efficiency.
It improves the production efficiency of tunnel oxide passivated contact batteries, enhances the light absorption efficiency and current transmission stability of the batteries, and improves the stability and durability of the batteries.
Smart Images
Figure CN122138510A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of solar cell technology and relates to a method for producing a tunnel oxide passivated contact cell. Background Technology
[0002] Tunneling oxide passivated contact solar cells are a type of solar cell based on the selective carrier principle, using tunneling oxide passivated contacts. Their structure is an N-type silicon substrate cell. On the back of the cell, an ultrathin layer of silicon oxide and a thin layer of doped silicon together form the passivation contact structure. This structure effectively reduces surface recombination and metal-contact recombination, providing greater potential for further improvement in the conversion efficiency of N-PERT cells. TOPCon cells retain and utilize existing traditional P-type cell equipment processes to the greatest extent possible, requiring only the addition of boron diffusion and thin-film deposition equipment. They eliminate the need for back-side openings and alignment, greatly simplifying the cell manufacturing process and making mass production easier.
[0003] Although tunneling oxide passivated contact solar cells have significant advantages in terms of conversion efficiency, bifaciality, and temperature coefficient, their production process involves multiple steps and precise process control, such as the preparation of ultrathin silicon oxide layers, the deposition of doped silicon thin layers, and annealing. These steps place high demands on equipment and processes, and the production process is complex and cumbersome, which severely restricts the production efficiency of tunneling oxide passivated contact solar cells.
[0004] In summary, the existing production process of tunnel oxide passivated contact batteries has the problems of high process requirements and complex and cumbersome production process. Summary of the Invention
[0005] The purpose of this invention is to provide a method for producing tunnel oxide passivated contact batteries, in order to solve the technical problems of high process requirements and complex and cumbersome production process in the existing production process of tunnel oxide passivated contact batteries. This invention improves the production efficiency of tunnel oxide passivated contact batteries by optimizing the production process.
[0006] To achieve the above objectives, the present invention employs the following technical solution: This invention discloses a method for manufacturing a tunnel oxide passivated contact battery, comprising the following steps: The silicon wafer is sequentially texturized, P-type diffused, and etched. An aluminum oxide passivation layer is deposited on the front side of the etched silicon wafer; An aluminum oxide passivation layer is prepared on the front side of a silicon wafer and a silicon oxide thin film is prepared on the back side. A doped amorphous silicon thin film is then deposited on the silicon oxide thin film. The amorphous silicon thin film deposited on the silicon wafer is annealed to crystallize the amorphous silicon thin film and form a polycrystalline silicon structure. A silicon nitride thin film is deposited on the back amorphous silicon layer as an antireflection layer and a protective layer; Metal grid lines are printed on the front and back sides of a silicon wafer. The silicon wafer with the printed metal grid lines is then placed in a high-temperature furnace for sintering to obtain a tunnel oxide passivated contact cell.
[0007] Furthermore, in the steps of sequentially texturing, P-type diffusion, and etching the silicon wafer, a chemical etching method is used to texture the silicon wafer.
[0008] Furthermore, in the steps of texturing, P-type diffusion, and etching the silicon wafer in sequence, boron is selected as the impurity element when performing P-type diffusion on the silicon wafer, the diffusion temperature is greater than or equal to 1000℃, and the diffusion time is 150 minutes.
[0009] Furthermore, in the steps of texturing, P-type diffusion, and etching the silicon wafer in sequence, wet etching is used when etching the silicon wafer. The etching solution is an acidic solution containing boron, the etching temperature is between 40°C and 80°C, and the etching time is between 30 min and 100 min.
[0010] Furthermore, the step of depositing an aluminum oxide passivation layer on the front side of the etched silicon wafer is as follows: Surface pretreatment is performed on the etched silicon wafer; An aluminum oxide passivation layer is deposited on the front side of the etched silicon wafer using chemical vapor deposition.
[0011] Furthermore, when depositing an aluminum oxide passivation layer on the front side of the etched silicon wafer using chemical vapor deposition, the deposition temperature is 300°C~500°C, and the flow rate of the aluminum source gas is 80 ml / min~150 ml / min.
[0012] Furthermore, the amorphous silicon thin film deposited on the silicon wafer is annealed to crystallize the amorphous silicon thin film and form a polycrystalline silicon structure, wherein the annealing temperature is between 600°C and 1000°C.
[0013] Furthermore, a silicon nitride thin film is deposited on the back amorphous silicon layer as an antireflection layer and a protective layer. During the silicon nitride thin film deposition process, a silicon source gas is selected with a flow rate of 2000 sccm to 2500 sccm, a deposition temperature of 445℃ to 455℃, and a deposition pressure of 1100 Pa.
[0014] Furthermore, the printing of metal gate lines on the front and back sides of the silicon wafer is as follows: A layer of conductive paste is coated on the front side of the silicon wafer; Using screen printing or laser transfer technology, regularly arranged metal grid lines are formed on the front and back sides of the silicon wafer.
[0015] Furthermore, the silicon wafer with printed metal grid lines is placed in a high-temperature furnace for sintering. After sintering, the sintered cell is tested to check its performance indicators such as open-circuit voltage, short-circuit current, and conversion efficiency.
[0016] Compared with the prior art, the present invention has the following beneficial effects: 1. This invention improves light absorption efficiency and ensures smooth current flow through the battery by sequentially texturing, P-type diffusion, and etching the silicon wafer. Depositing an aluminum oxide passivation layer on the front side of the etched silicon wafer reduces recombination losses on the wafer surface, increases the open-circuit voltage and short-circuit current of the battery, and prevents short circuits caused by direct contact. Preparing a silicon oxide film on the front aluminum oxide passivation layer and the back side of the silicon wafer, followed by depositing a doped amorphous silicon film on the silicon oxide film, further enhances the passivation effect and conductivity of the battery. Annealing the amorphous silicon film deposited on the silicon wafer crystallizes it, forming a polycrystalline silicon structure. The crystallized polycrystalline silicon structure exhibits better conductivity and stability, enabling more efficient collection and transport of charge carriers. Depositing a silicon nitride film on the back amorphous silicon layer serves as an antireflection and protective layer, reducing light reflection on the battery surface and improving light absorption efficiency. Metal grid lines are printed on the front and back sides of a silicon wafer. The silicon wafer with the printed metal grid lines is then placed in a high-temperature furnace for sintering to obtain a tunneling oxide passivated contact cell. Sintering the silicon wafer with the printed metal grid lines in a high-temperature furnace allows for a good ohmic contact between the metal grid lines and the silicon wafer, ensuring smooth current transmission. Simultaneously, the sintering process further strengthens the cell structure, improving its stability and durability. This invention improves the production efficiency of tunneling oxide passivated contact cells by optimizing the production process. Attached Figure Description
[0017] Figure 1 This is a flowchart of the method of the present invention. Detailed Implementation
[0018] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.
[0019] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0020] The present invention will now be described in further detail with reference to the accompanying drawings: See Figure 1 This invention discloses a method for producing a tunnel oxide passivated contact battery, comprising the following steps: S1. The silicon wafer is sequentially texturized, P-type diffused, and etched; Preferably, the silicon wafer is texturized using a chemical etching method.
[0021] Preferably, when performing P-type diffusion on silicon wafers, boron is selected as the impurity element, the diffusion temperature is greater than or equal to 1000℃, and the diffusion time is 150 minutes.
[0022] Preferably, when etching the silicon wafer, wet etching is used, the etching solution is an acidic solution containing boron, the etching temperature is between 40°C and 80°C, and the etching time is between 30 min and 100 min.
[0023] S2. Deposit an aluminum oxide passivation layer on the front side of the etched silicon wafer, as follows: Surface pretreatment is performed on the etched silicon wafer; An aluminum oxide passivation layer is deposited on the front side of the etched silicon wafer using chemical vapor deposition.
[0024] Preferably, the deposition temperature is 300°C to 500°C, and the flow rate of the aluminum source gas is 80 ml / min to 150 ml / min.
[0025] S3. Prepare a silicon oxide thin film on the front side of the silicon wafer and a silicon oxide thin film on the back side, and deposit a doped amorphous silicon thin film on the silicon oxide thin film; S4. Anneal the amorphous silicon film deposited on the silicon wafer to crystallize the amorphous silicon film and form a polycrystalline silicon structure; Preferably, the annealing temperature is between 600°C and 1000°C.
[0026] S5. Deposit a silicon nitride thin film on the back amorphous silicon layer as an anti-reflection layer and a protective layer; Preferably, during the silicon nitride thin film deposition process, a silicon source gas is selected with a flow rate of 2000 sccm to 2500 sccm, a deposition temperature of 445℃ to 455℃, and a deposition pressure of 1100 Pa.
[0027] S6. Print metal grid lines on the front and back sides of the silicon wafer as current collection and transmission channels. Place the silicon wafer with printed metal grid lines in a high-temperature furnace for sintering treatment to make the metal grid lines form good ohmic contact with the silicon wafer, thus obtaining a tunnel oxide passivated contact cell.
[0028] Preferably, the printing of metal gate lines on the front and back sides of the silicon wafer as current collection and transmission channels is as follows: A layer of conductive paste is coated on the front side of the silicon wafer; Using screen printing or laser transfer technology, regularly arranged metal grid lines are formed on the front and back sides of the silicon wafer.
[0029] Preferably, the silicon wafer with printed metal grid lines is placed in a high-temperature furnace for sintering. After sintering, the sintered cell is tested to check its performance indicators such as open-circuit voltage, short-circuit current, and conversion efficiency.
[0030] See Figure 1 In another feasible embodiment of the invention, the following modifications are made as appropriate. The process includes the following steps: sequentially texturing, P-type diffusion, and etching the silicon wafer; texturing the silicon wafer creates tiny pyramidal structures on its surface, which can more effectively capture light, reduce reflection, and thus improve light absorption efficiency. P-type diffusion of the silicon wafer forms a PN junction. Etching removes unnecessary diffusion layers from the surface and periphery of the silicon wafer to prevent short circuits and ensure smooth current flow through the battery.
[0031] An aluminum oxide passivation layer is deposited on the front side of the etched silicon wafer. The aluminum oxide layer has excellent passivation effect, which can reduce recombination losses on the silicon wafer surface and improve the open-circuit voltage and short-circuit current of the battery. At the same time, it can also serve as an isolation layer between the front electrode and the silicon wafer, preventing short circuits caused by direct contact.
[0032] By preparing a silicon oxide thin film on the front side of the silicon wafer and a silicon oxide thin film on the back side, and depositing a doped amorphous silicon thin film on the silicon oxide thin film, the passivation effect and conductivity of the battery can be further improved. In addition, preparing a silicon oxide thin film on both the front side of the silicon wafer and the back side is beneficial to production. Annealing the amorphous silicon thin film deposited on the silicon wafer crystallizes the amorphous silicon thin film to form a polycrystalline silicon structure. The crystallized polycrystalline silicon structure has better conductivity and stability and can collect and transport charge carriers more effectively. A silicon nitride thin film is deposited on the amorphous silicon layer on the back side as an anti-reflection layer and a protective layer. The silicon nitride layer, as an anti-reflection layer, can reduce the reflection of light on the surface of the battery and improve the light absorption efficiency. Metal grid lines are printed on the front and back sides of a silicon wafer. The wafer with the printed metal grid lines is then sintered in a high-temperature furnace to obtain a tunneling oxide passivated contact solar cell. Sintering the silicon wafer with the printed metal grid lines in a high-temperature furnace allows for a good ohmic contact between the metal grid lines and the silicon wafer, ensuring smooth current transmission. Simultaneously, the sintering process further strengthens the cell's structure, improving its stability and durability. Furthermore, compared to traditional production methods, optimizing the production process of tunneling oxide passivated contact solar cells improves production efficiency.
[0033] Example 1: See Figure 1 This embodiment discloses a method for manufacturing a tunneling oxide layer passivated contact battery, including the following steps: S1. The silicon wafer is sequentially texturized, P-type diffused, and etched; Preferably, the silicon wafer is texturized using a chemical etching method.
[0034] Preferably, when performing P-type diffusion on the silicon wafer, boron is selected as the impurity element, the diffusion temperature is 1000℃, and the diffusion time is 150 minutes.
[0035] Preferably, when etching the silicon wafer, wet etching is used, the etching solution is an acidic solution containing boron, the etching temperature is between 40°C, and the etching time is 100 min.
[0036] S2. Deposit an aluminum oxide passivation layer on the front side of the etched silicon wafer, as follows: Surface pretreatment is performed on the etched silicon wafer; An aluminum oxide passivation layer is deposited on the front side of the etched silicon wafer using chemical vapor deposition.
[0037] Preferably, the deposition temperature is 300°C and the flow rate of the aluminum source gas is 150 ml / min.
[0038] S3. Prepare a silicon oxide thin film on the front side of the silicon wafer and a silicon oxide thin film on the back side, and deposit a doped amorphous silicon thin film on the silicon oxide thin film; S4. Anneal the amorphous silicon film deposited on the silicon wafer to crystallize the amorphous silicon film and form a polycrystalline silicon structure; Preferably, the annealing temperature is between 600°C and 600°C.
[0039] S5. Deposit a silicon nitride thin film on the back amorphous silicon layer as an anti-reflection layer and a protective layer; Preferably, during the silicon nitride thin film deposition process, a silicon source gas with a flow rate of 2000 sccm, a deposition temperature of 455℃, and a deposition pressure of 1100 Pa are selected.
[0040] S6. Print metal grid lines on the front and back sides of the silicon wafer as current collection and transmission channels. Place the silicon wafer with printed metal grid lines in a high-temperature furnace for sintering treatment to make the metal grid lines form good ohmic contact with the silicon wafer, thus obtaining a tunnel oxide passivated contact cell.
[0041] Preferably, the printing of metal gate lines on the front and back sides of the silicon wafer as current collection and transmission channels is as follows: A layer of conductive paste is coated on the front side of the silicon wafer; Using screen printing or laser transfer technology, regularly arranged metal grid lines are formed on the front and back sides of the silicon wafer.
[0042] Preferably, the silicon wafer with printed metal grid lines is placed in a high-temperature furnace for sintering. After sintering, the sintered cell is tested to check its performance indicators such as open-circuit voltage, short-circuit current, and conversion efficiency.
[0043] Experimental tests show that the bifaciality of the emitter and back passivated battery in this embodiment reaches 79% to 80%, the ratio of the battery's output power under 50°C operating conditions to its output power under standard test conditions reaches 91% to 92%, the temperature coefficient is -0.32% / °C, and the highest efficiency is 24.5%.
[0044] Example 2: See Figure 1 This embodiment discloses a method for manufacturing a tunneling oxide layer passivated contact battery, including the following steps: S1. The silicon wafer is sequentially texturized, P-type diffused, and etched; Preferably, the silicon wafer is texturized using a chemical etching method.
[0045] Preferably, when performing P-type diffusion on the silicon wafer, boron is selected as the impurity element, the diffusion temperature is 1100℃, and the diffusion time is 150 minutes.
[0046] Preferably, when etching the silicon wafer, wet etching is used, the etching solution is an acidic solution containing boron, the etching temperature is between 60°C, and the etching time is 65 minutes.
[0047] S2. Deposit an aluminum oxide passivation layer on the front side of the etched silicon wafer, as follows: Surface pretreatment is performed on the etched silicon wafer; An aluminum oxide passivation layer is deposited on the front side of the etched silicon wafer using chemical vapor deposition.
[0048] Preferably, the deposition temperature is 400°C and the flow rate of the aluminum source gas is 115 ml / min.
[0049] S3. Prepare a silicon oxide thin film on the front side of the silicon wafer and a silicon oxide thin film on the back side, and deposit a doped amorphous silicon thin film on the silicon oxide thin film; S4. Anneal the amorphous silicon film deposited on the silicon wafer to crystallize the amorphous silicon film and form a polycrystalline silicon structure; Preferably, the annealing temperature is between 800°C and 800°C.
[0050] S5. Deposit a silicon nitride thin film on the back amorphous silicon layer as an anti-reflection layer and a protective layer; Preferably, during the silicon nitride thin film deposition process, a silicon source gas with a flow rate of 2250 sccm, a deposition temperature of 450℃, and a deposition pressure of 1100 Pa are selected.
[0051] S6. Print metal grid lines on the front and back sides of the silicon wafer as current collection and transmission channels. Place the silicon wafer with printed metal grid lines in a high-temperature furnace for sintering treatment to make the metal grid lines form good ohmic contact with the silicon wafer, thus obtaining a tunnel oxide passivated contact cell.
[0052] Preferably, the printing of metal gate lines on the front and back sides of the silicon wafer as current collection and transmission channels is as follows: A layer of conductive paste is coated on the front side of the silicon wafer; Using screen printing or laser transfer technology, regularly arranged metal grid lines are formed on the front and back sides of the silicon wafer.
[0053] Preferably, the silicon wafer with printed metal grid lines is placed in a high-temperature furnace for sintering. After sintering, the sintered cell is tested to check its performance indicators such as open-circuit voltage, short-circuit current, and conversion efficiency.
[0054] Experimental tests show that the bifaciality of the emitter and back passivated battery in this embodiment reaches 79% to 80%, the ratio of the battery's output power under 50°C operating conditions to its output power under standard test conditions reaches 91% to 92%, the temperature coefficient is -0.32% / °C, and the highest efficiency is 24.5%.
[0055] Example 3: See Figure 1This embodiment discloses a method for manufacturing a tunneling oxide layer passivated contact battery, including the following steps: S1. The silicon wafer is sequentially texturized, P-type diffused, and etched; Preferably, the silicon wafer is texturized using a chemical etching method.
[0056] Preferably, when performing P-type diffusion on the silicon wafer, boron is selected as the impurity element, the diffusion temperature is 1200℃, and the diffusion time is 150 minutes.
[0057] Preferably, when etching the silicon wafer, wet etching is used, the etching solution is an acidic solution containing boron, the etching temperature is between 80°C, and the etching time is 30 minutes.
[0058] S2. Deposit an aluminum oxide passivation layer on the front side of the etched silicon wafer, as follows: Surface pretreatment is performed on the etched silicon wafer; An aluminum oxide passivation layer is deposited on the front side of the etched silicon wafer using chemical vapor deposition.
[0059] Preferably, the deposition temperature is 500°C and the flow rate of the aluminum source gas is 80 ml / min.
[0060] S3. Prepare a silicon oxide thin film on the front side of the silicon wafer and a silicon oxide thin film on the back side, and deposit a doped amorphous silicon thin film on the silicon oxide thin film; S4. Anneal the amorphous silicon film deposited on the silicon wafer to crystallize the amorphous silicon film and form a polycrystalline silicon structure; Preferably, the annealing temperature is between 1000°C and 1000°C.
[0061] S5. Deposit a silicon nitride thin film on the back amorphous silicon layer as an anti-reflection layer and a protective layer; Preferably, during the silicon nitride thin film deposition process, a silicon source gas with a flow rate of 2500 sccm, a deposition temperature of 455℃, and a deposition pressure of 1100 Pa are selected.
[0062] S6. Print metal grid lines on the front and back sides of the silicon wafer as current collection and transmission channels. Place the silicon wafer with printed metal grid lines in a high-temperature furnace for sintering treatment to make the metal grid lines form good ohmic contact with the silicon wafer, thus obtaining a tunnel oxide passivated contact cell.
[0063] Preferably, the printing of metal gate lines on the front and back sides of the silicon wafer as current collection and transmission channels is as follows: A layer of conductive paste is coated on the front side of the silicon wafer; Using screen printing or laser transfer technology, regularly arranged metal grid lines are formed on the front and back sides of the silicon wafer.
[0064] Preferably, the silicon wafer with printed metal grid lines is placed in a high-temperature furnace for sintering. After sintering, the sintered cell is tested to check its performance indicators such as open-circuit voltage, short-circuit current, and conversion efficiency.
[0065] Experimental tests show that the bifaciality of the emitter and back passivated battery in this embodiment reaches 79% to 80%, the ratio of the battery's output power under 50°C operating conditions to its output power under standard test conditions reaches 91% to 92%, the temperature coefficient is -0.32% / °C, and the highest efficiency is 24.5%.
[0066] This invention improves the production efficiency of tunneling oxide passivated contact batteries by optimizing the production process. Furthermore, the produced tunneling oxide passivated contact batteries exhibit good stability, durability, and high efficiency.
[0067] The above content is only for illustrating the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solution based on the technical concept proposed in this invention shall fall within the scope of protection of the claims of this invention.
Claims
1. A method for producing a tunneling oxide passivated contact battery, characterized in that, Includes the following steps: The silicon wafer is sequentially texturized, P-type diffused, and etched. An aluminum oxide passivation layer is deposited on the front side of the etched silicon wafer; An aluminum oxide passivation layer is prepared on the front side of a silicon wafer and a silicon oxide thin film is prepared on the back side. A doped amorphous silicon thin film is then deposited on the silicon oxide thin film. The amorphous silicon thin film deposited on the silicon wafer is annealed to crystallize the amorphous silicon thin film and form a polycrystalline silicon structure. A silicon nitride thin film is deposited on the back amorphous silicon layer as an antireflection layer and a protective layer; Metal grid lines are printed on the front and back sides of a silicon wafer. The silicon wafer with the printed metal grid lines is then placed in a high-temperature furnace for sintering to obtain a tunnel oxide passivated contact cell.
2. The method for producing a tunneling oxide passivated contact battery according to claim 1, characterized in that, In the steps of texturing, P-type diffusion, and etching the silicon wafer sequentially, chemical etching is used to texturize the silicon wafer.
3. The method for producing a tunneling oxide passivated contact battery according to claim 1, characterized in that, In the steps of texturing, P-type diffusion and etching the silicon wafer in sequence, boron is selected as the impurity element when performing P-type diffusion on the silicon wafer, the diffusion temperature is greater than or equal to 1000℃ and the diffusion time is 150 minutes.
4. The method for producing a tunneling oxide passivated contact battery according to claim 1, characterized in that, In the steps of texturing, P-type diffusion and etching the silicon wafer in sequence, wet etching is used when etching the silicon wafer. The etching solution is an acidic solution containing boron, the etching temperature is between 40°C and 80°C, and the etching time is between 30 min and 100 min.
5. The method for producing a tunneling oxide passivated contact battery according to claim 1, characterized in that, The specific steps for depositing an aluminum oxide passivation layer on the front side of the etched silicon wafer are as follows: Surface pretreatment is performed on the etched silicon wafer; An aluminum oxide passivation layer is deposited on the front side of the etched silicon wafer using chemical vapor deposition.
6. The method for producing a tunneling oxide passivated contact battery according to claim 5, characterized in that, When depositing an aluminum oxide passivation layer on the front side of the etched silicon wafer using chemical vapor deposition, the deposition temperature is 300°C~500°C, and the flow rate of the aluminum source gas is 80 ml / min~150 ml / min.
7. The method for producing a tunneling oxide passivated contact battery according to claim 1, characterized in that, The amorphous silicon thin film deposited on the silicon wafer is annealed to crystallize the amorphous silicon thin film and form a polycrystalline silicon structure, wherein the annealing temperature is between 600°C and 1000°C.
8. The method for producing a tunneling oxide passivated contact battery according to claim 1, characterized in that, A silicon nitride thin film is deposited on the back amorphous silicon layer as an antireflection layer and a protective layer. During the silicon nitride thin film deposition process, a silicon source gas is selected with a flow rate of 2000 sccm to 2500 sccm, a deposition temperature of 445℃ to 455℃, and a deposition pressure of 1100 Pa.
9. The method for producing a tunneling oxide passivated contact battery according to claim 1, characterized in that, The printing of metal gate lines on the front and back sides of the silicon wafer is as follows: A layer of conductive paste is coated on the front side of the silicon wafer; Using screen printing or laser transfer technology, regularly arranged metal grid lines are formed on the front and back sides of the silicon wafer.
10. The method for producing a tunneling oxide passivated contact battery according to claim 1, characterized in that, The silicon wafers printed with metal grid lines are placed in a high-temperature furnace for sintering. After sintering, the sintered cells are tested to check their performance indicators such as open-circuit voltage, short-circuit current, and conversion efficiency.