Interposer, semiconductor package, and method of manufacturing semiconductor package

Abstract

Examples of interposers, semiconductor packages, and methods of manufacturing semiconductor packages are provided. In one aspect, the interposer includes: a lower interposer plate; and an upper interposer plate coupled to the lower interposer plate, wherein the lower interposer plate includes: a first body layer; a first capacitor below the first body layer; a first interconnect layer below the first capacitor; and a first pad on an upper surface of the first body layer, and the upper interposer plate includes: a second body layer; a second capacitor above the second body layer; a second interconnect layer above the second capacitor; and a second pad on a lower surface of the second body layer, and the lower interposer plate is coupled to the upper interposer plate, and the first pad is electrically connected to the second pad.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0173948, filed on November 28, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The present invention relates to intermediates, semiconductor packages, and methods for manufacturing semiconductor packages. Background Technology

[0003] With the rapid development of the electronics industry and user demands, the size and weight of electronic devices have continued to decrease. As electronic devices become smaller and lighter, the semiconductor packages used in them have also become smaller and lighter, while still requiring high performance, high capacity, and excellent reliability. To achieve reduced size and weight, high performance, high capacity, and excellent reliability, continuous research and development have been undertaken on semiconductor chips, including those with through-silicon vias (TSVs), and semiconductor packages in which semiconductor chips are stacked. Furthermore, interposers (or intermediate layers) that connect semiconductor devices arranged on top of the semiconductor package to each other or to the package substrate have been mounted on the package substrate and serve as the dielectric substrate. Summary of the Invention

[0004] This disclosure provides an intermediary for improving signal integrity (SI) / power integrity (PI) characteristics and reducing the size of a semiconductor package, as well as a semiconductor package including the intermediary.

[0005] Furthermore, the purpose of this disclosure is not limited to the above-described purposes, and other purposes will be clearly understood by those skilled in the art from the following description.

[0006] According to one aspect of this disclosure, an intermediary includes: a lower intermediary plate; and an upper intermediary plate disposed above and coupled to the lower intermediary plate, wherein the lower intermediary plate includes: a first body layer; a first capacitor below the first body layer; a first interconnect layer below the first capacitor; and a first pad on the upper surface of the first body layer, and the upper intermediary plate includes: a second body layer; a second capacitor above the second body layer; a second interconnect layer above the second capacitor; and a second pad on the lower surface of the second body layer, and the first pad is electrically connected to the second pad through the coupling of the lower intermediary plate and the upper intermediary plate.

[0007] According to another aspect of this disclosure, an intermediary includes: a lower intermediary plate; and an upper intermediary plate disposed above and coupled to the lower intermediary plate, wherein the lower intermediary plate includes: a first body layer; a first capacitor on the first body layer; a first interconnect layer on the first capacitor; a first pad on the first body layer or the first interconnect layer; and a first through electrode extending through the first body layer and connecting the first interconnect layer to the first pad; the upper intermediary plate includes: a second body layer; a second capacitor on the second body layer; a second interconnect layer on the second capacitor; a second pad on the second body layer or the second interconnect layer; and a second through electrode extending through the second body layer and connecting the second interconnect layer to the second pad, and the first pad is electrically connected to the second pad through the coupling of the lower and upper intermediary plates.

[0008] According to another aspect of this disclosure, a semiconductor package includes: a package substrate; an interposer mounted on the package substrate and including a lower interposer plate and an upper interposer plate bonded to the lower interposer plate; and at least one semiconductor device mounted on the interposer, wherein the lower interposer plate includes: a first body layer; a first capacitor below the first body layer; a first interconnect layer below the first capacitor; and a first pad on an upper surface of the first body layer, and the upper interposer plate includes: a second body layer; a second capacitor above the second body layer; a second interconnect layer above the second capacitor; and a second pad on a lower surface of the second body layer, and the first pad is electrically connected to the second pad through the bonding of the lower interposer plate and the upper interposer plate.

[0009] According to another aspect of this disclosure, a method of manufacturing a semiconductor package includes: preparing an interposer substrate; mounting a semiconductor device on the interposer substrate; sealing the semiconductor device on the interposer substrate by a sealing member; manufacturing an intermediate semiconductor package including an interposer and at least one semiconductor device by separating the interposer substrate and the semiconductor device; and mounting the intermediate semiconductor package on a package substrate, wherein the interposer includes a lower interposer plate and a upper interposer plate, the lower interposer plate including: a first body layer; a first capacitor below the first body layer; a first interconnect layer below the first capacitor; a first pad on an upper surface of the first body layer; and a first through electrode extending through the first body layer and connecting the first interconnect layer to the first pad; the upper interposer plate is disposed above the lower interposer plate and coupled to the lower interposer plate, the upper interposer plate including: a second body layer; a second capacitor above the second body layer; a second interconnect layer above the second capacitor; a second pad on a lower surface of the second body layer; and a second through electrode extending through the second body layer and connecting the second interconnect layer to the second pad. Attached Figure Description

[0010] The embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0011] Figure 1A and Figure 1B These are cross-sectional views and enlarged views of the intermediate body according to the implementation method.

[0012] Figure 2A and Figure 2B These are cross-sectional views and enlarged views of the intermediate body according to the implementation method.

[0013] Figure 3A and Figure 3B This is a cross-sectional view of the intermediate body according to the implementation method.

[0014] Figures 4A to 4C This is a cross-sectional view of the intermediate body according to the implementation method.

[0015] Figure 5 This is a cross-sectional view of a semiconductor package according to an embodiment.

[0016] Figures 6A to 6C yes Figure 5 A more detailed cross-sectional view of the structure of the second semiconductor device in the semiconductor package.

[0017] Figure 7A and Figure 7B This is a cross-sectional view of a semiconductor package according to an embodiment.

[0018] Figures 8A to 8F This is a cross-sectional view illustrating a method for manufacturing an intermediate substrate according to an embodiment.

[0019] Figure 9A and Figure 9B This is a cross-sectional view illustrating a method for manufacturing an intermediate substrate according to an embodiment.

[0020] Figure 10 This is a cross-sectional view illustrating a method for manufacturing an intermediate substrate according to an embodiment.

[0021] Figures 11A to 11E This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment. Detailed Implementation

[0022] In the following description, embodiments are described in detail with reference to the accompanying drawings. The same reference numerals are used for the same elements in the drawings, and descriptions are not repeated.

[0023] Figure 1A and Figure 1B These are cross-sectional and enlarged views of the interposer (or intermediate layer) 100 according to the embodiment, wherein... Figure 1B yes Figure 1A A magnified view of region A.

[0024] Reference Figure 1A and Figure 1B According to the embodiment, the intermediary 100 can adjust the semiconductor devices 1300, 1400 and 1500 mounted above the intermediary 100 (see... Figure 5 Signal transmission between semiconductor devices 1300, 1400, and 1500 and the package substrate 1200 (see [link]). Furthermore, the intermediary 100 can adjust the signal transmission between semiconductor devices 1300, 1400, and 1500 and the package substrate 1200 (see [link]). Figure 5 Signal and power transmission between components. For example, the interposer 100 may be mounted on the package substrate 1200, and semiconductor devices 1300, 1400, and 1500 may be connected to the package substrate 1200.

[0025] Intermediate 100 may include a lower intermediate plate 100-1 and an upper intermediate plate 100-2. Each of the lower intermediate plate 100-1 and the upper intermediate plate 100-2 may include silicon (Si). Therefore, intermediate 100 may include a Si intermediate. The lower intermediate plate 100-1 and the upper intermediate plate 100-2 may be bonded to each other by a hybrid copper bond (HCB). Here, HCB may represent a bond that combines a pad-to-pad bond with an insulator-to-insulator bond. Because pads typically include copper (Cu), a pad-to-pad bond may be referred to as a Cu-to-Cu bond. The HCB is described in more detail below with respect to the bonding between a first back-side pad 130b-1 of the lower intermediate plate 100-1 and a second back-side pad 130b-2 of the upper intermediate plate 100-2.

[0026] The lower intermediate plate 100-1 may include a first body layer 101-1, a first interconnect layer 110-1, a first through electrode 120-1, a first pad 130-1, a first capacitor 140-1, and a first external connection terminal 150. In the lower intermediate plate 100-1, the first interconnect layer 110-1 may correspond to the front side. For example, the lower surface of the first interconnect layer 110-1 may correspond to the front side, and the upper surface of the first body layer 101-1 may correspond to the back side. The first body layer 101-1 may include, for example, Si.

[0027] The first interconnect layer 110-1 may be disposed below the first main body layer 101-1. The upper end of the first interconnect layer 110-1 may be connected to the first through electrode 120-1, and the lower end of the first interconnect layer 110-1 may be connected to the first front pad 130f-1. Furthermore, the first interconnect layer 110-1 may be connected to the first capacitor 140-1. For example, the first interconnect layer 110-1 may be located below the first capacitor 140-1.

[0028] like Figure 1BAs shown, the first interconnect layer 110-1 may include an interlayer insulating layer 112, interconnects 114, vias 116, and an aluminum (Al) pad 118. Due to the multilayer structure of the interconnects 114, the interlayer insulating layer 112 may also have a multilayer structure. All layers of the interlayer insulating layer 112 may comprise the same material, or at least one layer of the interlayer insulating layer 112 may comprise a different material. The interconnects 114 may be arranged as a multilayer structure within the interlayer insulating layer 112. Interconnects 114 in different layers may be connected to each other vias 116. The interconnects 114 and vias 116 may comprise, for example, Cu. However, the material of the interconnects 114 and vias 116 is not limited to Cu. The Al pad 118 may be disposed at the lower end of the first interconnect layer 110-1 and may be connected to the interconnects 114 vias 116. The Al pad 118 may be covered by a first front protective layer 135f-1. According to some embodiments, the Al pad 118 may be included within the interconnects 114.

[0029] The first through-hole electrode 120-1 can penetrate the first body layer 101-1 to extend in the vertical direction (i.e., the z-direction, which is perpendicular to the plane formed by the x and y directions)). The first body layer 101-1 may include Si, therefore, the first through-hole electrode 120-1 may correspond to a through-silicon via (TSV). Figure 1B As shown, the first through electrode 120-1 may have a structure in which the upper part of the first through electrode 120-1 is narrow and the lower part of the first through electrode 120-1 is wide. This may be because the first through electrode 120-1 is formed by forming a trench on the lower side of the first body layer 101-1. However, according to some embodiments, the upper and lower parts of the first through electrode 120-1 may have similar widths.

[0030] The lower end of the first through electrode 120-1 can be connected to the interconnect line 114 of the first interconnect layer 110-1, and through the interconnect line 114, the first through electrode 120-1 can be connected to the first front pad 130f-1 on the lower surface of the first interconnect layer 110-1 and connected to the first external connection terminal 150. In addition, the upper end of the first through electrode 120-1 can be connected to the first back pad 130b-1 on the first main body layer 101-1.

[0031] The first through electrode 120-1 may have a cylindrical shape and may include a barrier layer on its outer surface and a buried conductive layer inside. The barrier layer may include at least one material selected from Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, and NiB. The buried conductive layer may include at least one material selected from Cu, Cu alloys (such as CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, CuW), W, W alloys, Ni, Ru, and Co.

[0032] Furthermore, the first electrode insulating layer 122-1 may be disposed between the first through electrode 120-1 and the first body layer 101-1. The first electrode insulating layer 122-1 may include, for example, an oxide layer, a nitride layer, a carbide layer, a polymer layer, or a combination thereof. Figure 1B As shown, the first electrode insulating layer 122-1 may cover the side surface of the first through electrode 120-1 and may extend on the upper surface of the first interconnect layer 110-1.

[0033] The first pad 130-1 may include a first front pad 130f-1 and a first back pad 130b-1. The first front pad 130f-1 may be disposed on the lower surface of the first interconnect layer 110-1. Furthermore, the first front pad 130f-1 may be connected to the interconnect line 114 via an Al pad 118 and a via 116. The first back pad 130b-1 may be disposed on the upper surface of the first body layer 101-1 and may be connected to the first through electrode 120-1. The first pad 130-1 may include at least one of, for example, Al, Cu, Ni, W, Pt, and Au. In the intermediate 100 according to an embodiment, the first pad 130-1 may include Cu. However, the material of the first pad 130-1 is not limited to Cu.

[0034] A first protective layer 135-1 may be disposed on the lower and upper surfaces of the lower intermediate plate 100-1. The first protective layer 135-1 may include a first back-side protective layer 135b-1 and a first front-side protective layer 135f-1. The first back-side protective layer 135b-1 may be disposed on the upper surface of the first body layer 101-1. A first back-side pad 130b-1 may be disposed with a structure extending through the first back-side protective layer 135b-1. For example, the first back-side pad 130b-1 may extend through the first back-side protective layer 135b-1 and may be connected to the first through electrode 120-1. A first front-side protective layer 135f-1 may be disposed on the lower surface of the first interconnect layer 110-1. The first front-side pad 130f-1 may be disposed with a structure extending through a portion of the first front-side protective layer 135f-1. For example, a first front pad 130f-1 may extend through a portion of the first front protective layer 135f-1 and may be connected to the Al pad 118 in the first front protective layer 135f-1. The first protective layer 135-1 may include, for example, an oxide layer, a nitride layer, a carbide layer, a polymer layer, or a combination thereof. However, the material of the first protective layer 135-1 is not limited thereto. The first protective layer 135-1 may have a single-layer or multi-layer structure.

[0035] A first capacitor 140-1 may be disposed in a first host layer 101-1. The first capacitor 140-1 may include, for example, an integrated stacked capacitor (ISC). An ISC may have a large capacitance (e.g., several nF to tens of nF) based on its structure. The first capacitor 140-1 may include a lower electrode 142, an upper electrode 146, and a dielectric layer 144. The lower electrode 142 and the upper electrode 146 may include polysilicon. Therefore, based on the structure and material, the lower electrode 142 may be referred to as storage polysilicon, and the upper electrode 146 may be referred to as planar polysilicon. However, according to some embodiments, the lower electrode 142 and the upper electrode 146 may include a metallic material.

[0036] A first capacitor 140-1 may be disposed within a first main insulating layer 141-1 on a first main body layer 101-1. A first separating insulating layer 103-1 may be disposed between the first main body layer 101-1 and the first main insulating layer 141-1. However, according to some embodiments, the first separating insulating layer 103-1 may be omitted. A first plate electrode 145-1 may be disposed on the first separating insulating layer 103-1. The first plate electrode 145-1 may be connected to the lower electrode 142. A first covering through electrode 147-1 may pass through the portion of the first main insulating layer 141-1 corresponding to the upper electrode 146 and may be connected to the upper electrode 146. Although not shown, a second covering through electrode may pass through the first main body layer 101-1 and the first main insulating layer 141-1 and may be connected to the first plate electrode 145-1. Furthermore, in Figure 1B In the diagram, the first capacitor 140-1 is shown as having a structure with two V-shaped connections. However, in practice, the first capacitor 140-1 may have a structure with multiple V-shaped connections.

[0037] A first external connection terminal 150 may be disposed on a first front pad 130f-1 on the lower surface of the lower intermediate plate 100-1. The first external connection terminal 150 may be connected to a first through electrode 120-1 via the first front pad 130f-1 and the first interconnect layer 110-1. The first external connection terminal 150 may include solder. The solder may include In, Bi, Sb, Cu, Ag, Zn and / or alloys thereof. For example, the solder may include Sn, Sn-Ag, Sn-Au, Sn-Cu, Sn-Bi, Sn-Zn, Sn-Ag-Cu, Sn-Ag-Bi, Sn-Ag-Zn, Sn-Cu-Bi, Sn-Cu-Zn, Sn-Bi-Zn, etc. The solder may be referred to as a bump, solder bump, etc.

[0038] According to some embodiments, the first external connection terminal 150 may include a post, and solder may be disposed on the post. The post may include, for example, Ni, Cu, Pd, Pt, Au, or combinations thereof. According to some embodiments, the post may act as a pad and may include Cu. In this case, the post may be referred to as a bump pad, Cu pad, Cu post, etc. Furthermore, when the post acts as a pad, the first front pad 130f-1 may be omitted.

[0039] An upper intermediate plate 100-2 may be disposed on a lower intermediate plate 100-1. The upper intermediate plate 100-2 may include a second main body layer 101-2, a second interconnect layer 110-2, a second through electrode 120-2, a second pad 130-2, and a second capacitor 140-2. In the upper intermediate plate 100-2, the second interconnect layer 110-2 may correspond to the front side. That is, the upper surface of the second interconnect layer 110-2 may correspond to the front side, and the lower surface of the second main body layer 101-2 may correspond to the back side.

[0040] The components of the upper intermediate plate 100-2 are substantially the same as those of the lower intermediate plate 100-1. However, the upper intermediate plate 100-2 may be arranged in a direction opposite to that of the lower intermediate plate 100-1. Specifically, the front side of the lower intermediate plate 100-1 may face downward and the back side of the lower intermediate plate 100-1 may face upward, while the front side of the upper intermediate plate 100-2 may face upward and the back side of the upper intermediate plate 100-2 may face downward. As described above, in the intermediate 100 according to the embodiment, the upper intermediate plate 100-2 and the lower intermediate plate 100-1 may be arranged in directions opposite to each other, therefore, the components of the upper intermediate plate 100-2 may be symmetrically positioned with respect to the components of the lower intermediate plate 100-1 in the z-direction. For example, the first pad 130-1 and the second pad 130-2 may be arranged in symmetrical positions. Therefore, with respect to their arrangement and function, the first back pad 130b-1 can correspond to the second back pad 130b-2, and the first front pad 130f-1 can correspond to the second front pad 130f-2. According to some embodiments, similar to the lower intermediate plate 100-1, the upper intermediate plate 100-2 may further include a second separating insulating layer 103-2, a second electrode insulating layer 122-2, a second plate electrode 145-2, a second main body insulating layer 141-2, and a second covering through electrode 147-2.

[0041] However, the first external connection terminal 150 may be arranged on the first front pad 130f-1, while the semiconductor devices 1300, 1400 and 1500 (see [reference]) mounted on the interposer 100 Figure 5 External connection terminals 1350, 1450 and 1550 (see) Figure 5The first front pad 130f-1 can be arranged on the second front pad 130f-2. Therefore, the first front pad 130f-1 can have a different size and a different pitch than the second front pad 130f-2. For example, the size and pitch of the second front pad 130f-2 can be smaller than the size and pitch of the first front pad 130f-1. Furthermore, due to the differences between the first front pad 130f-1 and the second front pad 130f-2, the connection structure and the number of layers of the interconnect 114 can differ between the first interconnect layer 110-1 and the second interconnect layer 110-2.

[0042] Furthermore, the lower intermediate plate 100-1 connected to the first external connection terminal 150 may be formed to have a greater thickness than the upper intermediate plate 100-2. Therefore, as... Figure 1B As shown, the first capacitor 140-1 may have a larger size and a larger capacitance than the second capacitor 140-2. However, the size and capacitance of the first capacitor 140-1 and the second capacitor 140-2 are not limited thereto. For example, according to some embodiments, the first capacitor 140-1 may have substantially the same size and capacitance as the second capacitor 140-2. According to some embodiments, the capacitance of the second capacitor 140-2 may be less than or equal to the capacitance of the first capacitor 140-1.

[0043] Other aspects of the second main body layer 101-2, the second interconnect layer 110-2, the second through electrode 120-2, the second pad 130-2, and the second capacitor 140-2 may be the same as those of the first main body layer 101-1, the first interconnect layer 110-1, the first through electrode 120-1, the first pad 130-1, and the first capacitor 140-1 of the lower intermediate plate 100-1 described above. According to some embodiments, similar to the first interconnect layer 110-1, the second interconnect layer 110-2 may also include an interlayer insulating layer 112, an interconnect line 114, a via 116, and an Al pad 118, and similar to the first capacitor 140-1, the second capacitor 140-2 may also include a lower electrode 142, an upper electrode 146, and a dielectric layer 144.

[0044] In the intermediate body 100 according to the embodiment, the lower intermediate body plate 100-1 and the upper intermediate body plate 100-2 can be coupled to each other via HCB as described above. For example, the first back side pad 130b-1 of the lower intermediate body plate 100-1 can be coupled to the corresponding second back side pad 130b-2 of the upper intermediate body plate 100-2, and the first back side protective layer 135b-1 of the lower intermediate body plate 100-1 can be coupled to the second back side protective layer 135b-2 of the upper intermediate body plate 100-2. According to some embodiments, the first back side pad 130b-1 of the lower intermediate body plate 100-1 can be electrically connected to the second back side pad 130b-2 of the upper intermediate body plate 100-2. Reference will be used... Figures 8A to 8FThe method for manufacturing intermediate substrates is described in more detail regarding aspects of HCB.

[0045] The interposer 100 according to an embodiment may include a 2.5D interposer. For reference, the interposer 100 may include a 2.5D interposer and a 2.3D interposer. Furthermore, according to some embodiments, the structure of the interposer 100 may be further specified by including a Si bridge. Therefore, structures other than 2.5D interposers will be referred to as 2.xD interposers. A 2.5D interposer may generally represent a Si interposer and may include a TSV within it. A 2.3D interposer may represent an organic or inorganic interposer. When a 2.3D interposer includes a through electrode, depending on the material of the host layer, the through electrode may be referred to as a through-dielectric via (TDV), through-glass via (TGV), etc. According to some embodiments, a 2.3D interposer may be referred to as a panel-level package (PLP) interposer, a redistribution layer (RDL) interposer, etc.

[0046] The interposer 100 according to the embodiment may have a structure in which the lower interposer plate 100-1 and the upper interposer plate 100-2 are joined to each other by an HCB. Furthermore, the lower interposer plate 100-1 and the upper interposer plate 100-2 may each include a first capacitor 140-1 and a second capacitor 140-2 having an ISC structure. Therefore, when a system-in-package (SiP) is formed by including the interposer 100 according to the embodiment, the interposer 100 can provide sufficient capacitance, thus improving signal integrity (SI) / power integrity (PI) characteristics without additionally arranging capacitors. Furthermore, because no additional external capacitors are required, the size of the SiP can be reduced by as much as the size and solder area of ​​additional capacitors. Additionally, the first capacitor 140-1 may be arranged to have a large size on the lower surface of the interposer 100 (e.g., on the front side of the lower interposer plate 100-1) to be adjacent to the package substrate 1200 (see [link to documentation]). Figure 5 Therefore, the total capacitance of the SiP capacitor can be improved. Furthermore, since the capacitor is arranged adjacent to the power / ground, the PI characteristics can be improved, and because of the second external connection terminal 1250 connected to the power / ground based on the package substrate 1200 (see... Figure 5 The first capacitor 140-1 can be arranged on the front side of the lower plate 100-1 of the intermediate body, so the PI characteristics can be further improved.

[0047] Figure 2A and Figure 2B These are cross-sectional views and enlarged views of the intermediate body 100a according to the embodiment, wherein Figure 2B yes Figure 2A An enlarged view of area B. (Refer to the above.) Figure 1A and Figure 1B The aspects described are either described briefly or not repeatedly.

[0048] Reference Figure 2A and Figure 2B According to the embodiment, the mediator 100a and Figure 1A The difference in the intermediate body 100 may be that the lower intermediate body plate 100-1 and the upper intermediate body plate 100-2 are connected to each other via an inter-plate connection terminal 160. Specifically, the intermediate body 100a according to the embodiment may include a lower intermediate body plate 100-1, an upper intermediate body plate 100-2, and an inter-plate connection terminal 160. The lower intermediate body plate 100-1 and the upper intermediate body plate 100-2 may be connected to the reference... Figure 1A The lower intermediate plate 100-1 and the upper intermediate plate 100-2 of the intermediate body 100 are described identically. Therefore, the lower intermediate plate 100-1 and the upper intermediate plate 100-2 may each include Si. Furthermore, the intermediate body 100a according to the embodiment may correspond to the Si intermediate body.

[0049] In the intermediate body 100a according to the embodiment, the lower intermediate body plate 100-1 and the upper intermediate body plate 100-2 can be joined together by an inter-plate connection terminal 160. The inter-plate connection terminal 160 can be arranged between a first back pad 130b-1 of the lower intermediate body plate 100-1 and a second back pad 130b-2 of the upper intermediate body plate 100-2. The inter-plate connection terminal 160 may include, for example, solder. The solder can be used with reference to... Figure 1A The first external connection terminal 150 of the interposer 100 is described in the same manner. According to some embodiments, the inter-board connection terminal 160 may further include posts, and solder may be disposed on the posts. The posts may also be similar to those described in the reference... Figure 1A The first external connection terminal 150 of the intermediary 100 is described in the same way.

[0050] Because the lower intermediate plate 100-1 and the upper intermediate plate 100-2 can be bonded to each other via inter-plate connection terminals 160, an adhesive layer 165 can be disposed between the lower intermediate plate 100-1 and the upper intermediate plate 100-2. For example, the adhesive layer 165 can fill the space between the lower intermediate plate 100-1 and the upper intermediate plate 100-2 and can cover the side surface of the inter-plate connection terminals 160. The adhesive layer 165 may include, for example, a non-conductive film (NCF). Generally, NCF can be used as an adhesive layer when semiconductor chips are bonded by thermocompression bonding (TCB) in a semiconductor chip stacking process. However, in the intermediate 100a according to the embodiment, the material of the adhesive layer 165 is not limited to NCF. Furthermore, according to some embodiments, an underfill or molding member (such as epoxy molding compound (EMC)) instead of the adhesive layer 165 can fill the space between the lower intermediate plate 100-1 and the upper intermediate plate 100-2.

[0051] Figure 3A and Figure 3B These are cross-sectional views of mediators 100b and 100c according to the embodiments. (Refer to the above.) Figures 1A to 2B The aspects described are either described briefly or not repeatedly.

[0052] Reference Figure 3A According to the implementation method, the mediator 100b and Figure 1A The difference between the intermediate body 100 and the intermediate body 100b may be that the intermediate body 100b may further include a first redistribution layer 100-3. Specifically, the intermediate body 100b according to the embodiment may include a lower intermediate body plate 100-1, an upper intermediate body plate 100a-2, and a first redistribution layer 100-3. The lower intermediate body plate 100-1 and the upper intermediate body plate 100a-2 may be compared with reference to... Figure 1A The lower plate 100-1 and upper plate 100-2 of the mediator 100 are described in the same way. However, as Figure 3A As shown, the second front pad 130f-2 may be omitted in the upper plate 100a-2 of the intermediate body. However, according to some embodiments, the second front pad 130f-2 may be retained in the upper plate 100a-2 of the intermediate body.

[0053] The lower intermediate plate 100-1 and the upper intermediate plate 100a-2 may each include Si and can be bonded to each other via HCB. Therefore, the intermediate 100b according to the embodiment can correspond to a Si intermediate. However, in the intermediate 100b according to the embodiment, the lower intermediate plate 100-1 and the upper intermediate plate 100a-2 are not limited to being bonded via HCB, and can be bonded to each other via inter-plate connection terminal 160.

[0054] The first redistribution layer 100-3 may be disposed on the upper plate 100a-2 of the intermediate body. However, the first redistribution layer 100-3 is not limited thereto, and may also be disposed on the lower plate 100-1 of the intermediate body. When the first redistribution layer 100-3 is disposed on the lower plate 100-1 of the intermediate body, the first redistribution layer 100-3 can serve as a... Figure 3B The second redistribution layer 100-4 of the intermediate body 100c has the same structure arranged on the lower plate 100-1 of the intermediate body.

[0055] The first redistribution layer 100-3 may include a first redistribution host layer 101-3, a first redistribution line 110-3, and a first redistribution pad 130-3. The first redistribution host layer 101-3 may include, for example, a photoimageable dielectric (PID) or photoimageable polyimide (PIP) resin, and may also include inorganic pillars. However, the material of the first redistribution host layer 101-3 is not limited to the materials described above. For example, the first redistribution host layer 101-3 may include polyimideisoindro quirazorindione (PIQ), polyimide (PI), polybenzoxazole (PBO), etc.

[0056] The first redistribution line 110-3 may be arranged in the first redistribution body layer 101-3. When the first redistribution line 110-3 comprises multiple layers, multiple first redistribution lines 110-3 in different layers may be connected to each other via vias. The first redistribution line 110-3 may be connected to the interconnect line 114 of the second interconnect layer 110-2 of the intermediate upper plate 100a-2. For reference, the first redistribution line 110-3 may be connected to the Al pad 118 of the second interconnect layer 110-2 via vias. When the second front pad 130f-2 is arranged on the second interconnect layer 110-2, the first redistribution line 110-3 may be connected to the second front pad 130f-2 via vias.

[0057] The first redistribution pad 130-3 may be disposed on the upper surface of the first redistribution layer 100-3. External connection terminals 1350, 1450 and 1550 of the semiconductor devices 1300, 1400 and 1500 mounted on the interposer 100b may be disposed on the first redistribution pad 130-3.

[0058] Reference Figure 3B According to the embodiment, the mediator 100c and Figure 3A The difference between the intermediary 100b and the intermediary 100c is that the intermediary 100c may also include a second redistribution layer 100-4. Specifically, according to the embodiment, the intermediary 100c may include a lower intermediary plate 100a-1, an upper intermediary plate 100a-2, a first redistribution layer 100-3, and a second redistribution layer 100-4. The lower intermediary plate 100a-1, the upper intermediary plate 100a-2, and the first redistribution layer 100-3 may be connected with… Figure 3A The lower intermediate plate 100-1, upper intermediate plate 100a-2, and first redistribution layer 100-3 of the intermediate body 100b are the same. However, as Figure 3B As shown, the first front pad 130f-1 may be omitted in the lower plate 100a-1 of the intermediate body. However, according to some embodiments, the first front pad 130f-1 may be retained in the lower plate 100a-1 of the intermediate body.

[0059] The lower intermediate plate 100a-1 and the upper intermediate plate 100a-2 may each include Si and can be bonded to each other via HCB. Therefore, the intermediate 100c according to the embodiment can correspond to a Si intermediate. In the intermediate 100c according to the embodiment, the lower intermediate plate 100a-1 and the upper intermediate plate 100a-2 are not limited to being bonded via HCB, and can be bonded to each other via inter-plate connection terminals 160.

[0060] The second redistribution layer 100-4 can be arranged on the lower plate 100a-1 of the intermediate body. The second redistribution layer 100-4 may include a second redistribution main layer 101-4, a second redistribution line 110-4, and a second redistribution pad 130-4. The second redistribution layer 100-4 may differ from the first redistribution layer 100-3 in terms of arrangement. Furthermore, the second redistribution pad 130-4 may differ from the first redistribution pad 130-3 in terms of size, pitch, etc. Therefore, the connection relationship and / or the number of layers of the second redistribution line 110-4 may differ from the connection relationship and / or the number of layers of the first redistribution line 110-3. In addition, the overall structure and materials of the second redistribution layer 100-4 may be substantially the same as those of the first redistribution layer 100-3.

[0061] The second redistribution line 110-4 can be connected to the interconnect line 114 of the first interconnect layer 110-1 of the lower intermediate plate 100a-1. For reference, the second redistribution line 110-4 can be connected to the Al pad 118 of the first interconnect layer 110-1 via a via. When the first front pad 130f-1 is disposed on the first interconnect layer 110-1, the second redistribution line 110-4 can be connected to the first front pad 130f-1 via a via.

[0062] The second redistribution pad 130-4 can be disposed on the lower surface of the second redistribution layer 100-4. For example... Figure 3B As shown, the first external connection terminal 150 may be arranged on the second redistribution pad 130-4.

[0063] Figures 4A to 4C These are cross-sectional views of mediators 100d, 100e, and 100f according to the embodiment. (Refer to above) Figures 1A to 3B The aspects described are either described briefly or not repeatedly.

[0064] Reference Figure 4A According to the embodiment, the intermediary 100d can be coupled to the lower intermediary plate 100-1 and the upper intermediary plate 100-2a in the direction of connection. Figure 1AThe intermediate body 100 is different. Specifically, according to the embodiment, the intermediate body 100d may include a lower intermediate body plate 100-1 and an upper intermediate body plate 100-2a. Except for the joining direction of the lower intermediate body plate 100-1 and the upper intermediate body plate 100-2a, the lower intermediate body plate 100-1 and the upper intermediate body plate 100-2a may be connected to a reference... Figure 1A The lower intermediate plate 100-1 and the upper intermediate plate 100-2 of the intermediate body 100 are described in the same way.

[0065] The lower intermediate plate 100-1 and the upper intermediate plate 100-2a may each include Si and can be bonded to each other via HCB. Therefore, the intermediate 100d according to the embodiment can correspond to a Si intermediate. In the intermediate 100d according to the embodiment, the lower intermediate plate 100-1 and the upper intermediate plate 100-2a are not limited to being bonded via HCB, and can be bonded to each other via inter-plate connection terminals 160.

[0066] In the mediator 100d according to the embodiment, the lower mediator plate 100-1 and the upper mediator plate 100-2a can be coupled to each other via their back sides and front sides. Specifically, in the mediator 100d according to the embodiment, the back side of the lower mediator plate 100-1 can be coupled to the front side of the upper mediator plate 100-2a. Therefore, the first back side pad 130b-1 of the lower mediator plate 100-1 can be coupled to the corresponding second front side pad 130f-2a of the upper mediator plate 100-2a. Furthermore, the first protective layer 135-1 of the lower mediator plate 100-1 (e.g., the first back side protective layer 135b-1) can be coupled to the second protective layer 135-2 of the upper mediator plate 100-2a (e.g., the second front side protective layer 135f-2). In this disclosure, "front side" can refer to the side including the first interconnect layer or the second interconnect layer (e.g., the side adjacent to the first interconnect layer or the second interconnect layer). The back side may refer to the side that includes the first main layer or the second main layer (e.g., the back side may refer to the side adjacent to the upper surface of the first main layer or the second main layer). The upper surface may refer to the topmost or topmost layer of the layer or structure, or the surface facing upwards (e.g., along the positive z-direction). The lower surface may refer to the bottommost or bottommost layer of the layer or structure, or the surface facing downwards (e.g., along the negative z-direction).

[0067] In the intermediate 100d according to the embodiment, the external connection terminals 1350, 1450, and 1550 of the semiconductor devices 1300, 1400, and 1500 can be arranged on a second back-side pad 130b-2 on the back side of the upper plate 100-2a of the intermediate. Furthermore, the second back-side pad 130b-2 can be directly connected to the second through electrode 120-2. Therefore, with... Figure 1A Compared to the second back side pad 130b-2 and the second through electrode 120-2 of the intermediate body 100 upper plate 100-2, the intermediate body 100... Figure 4AThe second back pad 130b-2 and the second through electrode 120-2 of the upper plate 100-2a of the intermediate body 100d can be arranged to have a smaller pitch.

[0068] Reference Figure 4B According to the embodiment, the intermediary body 100e can be coupled to the lower intermediary plate 100-1a and the upper intermediary plate 100-2a in the direction of connection. Figure 1A The intermediate body 100e differs from the intermediate body 100e in the embodiment. Specifically, the intermediate body 100e according to the embodiment may include a lower intermediate body plate 100-1a and an upper intermediate body plate 100-2a. Except for the coupling direction, the lower intermediate body plate 100-1a and the upper intermediate body plate 100-2a may be associated with... Figure 1A The lower intermediate plate 100-1 and the upper intermediate plate 100-2 of the intermediate body 100 are described in the same way.

[0069] The lower intermediate plate 100-1a and the upper intermediate plate 100-2a may each include Si and can be bonded to each other via HCB. Therefore, the intermediate 100e according to the embodiment can correspond to a Si intermediate. In the intermediate 100e according to the embodiment, the lower intermediate plate 100-1a and the upper intermediate plate 100-2a are not limited to being bonded via HCB, and can be bonded to each other via inter-plate connection terminals 160.

[0070] In the mediator 100e according to the embodiment, the lower mediator plate 100-1a and the upper mediator plate 100-2a can be coupled to each other via their front sides. Specifically, in the mediator 100e according to the embodiment, the front side of the lower mediator plate 100-1a can be coupled to the front side of the upper mediator plate 100-2a. Therefore, the first front side pad 130f-1 of the lower mediator plate 100-1a can be coupled to the corresponding second front side pad 130f-2 of the upper mediator plate 100-2a. Furthermore, the first protective layer 135-1 (e.g., the first front protective layer 135f-1) of the lower mediator plate 100-1a can be coupled to the second protective layer 135-2 (e.g., the second front protective layer 135f-2) of the upper mediator plate 100-2a.

[0071] In the intermediate body 100e according to the embodiment, the external connection terminals 1350, 1450, and 1550 of the semiconductor devices 1300, 1400, and 1500 can be arranged on a second back-side pad 130b-2 on the back side of the upper plate 100-2a of the intermediate body. Furthermore, the second back-side pad 130b-2 can be directly connected to the second through electrode 120-2. Therefore, with... Figure 1A Compared to the second back side pad 130b-2 and the second through electrode 120-2 of the intermediate body 100 upper plate 100-2, the intermediate body 100... Figure 4BThe second back pad 130b-2 and the second through electrode 120-2 of the upper plate 100-2a of the intermediate body 100e can be arranged to have a smaller pitch.

[0072] Reference Figure 4C According to the embodiment, the intermediary body 100f can be connected with the lower intermediary plate 100-1a and the upper intermediary plate 100-2 in the joining direction. Figure 1A The intermediate body 100 is different. Specifically, according to the embodiment, the intermediate body 100f may include a lower intermediate body plate 100-1a and an upper intermediate body plate 100-2. Except for the coupling direction, the lower intermediate body plate 100-1a and the upper intermediate body plate 100-2 may be associated with... Figure 1A The lower intermediate plate 100-1 and the upper intermediate plate 100-2 of the intermediate body 100 are described in the same way.

[0073] The lower intermediate plate 100-1a and the upper intermediate plate 100-2 may each include Si and can be bonded to each other via HCB. Therefore, the intermediate 100f according to the embodiment can correspond to a Si intermediate. In the intermediate 100f according to the embodiment, the lower intermediate plate 100-1a and the upper intermediate plate 100-2 are not limited to being bonded via HCB, and can be bonded to each other via inter-plate connection terminals 160.

[0074] In the mediator 100f according to the embodiment, the lower mediator plate 100-1a and the upper mediator plate 100-2 can be coupled to each other via their front and back sides. Specifically, in the mediator 100f according to the embodiment, the front side of the lower mediator plate 100-1a can be coupled to the back side of the upper mediator plate 100-2. Therefore, the first front pad 130f-1 of the lower mediator plate 100-1a can be coupled to the corresponding second back pad 130b-2 of the upper mediator plate 100-2. Furthermore, the first protective layer 135-1 of the lower mediator plate 100-1a (e.g., the first front protective layer 135f-1) can be coupled to the second protective layer 135-2 of the upper mediator plate 100-2 (e.g., the second back protective layer 135b-2).

[0075] Figure 5 This is a cross-sectional view of the semiconductor package 1000 according to an embodiment. (See also...) Figure 1A and Figure 1B describe Figure 5 And briefly describe or non-repeatedly describe the above references. Figures 1A to 4C The aspects described.

[0076] Reference Figure 5The semiconductor package 1000 according to an embodiment may include an interposer 100, a package substrate 1200, semiconductor devices 1300, 1400 and 1500, and an external sealing member 1600. The semiconductor package 1000 according to an embodiment may also include an underfill member 1650.

[0077] For example, intermediary 100 can be with Figure 1A The intermediate 100 corresponds to the intermediate 100. Therefore, the intermediate 100 may include a lower intermediate plate 100-1 and an upper intermediate plate 100-2, wherein the lower intermediate plate 100-1 and the upper intermediate plate 100-2 can be coupled to each other via HCB. In the semiconductor package 1000 according to the embodiment, the intermediate 100 is not limited to Figure 1A Intermediary 100. For example, replacing Figure 1A Intermediary 100, respectively refer to Figure 2A , Figure 3A , Figure 3B and Figures 4A to 4C One of the intermediates 100a to 100f may be included in the semiconductor package 1000.

[0078] The package substrate 1200 can be a support substrate, and the intermediate 100, semiconductor devices 1300, 1400, and 1500, etc., can be stacked on the package substrate 1200. At least one layer of interconnects can be provided in the package substrate 1200. When the interconnects comprise multiple layers, the interconnects of different layers can be connected to each other through vias. The package substrate 1200 can be formed based on, for example, a ceramic substrate, a printed circuit board (PCB), a glass substrate, an intermediate substrate, etc. A second external connection terminal 1250 can be disposed on the lower surface of the package substrate 1200. The semiconductor package 1000 according to the embodiment can be stacked on an external system substrate, motherboard, etc., via the second external connection terminal 1250.

[0079] Intermediate 100 can be mounted on package substrate 1200 via first external connection terminal 150. Semiconductor devices 1300, 1400, and 1500 can be mounted on package substrate 1200 using intermediate 100 as a medium. Intermediate 100 can connect semiconductor devices 1300, 1400, and 1500 to each other. Furthermore, intermediate 100 can connect semiconductor devices 1300, 1400, and 1500 to package substrate 1200. In the semiconductor package 1000 according to an embodiment, intermediate 100 can be used to convert or transmit electrical signals between semiconductor devices 1300, 1400, and 1500. Therefore, active devices may not be disposed in intermediate 100. However, according to some embodiments, intermediate 100 may include means for controlling signal transmission. Although not shown, underfill may be filled between intermediate 100 and package substrate 1200 and between first external connection terminal 150. According to some embodiments, underfill may be replaced by an adhesive layer or adhesive film.

[0080] Semiconductor devices 1300, 1400 and 1500 may include a first semiconductor device 1300, a second semiconductor device 1400 and a third semiconductor device 1500.

[0081] The first semiconductor device 1300 can be stacked on the central portion of the intermediate 100 via a third external connection terminal 1350. The first semiconductor device 1300 may have a chip or package structure. In the semiconductor package 1000 according to an embodiment, the first semiconductor device 1300 may have a chip structure. For example, the first semiconductor device 1300 may include a logic chip. Multiple logic devices may be included in the first semiconductor device 1300. Logic devices may include, for example, AND, NAND, OR, NOR, XOR, XNOR, inverter (INV), adder (ADD), delay (DLY), filter (FIL), multiplexer (MXT / MXIT), OR / AND / inverter (OAI), AND / OR (AO), AND / OR / inverter (AOI), D flip-flop, reset flip-flop, master-slave flip-flop, latch, counter, or buffer device. Logic devices can perform various signal processing (such as analog signal processing, analog-to-digital (A / D) conversion, control, etc.). The first semiconductor device 1300 may be referred to as a central processing unit (CPU) chip, microprocessor unit (MPU) chip, graphics processing unit (GPU) chip, neural processing unit (NPU) chip, system-on-glass (SOG) chip, application-specific integrated circuit (ASIC) chip, application processor (AP) chip, control chip, etc., based on its function.

[0082] In the semiconductor package 1000 according to an embodiment, the first semiconductor device 1300 may have a chip structure, which may include a system-on-a-chip (SoC) structure or a chiplet structure. In an SoC structure, various systems can be integrated into a single chip. Therefore, the first semiconductor device 1300 with an SoC structure can perform computation, data storage, A / D signal conversion, etc., on a single chip. In a chiplet structure, logic chips can be divided into individual functional chips, and the chips can be interconnected. The first semiconductor device 1300 with a chiplet structure can overcome the performance limitations of a single chip.

[0083] In the semiconductor package 1000 according to an embodiment, a second semiconductor device 1400 adjacent to the left side of the first semiconductor device 1300 can be stacked on the left side of the intermediate 100 via a fourth external connection terminal 1450. Furthermore, a third semiconductor device 1500 adjacent to the right side of the first semiconductor device 1300 can be stacked on the right side of the intermediate 100 via a fifth external connection terminal 1550. However, the positions of the second semiconductor device 1400 and the third semiconductor device 1500 are not limited to this. For example, the positions of the second semiconductor device 1400 and the third semiconductor device 1500 can be interchanged.

[0084] In the semiconductor package 1000 according to an embodiment, either the second semiconductor device 1400 or the third semiconductor device 1500 may be a memory device, and the other may be a logic device. Furthermore, according to some embodiments, both the second semiconductor device 1400 and the third semiconductor device 1500 may be memory devices.

[0085] For example, when the second semiconductor device 1400 is a memory device and the third semiconductor device 1500 is a logic device, the second semiconductor device 1400 may include a memory package (e.g., a high-bandwidth memory (HBM) package). However, the second semiconductor device 1400 is not limited to an HBM package. For example, the second semiconductor device 1400 may have a single-chip structure or may have a general package structure different from an HBM package. (Refer to...) Figures 6A to 6C A more detailed description is given of aspects of the second semiconductor device 1400 having an HBM package structure.

[0086] The third semiconductor device 1500, as a logic device, may include a logic chip. For example, the third semiconductor device 1500 may include a modem chip that supports communication with the first semiconductor device 1300. However, the type of the third semiconductor device 1500 is not limited to a modem chip. For example, the third semiconductor device 1500 may include other types of logic chips for supporting the operation of the first semiconductor device 1300 or for performing various signal processing operations together with or independently of the first semiconductor device 1300.

[0087] When both the second semiconductor device 1400 and the third semiconductor device 1500 are memory devices, both the second semiconductor device 1400 and the third semiconductor device 1500 may include an HBM package. Figure 5 In the semiconductor package 1000, two semiconductor devices serving as memory devices may be arranged adjacent to the first semiconductor device 1300. However, the number of semiconductor devices serving as memory devices is not limited to two. For example, three or more semiconductor devices serving as memory devices may be arranged adjacent to the first semiconductor device 1300 serving as logic devices. Furthermore, each of the three or more semiconductor devices may include an HBM package.

[0088] The external sealing member 1600 can cover and seal the semiconductor devices 1300, 1400, and 1500 on the interposer 100. For example... Figure 5 As shown, the external sealing member 1600 may not cover the upper surfaces of the semiconductor devices 1300, 1400, and 1500. However, according to some embodiments, the external sealing member 1600 may cover the upper surface of at least one of the semiconductor devices 1300, 1400, and 1500.

[0089] The semiconductor package 1000 according to the embodiment may have including Figure 1A The intermediate 100 has a SiP structure. Therefore, as described above, the semiconductor package 1000 according to the embodiment can have improved SI / PI characteristics without additionally arranged capacitors, and the size of the SiP can be reduced. To describe the SiP with reduced size in more detail, Figure 5 The diagram shows the additional capacitors CAPd, indicated by dashed lines, located on both sides of the package substrate 1200. In this way, when the additional capacitors CAPd are arranged on the package substrate 1200, the area of ​​the package substrate 1200 can be increased by as much as the size and solder area of ​​the additional capacitors CAPd. For example, when the additional capacitors CAPd are arranged, the size of the package substrate 1200 can be increased by... Figure 5The length corresponding to 2×W1 in the figure is such that the overall size of the SiP can be increased. However, in the case of the semiconductor package 1000 according to the embodiment, it is not necessary to arrange the additional capacitor CAPd, which can help reduce the size of the SiP.

[0090] For reference, the structure of the semiconductor package 1000 according to the embodiment is referred to as a 2.5D package structure. A 2.5D package structure can be a concept relative to a three-dimensional (3D) package structure in which all semiconductor chips are stacked together without intermediaries. Both 2.5D and 3D package structures can be included in a SiP structure.

[0091] Figures 6A to 6C yes Figure 5 A more detailed cross-sectional view of the structure of the second semiconductor device 1400 in the semiconductor package 1000. (Refer to...) Figure 5 describe Figures 6A to 6C And briefly describe or non-repeatedly describe the above references. Figures 1A to 5 The aspects described.

[0092] Reference Figure 6A In the semiconductor package 1000 according to an embodiment, the second semiconductor device 1400 may have an HBM package structure. Specifically, the second semiconductor device 1400 may include a substrate chip 200, a memory chip 300, a first connection terminal 400, and an inner sealing member 500. For example... Figure 6A As shown, the substrate chip 200 may have a larger size than the memory chip 300 disposed above it. However, the size of the substrate chip 200 is not limited to this. For example, according to some embodiments, the substrate chip 200 may have a substantially the same size as the memory chip 300.

[0093] The substrate chip 200 may include a chip body 201, an active layer 210, a through electrode 220, a connection pad 230, and a protective layer 240. The chip body 201 may include semiconductor elements (e.g., Si or Ge). Furthermore, the chip body 201 may include compound semiconductors (such as SiC, GaAs, InAs, or InP). The chip body 201 may have a silicon-on-insulator (SOI) structure. For example, the chip body 201 may include a buried oxide (BOX) layer. The chip body 201 may include conductive regions (e.g., doped wells or structures such as doped source / drain regions). The chip body 201 may have various device isolation structures (such as shallow trench isolation (STI) structures).

[0094] Active layer 210 may include an integrated circuit layer and an interconnect layer on the integrated circuit layer. Generally, the integrated circuit layer may include various types of devices. For example, the integrated circuit layer may include various active and / or passive devices (such as transistors, logic devices, memory devices, system-on-a-scale integration (LSI), complementary metal-oxide-semiconductor (CMOS) imaging sensors (CIS), microelectromechanical systems (MEMS)). Transistors may include, for example, bipolar junction transistors (BJTs) or field-effect transistors (FETs) (such as planar FETs, FinFETs, etc.). Logic devices may be related to the above-mentioned... Figure 5 The first semiconductor device 1300 of the semiconductor package 1000 is described in the same way. The memory device may include volatile memory devices (such as dynamic random access memory (DRAM) or static random access memory (SRAM)) or non-volatile memory devices (such as flash memory, phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM) or resistive random access memory (RRAM)).

[0095] An interconnect layer can connect at least two devices to each other, connect devices to conductive regions of the chip body 201, or connect devices to the first connection terminal 400. Furthermore, the interconnect layer can connect the through electrode 220 to the first connection terminal 400. The interconnect layer may include, for example, interconnect lines, contacts, or vias. In the second semiconductor device 1400 according to an embodiment, the active layer 210 may be disposed below the chip body 201 and the through electrode 220. However, according to some embodiments, the active layer 210 may be disposed above the chip body 201 and the through electrode 220.

[0096] In the second semiconductor device 1400 according to an embodiment, the substrate chip 200 may include a plurality of logic devices in the integrated circuit layer of the active layer 210. The substrate chip 200 may be disposed below the memory chip 300, may combine signals from the memory chip 300 and transmit the combined signals to the outside, and may transmit signals and power from the outside to the memory chip 300. Therefore, the substrate chip 200 may be referred to as a buffer chip or an interface chip.

[0097] According to some embodiments, the base chip 200 may include a controller for controlling signal transmission between the memory chip 300 and an external device. When the base chip 200 includes a controller, it may be referred to as a logic chip or a control chip. Furthermore, according to some embodiments, the base chip 200 may include a power management integrated circuit (PMIC) for managing power or a clock. Additionally, according to some embodiments, the base chip 200 may include logic devices for operation. For reference, when the base chip 200 is referred to as a buffer chip, etc., the memory chip 300 may be referred to as a core chip.

[0098] In the second semiconductor device 1400 according to the embodiment, the substrate chip 200 is not limited to a buffer chip or a logic chip. For example, the substrate chip 200 may include a plurality of memory devices in the integrated circuit layer of the active layer 210. Therefore, the substrate chip 200 may include a memory chip.

[0099] The through-electrode 220 can penetrate the chip body 201 to extend from the upper surface to the lower surface of the chip body 201. According to some embodiments, the through-electrode 220 can extend into the active layer 210. In the second semiconductor device 1400 according to an embodiment, the chip body 201 may include Si; therefore, the through-electrode 220 may be referred to as a TSV. Other structures or materials of the through-electrode 220 may be related to… Figure 1A The first through electrode 120-1 of the lower plate of the intermediate body 100-1 is described in the same way.

[0100] Connector pad 230 may be disposed on the upper surface of chip body 201 and may be connected to through electrode 220. Protective layer 240 may be disposed on the upper surface of chip body 201. Other materials or structures of connector pad 230 and protective layer 240 may be related to... Figure 1A The first pad 130-1 and the first protective layer 135 of the lower intermediate plate 100-1 are described in the same way. Although not shown, the protective layer may also be disposed on the lower surface of the active layer 210.

[0101] Memory chips 300 may be stacked on the substrate chip 200. In the second semiconductor device 1400 according to an embodiment, eight memory chips 300 (e.g., first memory chips 300-1 to eighth memory chips 300-8) may be stacked on the substrate chip 200. However, the number of memory chips 300 stacked on the substrate chip 200 is not limited to eight. For example, two to seven memory chips 300 or nine or more memory chips 300 may be stacked on the substrate chip 200.

[0102] For reference, in the second semiconductor device 1400, the memory chip 300 may include 4n (n is a natural number) memory chips. Therefore, the second semiconductor device 1400 may include a multiple of four memory chips 300 (e.g., four, eight, or twelve memory chips 300). Furthermore, every four memory chips 300 can be tested and operated together by having the same stacking ID (identifier). For example, when the second semiconductor device 1400 includes eight memory chips 300, the first memory chips 300-1 to the fourth memory chips 300-4 may have a first stacking ID, and the fifth memory chips 300-5 to the eighth memory chips 300-8 may have a second stacking ID. However, the second semiconductor device 1400 is not limited to a multiple of four memory chips 300 and corresponding stacking IDs. For example, the second semiconductor device 1400 may include a multiple of two memory chips 300 and corresponding stacking IDs, or a multiple of eight memory chips 300 and corresponding stacking IDs.

[0103] The first memory chip 300-1 to the eighth memory chip 300-8 may have substantially the same horizontal dimensions and internal structure. However, the eighth memory chip 300-8, which is arranged at the top, may not include a through electrode. Furthermore, as... Figure 6A As shown, the eighth memory chip 300-8 may have a greater thickness than the other memory chips 300. According to some embodiments, the thickness of the eighth memory chip 300-8 can be adjusted so that the overall height of the second semiconductor device 1400 can be adjusted. In the following description, for convenience, the detailed structure of the memory chips 300 will be described using the first memory chip 300-1.

[0104] The first memory chip 300-1 may include a chip body 301, an active layer 310, a through electrode 320, a connection pad 330, and a protective layer 340. Aspects of the chip body 301 may be the same as those described regarding the chip body 201 of the substrate chip 200.

[0105] Active layer 310 may include multiple memory devices. For example, active layer 310 may include volatile memory devices (such as DRAM or SRAM) or non-volatile memory devices (such as PRAM, MRAM, FeRAM, or RRAM). For example, in the second semiconductor device 1400, first memory chip 300-1 may include a DRAM device in active layer 310. Therefore, first memory chip 300-1 may be a DRAM chip. Furthermore, because the second semiconductor device 1400 may be an HBM package, first memory chip 300-1 may be a DRAM chip for HBM.

[0106] The through electrode 320 may pass through the chip body 301 or may pass through the chip body 301 to extend into the active layer 310. For example, the first memory chip 300-1 may be divided into cell regions and pad regions, and when the through electrode 320 is formed only in the pad regions, the through electrode 320 may pass through the chip body 301 and extend into the active layer 310. Other aspects of the through electrode 320 may be the same as those described regarding the through electrode 220 of the substrate chip 200.

[0107] The connection pad 330 may include a lower connection pad 330d disposed on the lower surface of the active layer 310 and an upper connection pad 330u disposed on the upper surface of the chip body 301. In a typical semiconductor chip, the chip pad may be disposed on the lower surface of the active layer. Therefore, the lower connection pad 330d may correspond to the chip pad of the first memory chip 300-1.

[0108] The lower connection pad 330d can be connected to the interconnect line of the interconnect layer of the active layer 310 on the lower surface of the chip body 301. Furthermore, the lower connection pad 330d can be connected to the through electrode 320 via the interconnect line of the interconnect layer. The upper connection pad 330u can be connected to the through electrode 320 on the upper surface of the chip body 301. Other aspects of the connection pad 330 are the same as those described regarding the connection pad 230 of the substrate chip 200.

[0109] The protective layer 340 may include a lower protective layer 340d disposed on the lower surface of the active layer 310 and an upper protective layer 340u disposed on the upper surface of the chip body 301. Other aspects of the protective layer 340 may be the same as those described with respect to the protective layer 240 of the substrate chip 200.

[0110] In the second semiconductor device 1400 according to an embodiment, a memory chip 300 can be stacked on a substrate chip 200 or on another memory chip 300 directly below the substrate chip 200 via inter-chip interconnect terminals 360. For example, the inter-chip interconnect terminals 360 can be arranged between the connection pad 230 of the substrate chip 200 and the lower connection pad 330d of the first memory chip 300-1. Furthermore, the inter-chip interconnect terminals 360 can be arranged between the upper connection pad 330u of the lower memory chip 300 and the lower connection pad 330d of the upper memory chip 300 in two adjacent memory chips 300. The inter-chip interconnect terminals 360 can be connected to the above-mentioned... Figure 2A The inter-board connection terminal 160 of the intermediary 100a is described in the same way. For example, the inter-chip connection terminal 360 may include solder or pillars.

[0111] In the second semiconductor device 1400 according to an embodiment, memory chips 300 can be stacked via inter-chip interconnect terminals 360. Therefore, an adhesive layer 610 can be disposed between the substrate chip 200 and the first memory chip 300-1, and between two adjacent memory chips 300. For example, the adhesive layer 610 can fill between the substrate chip 200 and the first memory chip 300-1, and between two adjacent memory chips 300, and can cover the side surface of the inter-chip interconnect terminals 360. Furthermore, as... Figure 6A As shown, adhesive layer 610 may protrude from and cover the side surface of memory chip 300. According to some embodiments, although adhesive layer 610 may protrude from the side surface of memory chip 300, adhesive layer 610 may only cover a portion of the side surface of each of the memory chips 300. In this case, adhesive layer 610 at the upper end and adhesive layer 610 at the lower end may not be bonded to each other and may be separated from each other at the side surface of each of the memory chips 300. Adhesive layer 610 may include, for example, NCF. However, the material of adhesive layer 610 is not limited to NCF.

[0112] A first connection terminal 400 may be disposed on the lower surface of the substrate chip 200. The first connection terminal 400 may be connected to the interconnect line of the interconnect layer of the active layer 210. In addition, the first connection terminal 400 may be connected to the through electrode 220 via the interconnect line of the interconnect layer. Although not shown, a chip pad may be disposed on the lower surface of the substrate chip 200, and the first connection terminal 400 may be disposed on the chip pad.

[0113] The first connection terminal 400 may have a structure similar to the inter-chip connection terminal 360 described above. For example, the first connection terminal 400 may include solder. According to some embodiments, the first connection terminal 400 may include pillars and solder. The aspects regarding the pillars and solder of the first connection terminal 400 may be related to those regarding... Figure 1A The first external connection terminal 150 of the intermediary 100 is described in the same way.

[0114] The inner sealing member 500 may surround the side surface of the memory chip 300 on the substrate chip 200. For example... Figure 6A As shown, the inner sealing member 500 may not cover the upper surface of the uppermost memory chip (e.g., the eighth memory chip 300-8). Therefore, the upper surface of the eighth memory chip 300-8 can be exposed through the inner sealing member 500. However, according to some embodiments, the inner sealing member 500 may cover the upper surface of the uppermost memory chip (e.g., the eighth memory chip 300-8). The inner sealing member 500 may include, for example, electromagnetic compatibility (EMC). However, the material of the inner sealing member 500 is not limited to EMC.

[0115] Reference Figure 6B In the semiconductor package 1000 according to the embodiment, the second semiconductor device 1400a may have an HBM package structure, but... Figure 6A The second semiconductor device 1400a differs in that it may also include a top dummy chip 600. Specifically, the second semiconductor device 1400a may include a substrate chip 200, a memory chip 300, a first connection terminal 400, an inner sealing member 500, and a top dummy chip 600. Aspects concerning the substrate chip 200, the memory chip 300, the first connection terminal 400, and the inner sealing member 500 are consistent with those concerning... Figure 6A The second semiconductor device 1400 is described in the same way. However, since the top dummy chip 600 can be added, the inner sealing member 500 can have a structure for covering the side surface of the top dummy chip 600.

[0116] In the second semiconductor device 1400a, a top dummy chip 600 can be stacked on top of the memory chip 300 via an adhesive layer 620. The top dummy chip 600 can be added according to the height standards of the second semiconductor device 1400a. For example, in the case of an HBM package, the height, area, etc., are defined according to the Joint Electronic Devices Engineering Committee (JEDEC) standard, and because the second semiconductor device 1400a is an HBM package, a top dummy chip 600 with an appropriate height can be arranged on the memory chip 300, so that the second semiconductor device 1400a can have a height according to the JEDEC standard.

[0117] In the second semiconductor device 1400a, because a top dummy chip 600 can be added, the eighth memory chip 300-8 can have a thickness similar to that of the other memory chips 300. However, the eighth memory chip 300-8 is not limited to this. According to some embodiments, even when the top dummy chip 600 is included, the eighth memory chip 300-8 can have a greater thickness than the other memory chips 300. However, when the overall height of the second semiconductor device can be adjusted by adjusting the thickness of the eighth memory chip 300-8, the top dummy chip 600 can be omitted.

[0118] Reference Figure 6C In the semiconductor package 1000 according to the embodiment, although the second semiconductor device 1400b may have an HBM package structure, the second semiconductor device 1400b and Figure 6AThe second semiconductor device 1400 differs in that the memory chip 300a can be stacked via HCBs. Specifically, the second semiconductor device 1400b may include a substrate chip 200, a memory chip 300a, a first connection terminal 400, and an inner sealing member 500. Aspects concerning the substrate chip 200, the first connection terminal 400, and the inner sealing member 500 are consistent with those concerning... Figure 6A The second semiconductor device 1400 is described in the same way. However, since the memory chip 300a can be stacked via HCB without inter-chip connection terminals 360, an adhesive layer may not be filled between the memory chip 300a and the substrate chip 200, or between adjacent memory chips 300a.

[0119] In the second semiconductor device 1400b, a memory chip 300a can be stacked on the substrate chip 200 or on other memory chips 300a directly below it via HCB. Furthermore, according to some embodiments, the TCB method can be used to stack the memory chips 300a via HCB. More specifically, as described above, connection pads 230 and protective layers 240 can be disposed on the upper surface of the substrate chip 200. Furthermore, connection pads 330 and protective layers 340 can be disposed on the lower and upper surfaces of each of the memory chips 300a. The connection pads 230 of the substrate chip 200 can be disposed buried in the protective layer 240 and can have an upper surface exposed through the protective layer 240. Similarly, the connection pads 330 of the memory chip 300a can be disposed buried in the protective layer 340 and can have an upper or lower surface exposed through the protective layer 340. The protective layers 240 and 340 may include insulating layers (such as SiO2, SiN, SiCN, etc.).

[0120] The connection pad 230 of the substrate chip 200 can be bonded to the lower connection pad 330d of the first memory chip 300a-1, and the protective layer 240 of the substrate chip 200 can be bonded to the lower protective layer 340d of the first memory chip 300a-1. Therefore, an HCB can be formed between the substrate chip 200 and the first memory chip 300a-1. Furthermore, in the memory chip 300a, between two adjacent memory chips 300, the upper connection pad 330u and upper protective layer 340u on the upper surface of the lower memory chip 300a can be bonded to the lower connection pad 330d and lower protective layer 340d on the lower surface of the upper memory chip 300a. Therefore, an HCB can be formed.

[0121] Figure 7A and Figure 7B These are cross-sectional views of semiconductor packages 1000a and 1000b according to embodiments. (Refer to...) Figure 5 describe Figure 7A and Figure 7BAnd briefly describe or non-repeatedly describe the above references. Figures 1A to 6C The aspects described.

[0122] Reference Figure 7A According to the embodiment, the semiconductor package 1000a and Figure 5 The difference between the semiconductor package 1000 and the semiconductor package 1000a is that the semiconductor package 1000a may only include a first semiconductor device 1300 and a second semiconductor device 1400. In detail, the semiconductor package 1000a according to the embodiment may include an interposer 100, a package substrate 1200, a first semiconductor device 1300 and a second semiconductor device 1400, and an external sealing member 1600.

[0123] Intermediary 100 can be, for example Figure 1A The intermediate 100 corresponds to the intermediate 100. Therefore, the intermediate 100 may include a lower intermediate plate 100-1 and an upper intermediate plate 100-2, and the lower intermediate plate 100-1 and the upper intermediate plate 100-2 may be coupled to each other via HCB. In the semiconductor package 1000a according to the embodiment, the intermediate 100 is not limited to Figure 1A Intermediary 100. For example, replacing Figure 1A Intermediary 100, respectively refer to Figure 2A , Figure 3A , Figure 3B and Figures 4A to 4C One of the intermediates 100a to 100f may be included in the semiconductor package 1000a. Aspects regarding the package substrate 1200 and the external sealing member 1600 may be related to... Figure 5 The packaging substrate 1200 and the external sealing member 1600 of the semiconductor package 1000 are described in the same way.

[0124] Semiconductor devices 1300 and 1400 may include a first semiconductor device 1300 and a second semiconductor device 1400. The first semiconductor device 1300 may be stacked on the right side of the intermediate 100 via a third external connection terminal 1350. The first semiconductor device 1300 may have a chip or package structure. In the semiconductor package 1000a according to an embodiment, the first semiconductor device 1300 may have a chip structure. For example, the first semiconductor device 1300 may include a logic chip. Other aspects of the first semiconductor device 1300 may be discussed in relation to... Figure 5 The first semiconductor device 1300 of the semiconductor package 1000 is described in the same way as the semiconductor package 1000.

[0125] The second semiconductor device 1400 may include a memory device. The second semiconductor device 1400 may include a memory package (e.g., an HBM package). However, the second semiconductor device 1400 is not limited to an HBM package. For example, the second semiconductor device 1400 may have a single-chip structure or may have a general package structure different from an HBM package. Aspects of the second semiconductor device 1400 may be related to aspects concerning... Figure 5 The second semiconductor device 1400 of the semiconductor package 1000 is described in the same way. Furthermore, aspects concerning the second semiconductor device 1400 having an HBM package structure are consistent with those concerning... Figures 6A to 6C The second semiconductor devices 1400, 1400a and 1400b are described in the same way.

[0126] Reference Figure 7B According to the embodiment, the semiconductor package 1000b and Figure 5 The difference between the semiconductor package 1000 and the semiconductor package 1000b is that the semiconductor package 1000b may only include the first semiconductor device 1300. In detail, the semiconductor package 1000b according to the embodiment may include an interposer 100, a package substrate 1200, a first semiconductor device 1300 and an external sealing member 1600.

[0127] Intermediary 100 can be, for example Figure 1A The intermediate 100 corresponds to the intermediate 100. Therefore, the intermediate 100 may include a lower intermediate plate 100-1 and an upper intermediate plate 100-2, and the lower intermediate plate 100-1 and the upper intermediate plate 100-2 may be coupled to each other via HCB. In the semiconductor package 1000b according to the embodiment, the intermediate 100 is not limited to Figure 1A Intermediary 100. For example, replacing Figure 1A Intermediary 100, respectively refer to Figure 2A , Figure 3A , Figure 3B and Figures 4A to 4C One of the intermediates 100a to 100f may be included in the semiconductor package 1000b. Aspects regarding the package substrate 1200 and the external sealing member 1600 may be related to... Figure 5 The packaging substrate 1200 and the external sealing member 1600 of the semiconductor package 1000 are described in the same way.

[0128] A first semiconductor device 1300 may be stacked on the intermediate 100 via a third external connection terminal 1350. The first semiconductor device 1300 may have a chip or package structure. In the semiconductor package 1000b according to an embodiment, the first semiconductor device 1300 may have a chip structure. For example, the first semiconductor device 1300 may include a logic chip. Other aspects of the first semiconductor device 1300 may be discussed in relation to... Figure 5The first semiconductor device 1300 of the semiconductor package 1000 is described in the same way as the semiconductor package 1000.

[0129] Figures 8A to 8F This is a cross-sectional view illustrating a method for manufacturing an intermediate substrate 100S according to an embodiment. (Refer to...) Figure 1A and Figure 1B describe Figures 8A to 8F And briefly describe or non-repeatedly describe the above references. Figures 1A to 7B The aspects described.

[0130] Reference Figure 8A According to the method for manufacturing an intermediate substrate 100S according to an embodiment, firstly, a first through electrode 120-1 and a first capacitor 140-1 can be formed on an initial first host layer 101-1S (for example, the first through electrode 120-1 and the first capacitor 140-1 can be formed in the initial first host layer 101-1S) to form a first intermediate lower plate substrate 100-1Sa. Here, the initial first host layer 101-1S may have a wafer-level dimension; therefore, the first intermediate lower plate substrate 100-1Sa may have a wafer-level dimension and may include multiple initial intermediate lower plates. The aspects regarding the first through electrode 120-1 and the first capacitor 140-1 are related to the aspects regarding... Figure 1A The first through electrode 120-1 and the first capacitor 140-1 of the lower plate 100-1 of the intermediate body 100 are described in the same way.

[0131] Reference Figure 8B After forming the first through electrode 120-1 and the first capacitor 140-1, a first interconnect layer 110-1 can be formed on the initial first host layer 101-1S to form the second interposer substrate 100-1Sb. The first interconnect layer 110-1 can be formed to have wafer-level dimensions for completely covering the initial first host layer 101-1S. The first interconnect layer 110-1 may include an interlayer insulating layer 112, interconnects 114, vias 116, and Al pads 118. Figure 8B For convenience, only the interlayer insulating layer 112 and the interconnect 114 are shown in the diagram. Aspects regarding the first interconnect layer 110-1 can be found in relation to aspects regarding... Figure 1A The first interconnect layer 110-1 of the intermediary lower plate 100-1 of the intermediary 100 is described in the same way.

[0132] Reference Figure 8C After forming the first interconnect layer 110-1, a first pad 130-1 (e.g., a first front pad 130f-1) can be formed on the first interconnect layer 110-1. Subsequently, a first external connection terminal 150 can be formed on the first front pad 130f-1. Aspects of the first front pad 130f-1 and the first external connection terminal 150 are related to those concerning... Figure 1AThe first front pad 130f-1 and the first external connection terminal 150 of the lower plate 100-1 of the intermediary body 100 are described in the same way. By forming the first front pad 130f-1 and the first external connection terminal 150, the third intermediary body lower plate substrate 100-1Sc can be formed.

[0133] Reference Figure 8D After forming the first external connection terminal 150, the third intermediate substrate 100-1Sc can be flipped and fixed to the first carrier (e.g., the first carrier substrate) 2000 using an adhesive layer 2500. Subsequently, a portion of the back side of the initial first body layer 101-1S can be removed by grinding and etching, exposing the first through electrode 120-1. Next, a first back-side protective layer 135b-1 and a first back-side pad 130b-1 can be formed on the back side of the initial first body layer 101-1S. Aspects of the first back-side protective layer 135b-1 and the first back-side pad 130b-1 are related to those concerning... Figure 1A The first back-side protective layer 135b-1 and the first back-side pad 130b-1 of the intermediary lower plate 100-1 of the intermediary 100 are described in the same way. An intermediary lower plate substrate 100-1S can be formed by forming the first back-side protective layer 135b-1 and the first back-side pad 130b-1. The intermediary lower plate substrate 100-1S may have wafer-level dimensions and may include multiple intermediary lower plates 100-1.

[0134] Reference Figure 8E It can be accessed through Figures 8A to 8D The intermediate upper plate substrate 100-2S is formed by a process. For example, the intermediate upper plate substrate 100-2S can be fixed to the second carrier (e.g., the second carrier substrate) 3000 by using an adhesive layer 3500. However, when forming the intermediate upper plate substrate 100-2S, it is possible to... Figure 8C In the corresponding process, only the second front pad 130f-2 is formed. That is, the first external connection terminal 150 may not be formed on the upper intermediate substrate 100-2S. The upper intermediate substrate 100-2S may also have a wafer-level size and may include multiple upper intermediate substrates 100-2. The processes for forming the lower intermediate substrate 100-1S and the processes for forming the upper intermediate substrate 100-2S can be performed separately and in parallel with each other.

[0135] Reference Figure 8FNext, the upper intermediate substrate 100-2S can be bonded to the lower intermediate substrate 100-1S via HCB. As shown, the back side of the upper intermediate substrate 100-2S can be bonded to the back side of the lower intermediate substrate 100-1S via HCB. Through the bonding of the lower intermediate substrate 100-1S and the upper intermediate substrate 100-2S, the intermediate substrate 100S can be manufactured. The intermediate substrate 100S may have wafer-level dimensions and may include… Figure 1A Multiple intermediate bodies 100. Subsequently, the intermediate body base 100S can be separated from the structure mounted on the intermediate body base 100S by cutting to manufacture as Figure 1A The intermediary body 100.

[0136] For reference, to describe HCB in more detail, the lower intermediate substrate 100-1S and the upper intermediate substrate 100-2S may undergo plasma processing and ultrapure cleaning processes prior to the bonding process, thus forming OH dangling bonds on the first back-side protective layer 135b-1 and the second back-side protective layer 135b-2. Subsequently, the upper intermediate substrate 100-2S can be bonded to the lower intermediate substrate 100-1S at room temperature, such that the first back-side pad 130b-1 and the second back-side pad 130b-2 can be aligned with each other. In the early stages of bonding, the OH dangling bonds in the first back-side protective layer 135b-1S of the lower intermediate substrate 100-1S and the second back-side protective layer 135b-2 of the upper intermediate substrate 100-2S can form hydrogen bonds. These hydrogen bonds may have relatively low adhesive strength.

[0137] Subsequently, heat is applied through annealing, thus forming a solid bond structure between the first back-side pad 130b-1 and the second back-side pad 130b-2. Specifically, through annealing, metal expansion and metal diffusion processes can occur in the first back-side pad 130b-1 and the second back-side pad 130b-2, and through these processes, the first back-side pad 130b-1 and the second back-side pad 130b-2 can be integrally formed. Annealing can change the hydrogen bonds between the first back-side protective layer 135b-1 and the second back-side protective layer 135b-2 into oxide bonds. For example, using a simplified chemical formula, through high-temperature annealing, -OH + -OH → O + H₂O. Oxide bonds can have greater adhesive strength than hydrogen bonds. As a result, the lower intermediate substrate 100-1S and the upper intermediate substrate 100-2S can be firmly bonded together by HCB with high adhesive strength.

[0138] Figure 9A and Figure 9B This is a cross-sectional view illustrating a method for manufacturing an intermediate substrate 100aS according to an embodiment. (Refer to...) Figure 2A and Figure 2B describe Figure 9Aand Figure 9B And briefly describe or non-repeatedly describe the above references. Figures 8A to 8F The aspects described.

[0139] Reference Figure 9A According to the method for manufacturing the intermediate substrate 100aS according to the embodiment, in Figure 8E After the intermediate body upper plate substrate 100-2S is formed, the inter-plate connection terminal 160 can be formed on the second back side pad 130b-2.

[0140] Reference Figure 9B Next, the upper intermediate substrate 100-2S can be bonded to the lower intermediate substrate 100-1S via inter-board connection terminals 160. The TCB method can be used for bonding via inter-board connection terminals 160. Furthermore, an adhesive layer 165 can be filled between the lower intermediate substrate 100-1S and the upper intermediate substrate 100-2S. The adhesive layer 165 may include, for example, NCF. However, the adhesive layer 165 is not limited to NCF. The intermediate substrate 100aS can be manufactured by bonding the lower intermediate substrate 100-1S and the upper intermediate substrate 100-2S. The intermediate substrate 100aS may have wafer-level dimensions and may include… Figure 2A Multiple intermediate bodies 100a. The intermediate body substrate 100aS can subsequently be separated from the structure mounted on top of the intermediate body substrate 100aS by cutting, in order to be manufactured as... Figure 2A The intermediary 100a.

[0141] Figure 10 This is a cross-sectional view used to describe a method for manufacturing an intermediate substrate 100bS according to an embodiment. (See reference...) Figure 3A describe Figure 10 And briefly describe or non-repeatedly describe the above references. Figures 8A to 8F The aspects described.

[0142] Reference Figure 10 According to the method for manufacturing intermediate substrate 100bS according to the embodiment, in Figure 8F After the intermediate substrate 100S is formed, a first redistribution layer substrate 100-3S can be formed on the second interconnect layer 110-2 of the intermediate substrate 100-2S. The first redistribution layer substrate 100-3S can be formed to have wafer-level dimensions for completely covering the second interconnect layer 110-2. The first redistribution layer substrate 100-3S may include a first redistribution body layer 101-3, a first redistribution line 110-3, and a first redistribution pad 130-3. Aspects of the first redistribution body layer 101-3, the first redistribution line 110-3, and the first redistribution pad 130-3 are related to those of the first redistribution body layer 101-3, the first redistribution line 110-3, and the first redistribution pad 130-3. Figure 3AThe first redistribution body layer 101-3, the first redistribution line 110-3, and the first redistribution pad 130-3 of the first redistribution layer 100-3 of the intermediary body 100b are described in the same way.

[0143] An intermediate substrate 100bS can be fabricated by forming a first redistribution layer substrate 100-3S. The intermediate substrate 100bS may have wafer-level dimensions and may include... Figure 3A Multiple intermediate bodies 100b. Subsequently, the intermediate body substrate 100bS can be separated from the structure mounted on the intermediate body substrate 100bS by cutting to manufacture as Figure 3A The intermediary 100b.

[0144] Figures 11A to 11E This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor package 1000 according to an embodiment. (Refer to...) Figure 5 describe Figures 11A to 11E And briefly describe or non-repeatedly describe the above references. Figures 1A to 10 The aspects described.

[0145] Reference Figure 11A According to the method for manufacturing a semiconductor package 1000 according to an embodiment, semiconductor devices 1300, 1400, and 1500 are first mounted on a dielectric substrate 100S. Semiconductor devices 1300, 1400, and 1500 may include, for example, a first semiconductor device 1300, a second semiconductor device 1400, and a third semiconductor device 1500, and can be mounted on the dielectric substrate 100S via external connection terminals 1350, 1450, and 1550. The dielectric substrate 100S may have wafer-level dimensions and may include... Figure 1A Multiple intermediaries 100. Aspects concerning semiconductor devices 1300, 1400, and 1500 are related to... Figure 5 The semiconductor devices 1300, 1400, and 1500 of the semiconductor package 1000 are described in the same way.

[0146] Reference Figure 11B After mounting semiconductor devices 1300, 1400, and 1500, an external sealing member 1600Sa can be formed to seal semiconductor devices 1300, 1400, and 1500 onto the intermediate substrate 100S. The external sealing member 1600Sa can cover the side and top surfaces of semiconductor devices 1300, 1400, and 1500. The material, etc., of the external sealing member 1600Sa can be determined in accordance with relevant regulations. Figure 5 The same applies to the external sealing member 1600 of the semiconductor package 1000. In this disclosure, the external sealing member 1600Sa may also be referred to as a sealant.

[0147] Reference Figure 11CAfter the external sealing member 1600Sa is formed, the upper part of the external sealing member 1600Sa can be removed by back-side grinding (B / G). By removing the upper part of the external sealing member 1600Sa, the upper surfaces of the semiconductor devices 1300, 1400 and 1500 can be exposed through the external sealing member 1600S.

[0148] Reference Figure 11D After backside grinding (B / G), the intermediate substrate 100S and the structure above the intermediate substrate 100S (also referred to as the stacked structure in this disclosure) can be separated into multiple intermediate semiconductor packages by sawing (S). In other words, the stacked structure (i.e., wafer-structured) can be cut into multiple individual dies. Each die can be an intermediate semiconductor package 1000M. Each intermediate semiconductor package 1000M may include an intermediate 100 and corresponding semiconductor devices 1300, 1400, and 1500 stacked on the respective intermediate 100.

[0149] Reference Figure 11E After manufacturing the intermediate semiconductor package 1000M, the intermediate semiconductor package 1000M can be mounted on the package substrate 1200 via the first external connection terminal 150, thus enabling the complete manufacturing of the semiconductor package 1000. The semiconductor package 1000 can be connected to... Figure 5 The semiconductor package 1000 is compatible.

[0150] Therefore, the true technical protection scope of this disclosure should be defined by the appended claims.

[0151] Although this disclosure contains many specific implementation details, these should not be construed as limiting the scope of the claims. Specific features described in the context of individual implementations in this disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single implementation may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in a particular combination, one or more features from a combination may, in some cases, be excluded from that combination, and the combination may refer to a sub-combination or a variation of a sub-combination.

Claims

1. An intermediary, comprising: Intermediate body lower plate; as well as The upper plate of the intermediary body is located above the lower plate of the intermediary body and is attached to the lower plate of the intermediary body. The lower intermediate plate includes: a first main body layer; a first capacitor below the first main body layer; a first interconnect layer below the first capacitor; and a first pad on the upper surface of the first main body layer. The intermediate upper plate includes: a second main body layer; a second capacitor above the second main body layer; a second interconnect layer above the second capacitor; and a second pad on the lower surface of the second main body layer. The lower intermediate plate is connected to the upper intermediate plate, and the first pad is electrically connected to the second pad.

2. The intermediary according to claim 1, wherein, The lower and upper intermediate plates are bonded together by a hybrid copper bonding system.

3. The intermediary according to claim 1, wherein, The lower and upper intermediate plates are connected to each other via connecting terminals.

4. The intermediary according to claim 1, wherein, The lower intermediate plate also includes a first through electrode extending through the first body layer, the first through electrode connecting the first interconnect layer to the first pad, and The intermediate plate also includes a second through electrode extending through the second main body layer, which connects the second interconnect layer to the second pad.

5. The intermediary according to claim 1, wherein, The lower surface of the first interconnect layer is located on the front side of the lower intermediate plate, and the upper surface of the first main body layer is located on the back side of the lower intermediate plate. The upper surface of the second interconnect layer is located on the front side of the upper plate of the intermediate body, and the lower surface of the second main body layer is located on the back side of the upper plate of the intermediate body. Each of the first and second capacitors includes an integrated stacked capacitor, and The first capacitor is adjacent to the front side of the lower plate of the intermediate body, and the second capacitor is adjacent to the front side of the upper plate of the intermediate body.

6. The intermediary according to claim 1, wherein, The capacitance of the second capacitor is less than or equal to the capacitance of the first capacitor.

7. The intermediary according to any one of claims 1 to 6, further comprising: One or more redistribution layers, below the first interconnect layer and / or above the second interconnect layer.

8. An intermediary, comprising: Intermediate body lower plate; as well as The upper plate of the intermediary body is located above the lower plate of the intermediary body and is attached to the lower plate of the intermediary body. The intermediate lower plate includes: a first main body layer; a first capacitor on the first main body layer; a first interconnect layer on the first capacitor; a first pad on the first main body layer or on the first interconnect layer; and a first through electrode extending through the first main body layer. The intermediate plate includes: a second body layer; a second capacitor on the second body layer; a second interconnect layer on the second capacitor; a second pad on the second body layer or on the second interconnect layer; and a second through electrode extending through the second body layer. The lower intermediate plate is connected to the upper intermediate plate, and the first pad is electrically connected to the second pad.

9. The intermediary according to claim 8, wherein, The lower and upper intermediate plates are joined together by hybrid copper bonding or connecting terminals.

10. The intermediary according to claim 8, wherein, The first interconnect layer is located on the front side of the lower intermediate plate, and the first main body layer is located on the back side of the lower intermediate plate, wherein the second interconnect layer is located on the front side of the upper intermediate plate, and the second main body layer is located on the back side of the upper intermediate plate. The lower plate and upper plate of the intermediate body form a combined structure, which includes one of the following: The first bonding structure is that the back side of the lower plate of the intermediate body is bonded to the back side of the upper plate of the intermediate body. The second bonding structure is that the back side of the lower plate of the intermediate body is bonded to the front side of the upper plate of the intermediate body. The third connecting structure involves the front side of the lower plate of the intermediate body connecting to the back side of the upper plate of the intermediate body; and The fourth connection structure is that the front side of the lower plate of the intermediate body is connected to the front side of the upper plate of the intermediate body.

11. A semiconductor package, comprising: Packaging substrate; An intermediary is mounted on a packaging substrate. The intermediary includes a lower intermediary plate and a upper intermediary plate bonded to the lower intermediary plate. as well as At least one semiconductor device is mounted on the intermediate. The lower intermediate plate includes: a first main body layer; a first capacitor below the first main body layer; a first interconnect layer below the first capacitor; and a first pad on the upper surface of the first main body layer. The intermediate upper plate includes: a second main body layer; a second capacitor above the second main body layer; a second interconnect layer above the second capacitor; and a second pad on the lower surface of the second main body layer. The lower intermediate plate is connected to the upper intermediate plate, and the first pad is electrically connected to the second pad.

12. The semiconductor package of claim 11, wherein, The lower and upper intermediate plates are joined together by hybrid copper bonding or connecting terminals.

13. The semiconductor package of claim 11, wherein, Each of the first and second capacitors includes an integrated stacked capacitor, and The capacitance of the second capacitor is less than or equal to the capacitance of the first capacitor.

14. The semiconductor package of claim 11, wherein, The lower intermediate plate also includes a first through electrode extending through the first body layer, the first through electrode connecting the first interconnect layer to the first pad, and The intermediate plate also includes a second through electrode extending through the second main body layer, which connects the second interconnect layer to the second pad.

15. The semiconductor package according to any one of claims 11 to 14, further comprising: One or more redistribution layers, below the first interconnect layer and / or above the second interconnect layer.

16. The semiconductor package according to any one of claims 11 to 14, wherein, The at least one semiconductor device includes: A first semiconductor device, including a logic chip; and At least one second semiconductor device is located adjacent to the first semiconductor device. The at least one second semiconductor device includes a memory chip or a memory package.

17. A method for manufacturing a semiconductor package, the method comprising: Prepare an intermediate body base, which includes multiple intermediate bodies arranged along a first direction; A plurality of semiconductor devices are mounted on an intermediate substrate along a second direction perpendicular to a first direction, the plurality of semiconductor devices being arranged along the first direction; The plurality of semiconductor devices are sealed on an intermediate substrate using a sealant to form a stacked structure; The stacked structure is separated into a plurality of intermediate semiconductor packages, each of the plurality of intermediate semiconductor packages including a corresponding intermediate of the plurality of intermediate bodies and at least one semiconductor device of the plurality of semiconductor devices; as well as The corresponding intermediate semiconductor package among the plurality of intermediate semiconductor packages is mounted on the packaging substrate. Each of the plurality of intermediaries includes: The corresponding intermediate lower plate includes: a first body layer; a first capacitor below the first body layer; a first interconnect layer below the first capacitor; a first pad on the upper surface of the first body layer; and a first through electrode extending through the first body layer, the first through electrode connecting the first interconnect layer and the first pad; and A corresponding upper intermediate plate is located above and attached to a corresponding lower intermediate plate. The corresponding upper intermediate plate includes: a second body layer; a second capacitor above the second body layer; a second interconnect layer above the second capacitor; a second pad on the lower surface of the second body layer; and a second through electrode extending through the second body layer, the second through electrode connecting the second interconnect layer and the second pad.

18. The method according to claim 17, wherein, The steps for preparing the intermediate substrate include: Manufacturing intermediate body lower plate base; Manufacturing intermediate body upper plate substrate; and The upper substrate of the intermediate body is attached to the lower substrate of the intermediate body.

19. The method according to claim 18, in, The steps for manufacturing the intermediate substrate include: A first through electrode and a first capacitor are formed in the initial first main body layer; A first interconnect layer is formed above the first through electrode and the first capacitor; and A first pad is formed on the back side of the initial first main body layer. The steps for manufacturing the intermediate body upper plate substrate include: A second through electrode and a second capacitor are formed in the initial second main body layer; A second interconnect layer is formed above the second through electrode and the second capacitor; and A second pad is formed on the back side of the initial second main body layer, and The step of bonding the upper substrate of the intermediary to the lower substrate of the intermediary includes electrically connecting the first pad to the second pad.

20. The method according to claim 19, wherein, The steps of attaching the upper substrate of the intermediate to the lower substrate of the intermediate also include: The upper substrate of the intermediate body is bonded to the lower substrate of the intermediate body by means of mixed copper bonding or connection terminals.

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