Deposition mask and electronic device manufactured therefrom

Abstract

A deposition mask and an electronic device manufactured therefrom are provided. The deposition mask includes a mask frame in which a cell opening is formed, a film on an upper portion of the mask frame, and an electrode pattern portion on the mask frame.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0179555, filed on December 5, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] Some aspects of embodiments of this disclosure relate to deposition masks and electronic devices manufactured therefrom. Background Technology

[0003] A head-mounted display (HMD) is an image display device worn on a user's body in the form of glasses or a helmet to create an image that is focused close to the user's eyes. Head-mounted displays can enable virtual reality (VR) or augmented reality (AR).

[0004] Head-mounted displays use multiple lenses to magnify images displayed by a small display device. Therefore, display devices used in head-mounted displays can provide high-resolution images, for example, images with a resolution of 3,000 PPI (pixels per inch) or higher. For this purpose, OLEDoS (organic light-emitting diodes on silicon), as small, high-resolution organic light-emitting display devices, are used as display devices for head-mounted displays. OLEDoS is a device for displaying images in which organic light-emitting diodes (OLEDs) are located on a semiconductor silicon wafer substrate including complementary metal-oxide-semiconductor (CMOS).

[0005] To manufacture high-resolution display panels with a resolution of 3,000 PPI or higher, deposition masks designed for high resolution can be used. For example, a deposition mask can be manufactured by forming a film with multiple pixel openings on a substrate such as a silicon wafer and partially etching the substrate to form cell openings that expose the pixel openings.

[0006] This deposition mask can be used in deposition processes for forming organic light-emitting layers on a backplane substrate. During the deposition process, the backplane substrate can be positioned on the deposition mask, and the deposition source can be placed below the deposition mask to provide vapor-phase deposition material. The vapor-phase deposition material can be deposited on the backplane substrate through pixel openings in the deposition mask.

[0007] The information disclosed in this background section is only intended to enhance the understanding of the background art, and therefore the information discussed in this background section does not necessarily constitute prior art. Summary of the Invention

[0008] Some aspects of embodiments of this disclosure include deposition masks capable of relatively improving the deposition accuracy of organic light-emitting layers deposited on a backplane substrate, and electronic devices thereby manufactured.

[0009] However, the aspects of embodiments according to this disclosure are not limited to those set forth herein. These and other aspects of embodiments according to this disclosure will become more apparent to those skilled in the art upon which this disclosure pertains from the following detailed description of the disclosure.

[0010] According to some embodiments of the present disclosure, the deposition mask includes: a mask frame having cell openings formed therein; a film on the upper part of the mask frame; and an electrode pattern portion on the mask frame.

[0011] According to some embodiments, the electrode pattern portion surrounds the cell opening while being spaced apart from it.

[0012] According to some embodiments, the cell openings are configured as multiple, and the electrode pattern portions are located between the cell openings.

[0013] According to some embodiments, the electrode pattern portion is introduced from the upper surface of the mask frame into the interior of the mask frame.

[0014] According to some embodiments, the film is divided into a mask unit region on the upper part of the unit opening and a grid region on the upper part of the mask frame that does not include the mask unit region, and the electrode pattern portion is superimposed on the grid region.

[0015] According to some embodiments, the film includes an inorganic layer on the upper part of a mask frame and a nitride layer on the upper part of the inorganic layer, wherein the electrode pattern portion is on the lower part of the inorganic layer.

[0016] According to some embodiments, the electrode pattern portion includes a first electrode pattern and a second electrode pattern, the second electrode pattern being spaced apart from the first electrode pattern and having a polarity opposite to that of the first electrode pattern.

[0017] According to some embodiments, the electrode pattern portion also includes an insulating pattern between the first electrode pattern and the second electrode pattern.

[0018] According to some embodiments, a plurality of cell openings are provided, the plurality of cell openings are spaced apart in a first direction and in a second direction intersecting the first direction, and the electrode pattern portion extends in the first direction and the second direction to surround the plurality of cell openings.

[0019] According to some embodiments, the electrode pattern portion extends in a linear form in a first direction and a second direction.

[0020] According to some embodiments, the electrode pattern portion extends in a curved shape in a first direction and a second direction.

[0021] According to some embodiments of the present disclosure, an electronic device includes a display device manufactured by a deposition mask, wherein the deposition mask includes: a mask frame having cell openings formed therein; a film on the upper part of the mask frame; and an electrode pattern portion on the mask frame.

[0022] According to some embodiments, the electrode pattern portion surrounds the cell opening while being spaced apart from it.

[0023] According to some embodiments, the cell openings are configured as multiple, and the electrode pattern portions are located between the cell openings.

[0024] According to some embodiments, the electrode pattern portion is introduced from the upper surface of the mask frame into the interior of the mask frame.

[0025] According to some embodiments, the electrode pattern portion includes a first electrode pattern and a second electrode pattern, the second electrode pattern being spaced apart from the first electrode pattern and having a polarity opposite to that of the first electrode pattern.

[0026] According to some embodiments, the electrode pattern portion also includes an insulating pattern between the first electrode pattern and the second electrode pattern.

[0027] According to some embodiments, a plurality of cell openings are provided, the plurality of cell openings are spaced apart in a first direction and in a second direction intersecting the first direction, and the electrode pattern portion extends in the first direction and the second direction to surround the plurality of cell openings.

[0028] According to some embodiments, the electrode pattern portion extends in a linear form in a first direction and a second direction.

[0029] According to some embodiments, the electrode pattern portion extends in a curved shape in a first direction and a second direction.

[0030] According to some embodiments of this disclosure, by forming an electrode pattern portion around the cell opening on the mask frame to increase the adhesion between the film and the backing substrate, the deposition accuracy of the organic light-emitting layer deposited on the backing substrate can be relatively improved.

[0031] The features of embodiments according to this disclosure are not limited to those described above, and many more features are included in the following description of this disclosure. Attached Figure Description

[0032] The above and other aspects and features of embodiments of the present disclosure will become more apparent from the accompanying drawings, which describe aspects of some embodiments of the present disclosure in more detail, in which: Figure 1 This is an exploded perspective view illustrating a display device according to some embodiments of the present disclosure; Figure 2 It is used to show Figure 1 A plan view of the display device shown; Figure 3 It is shown Figure 2 The equivalent circuit diagram of the example of the first sub-pixel shown; Figure 4 It is shown Figure 1 A floor plan of an example display panel shown; Figure 5 It is shown Figure 4 An enlarged plan view of an example of the display area; Figure 6 It is shown Figure 4 A magnified plan view of another example of the display area; Figure 7 It shows along Figure 5 A cross-sectional view of an example display panel, taken by line I1-I1'; Figure 8 It shows along Figure 5 A cross-sectional view of another example of a display panel, taken by line I1-I1'; Figure 9 This is a perspective view showing an example of an electronic device; Figure 10 It is used to show Figure 9 An exploded perspective view of an electronic device; Figure 11 This is a perspective view showing another example of an electronic device; Figure 12 This is a view illustrating a deposition apparatus according to some embodiments of the present disclosure; Figure 13 It is shown Figure 12 The bottom view of the back panel base shown; Figure 14 This is a plan view illustrating a deposition mask according to some embodiments of the present disclosure; Figure 15 It is shown Figure 14 An enlarged plan view of the mask unit region shown; Figure 16 It shows along Figure 15 A cross-sectional view of an example deposition mask cut by line I2-I2'; Figure 17 yes Figure 16 A magnified view of part A; Figure 18 It shows along Figure 15 A cross-sectional view of another example of a deposition mask cut by line I2-I2'; Figure 19 yes Figure 18 A magnified view of part B; Figure 20 This is a cross-sectional view showing the state of contact between a deposition mask and a backing substrate according to some embodiments of the present disclosure; Figure 21 This is a block diagram of an electronic device according to some embodiments of the present disclosure; and Figure 22 This is a view illustrating an electronic device according to some embodiments of the present disclosure. Detailed Implementation

[0033] The aspects and features of embodiments of this disclosure, as well as methods of implementing them, will become more apparent from the following description of exemplary embodiments with reference to the accompanying drawings. However, embodiments of this disclosure are not limited to the exemplary embodiments disclosed herein, but can be implemented in various different ways. Exemplary embodiments are provided to make this disclosure thorough and to fully convey the scope of this disclosure to those skilled in the art. It will be noted that the scope of this disclosure is defined only by the claims.

[0034] As used herein, the phrase "element A on element B" means that element A can be directly located on element B and / or element A can be indirectly located on element B via another element C. Throughout the specification, the same reference numerals denote the same elements. The numbers, dimensions, ratios, angles, and quantities of elements given in the drawings are illustrative only and not limiting.

[0035] Although terms such as first, second, etc., are used to arbitrarily distinguish the elements described by these terms, and therefore these terms are not necessarily intended to indicate the time or other priority of these elements. These terms are only used to distinguish one element from another. Therefore, as used herein, within the scope of the art of this disclosure, a first element can be a second element.

[0036] Features of the various exemplary embodiments of this disclosure can be combined in part or in whole. As will be clearly understood by those skilled in the art, various interactions and operations are technically possible. Various exemplary embodiments can be practiced individually or in combination.

[0037] In the following, exemplary embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0038] Figure 1 This is an exploded perspective view illustrating a display device according to some embodiments of the present disclosure. Figure 2 It is used to show Figure 1 The plan view of the display device shown.

[0039] Reference Figure 1 and Figure 2The display device 10 according to some embodiments displays moving images (e.g., video images) or still images (e.g., static images). The display device 10 according to some embodiments can be employed by portable electronic devices such as mobile phones, smartphones, tablet PCs, mobile communication terminals, e-notebooks, e-readers, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). For example, the display device 10 according to some embodiments of this disclosure can be used as a display unit for televisions, laptop computers, monitors, electronic billboards, or Internet of Things (IoT) devices. Optionally, the display device 10 according to some embodiments of this disclosure can be applied to smartwatches, smartwatch phones, or head-mounted displays (HMDs) to realize virtual reality and augmented reality.

[0040] According to some embodiments, the display device 10 includes a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit 400, and a power supply circuit 500.

[0041] When viewed from above (e.g., in a plan view), the display panel 100 may have a shape resembling a rectangle. For example, when viewed from above (e.g., in a plan view), the display panel 100 may have a shape resembling a rectangle having a shorter side in a first direction DR1 and a longer side in a second direction DR2 intersecting the first direction DR1. In the display panel 100, the corner where the shorter side in the first direction DR1 and the longer side in the second direction DR2 intersect may be rounded with a predetermined curvature or may be a right angle. When viewed from above (e.g., in a plan view), the shape of the display panel 100 is not limited to a rectangular shape, but may be formed into a shape resembling other polygonal shapes, circular shapes, or elliptical shapes. When viewed from above (e.g., in a plan view), the shape of the display device 10 may follow the shape of the display panel 100, but the embodiments of this disclosure are not limited thereto.

[0042] The display panel 100 includes multiple pixels (PX), multiple scan lines (SL), multiple emission control lines (EL), multiple data lines (DL), a scan driver 610, an emission driver 620, and a data driver 700. For example... Figure 2 As shown, the display panel 100 can be divided into a display area DAA for displaying images and a non-display area NDA for not displaying images.

[0043] Multiple pixels PX can be located within the display area DAA. Pixels PX can be arranged in a matrix on the first direction DR1 and the second direction DR2. Scan lines SL and emission control lines EL can extend on the first direction DR1 and can be arranged on the second direction DR2. Data lines DL can extend on the second direction DR2 and can be arranged on the first direction DR1.

[0044] The multiple scan lines SL include multiple write scan lines GWL, multiple control scan lines GCL, and multiple bias scan lines GBL. The multiple emit control lines EL include multiple first emit control lines ECL1 and multiple second emit control lines ECL2.

[0045] Multiple pixels PX include multiple sub-pixels SP1, SP2, and SP3. The multiple sub-pixels SP1, SP2, and SP3 include, for example... Figure 3 The diagram shows multiple pixel transistors. These pixel transistors are formed via a semiconductor process and can be located on a semiconductor substrate SSUB (see [reference]). Figure 7 For example, the pixel transistor of the data driver 700 can be implemented as a complementary metal-oxide-semiconductor (CMOS) transistor. However, it should be understood that the embodiments of this disclosure are not limited thereto.

[0046] Each of the multiple sub-pixels SP1, SP2, and SP3 can be connected to a write scan line GWL, a control scan line GCL, a bias scan line GBL, a first emitt control line ECL1, a second emitt control line ECL2, and a data line DL. Each of the sub-pixels SP1, SP2, and SP3 can receive a data voltage from the data line DL according to the write scan signal from the write scan line GWL, and can allow the light-emitting element to emit light according to the data voltage.

[0047] The scan driver 610, the transmit driver 620, and the data driver 700 can be located in the non-display area NDA.

[0048] Scan driver 610 includes multiple scan transistors, and emitter driver 620 includes multiple light-emitting transistors. The multiple scan transistors and multiple light-emitting transistors are formed via semiconductor processes and can be formed on a semiconductor substrate SSUB (see [link to SSUB]). Figure 7 For example, multiple scanning transistors and multiple light-emitting transistors can be formed from CMOS transistors. However, it should be understood that the embodiments of this disclosure are not limited thereto.

[0049] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate a write scan signal based on the scan timing control signal SCS from the timing control circuit 400, and sequentially output the write scan signal to the write scan line GWL. The control scan signal output unit 612 may generate a control scan signal based on the scan timing control signal SCS, and sequentially output the control scan signal to the control scan line GCL. The bias scan signal output unit 613 may generate a bias scan signal based on the scan timing control signal SCS, and sequentially output the bias scan signal to the bias scan line GBL.

[0050] The transmit driver 620 includes a first transmit control driver 621 and a second transmit control driver 622. Each of the first transmit control driver 621 and the second transmit control driver 622 can receive a transmit timing control signal ECS from the timing control circuit 400. The first transmit control driver 621 can generate a first transmit control signal according to the transmit timing control signal ECS and sequentially output the first transmit control signal to the first transmit control line ECL1. The second transmit control driver 622 can generate a second transmit control signal according to the transmit timing control signal ECS and sequentially output the second transmit control signal to the second transmit control line ECL2.

[0051] The data driver 700 may include multiple data transistors, and the multiple data transistors may be formed via semiconductor processes and may be formed on a semiconductor substrate SSUB (see Figure 7 For example, multiple data transistors can be formed from CMOS transistors. However, it should be understood that the embodiments of this disclosure are not limited thereto.

[0052] The data driver 700 can receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the analog data voltage to the data line DL. In this case, sub-pixels SP1, SP2, and SP3 are selected by the write scan signal of the scan driver 610, and the data voltage can be applied to the selected sub-pixels SP1, SP2, and SP3.

[0053] The heat dissipation layer 200 may be stacked on the display panel 100 on a third direction DR3, which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be located on one surface of the display panel 100 (e.g., on the rear surface). The heat dissipation layer 200 is used to dissipate heat generated in the display panel 100. The heat dissipation layer 200 may include a metal layer made of metals such as silver (Ag), copper (Cu), and aluminum (Al) with high thermal conductivity, or a layer made of graphite.

[0054] Circuit board 300 can be electrically connected to the first pad (or "soldering pad") area PDA1 of display panel 100 using conductive adhesive components such as anisotropic conductive film (see...). Figure 4 Multiple first pads PD1 (see) Figure 4 Circuit board 300 can be a flexible printed circuit board made of a flexible material (e.g., a flexible film). Although in Figure 1 In the example shown, circuit board 300 is unfolded, but it can be bent. When circuit board 300 is bent, one end of it can be located on the rear surface of display panel 100 and / or the rear surface of heat dissipation layer 200. The other end of circuit board 300 can be attached to the first pad area PDA1 of display panel 100 (see [link to PDA1]) using conductive adhesive. Figure 4 Multiple first pads PD1 (see) Figure 4 One end of the circuit board 300 may be opposite to the other end of the circuit board 300.

[0055] The timing control circuit 400 can receive digital video data DATA and timing signals from an external source. In response to the timing signals, the timing control circuit 400 can generate a scan timing control signal SCS, a transmit timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver 610 and the transmit timing control signal ECS to the transmit driver 620. The timing control circuit 400 can also output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0056] The power supply circuit 500 can generate multiple panel driving voltages in response to an external power supply voltage. For example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT to apply to the display panel 100. (See below for further details.) Figure 3 Describe the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT.

[0057] Each of the timing control circuit 400 and the power supply circuit 500 can be implemented as an integrated circuit (IC) and attached to the surface of the circuit board 300. Scan timing control signal SCS, transmit timing control signal ECS, digital video data DATA, and data timing control signal DCS from the timing control circuit 400 can be supplied to the display panel 100 via the circuit board 300. The first drive voltage VSS, the second drive voltage VDD, and the third drive voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 via the circuit board 300.

[0058] Optionally, similar to the scan driver 610, transmit driver 620, and data driver 700, each of the timing control circuit 400 and power supply circuit 500 may be located in the non-display area NDA of the display panel 100. In this case, the timing control circuit 400 may include multiple timing transistors, and each power supply circuit 500 may include multiple power transistors. The multiple timing transistors and multiple power transistors can be formed by semiconductor processes and can be formed on a semiconductor substrate SSUB (see...). Figure 7 On the data driver 700. For example, multiple timing transistors and multiple power transistors can be formed by CMOS transistors. However, it should be understood that embodiments of this disclosure are not limited thereto. Each of the timing control circuit 400 and the power supply circuit 500 can be located in the data driver 700 and the first pad region PDA1 (see...). Figure 4 )between.

[0059] Figure 3 It is shown Figure 2 The equivalent circuit diagram of the example of the first sub-pixel shown. Although Figure 3 Various components in a subpixel according to some embodiments are shown, but embodiments of the present disclosure are not limited thereto, and according to some embodiments, a subpixel may include additional components or fewer components without departing from the spirit and scope of embodiments of the present disclosure.

[0060] Reference Figure 3 The first sub-pixel SP1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first emit control line ECL1, the second emit control line ECL2, and the data line DL. Additionally, the first sub-pixel SP1 can be connected to the first drive voltage line VSL, which is applied with a first drive voltage VSS equal to a low level; the second drive voltage line VDL, which is applied with a second drive voltage VDD equal to a high level; and the third drive voltage line VIL, which is applied with a third drive voltage VINT equal to the initialization voltage.

[0061] The first sub-pixel SP1 includes multiple transistors T1 to T6, a light-emitting element LE, a first capacitor CP1, and a second capacitor CP2.

[0062] The light-emitting element LE emits light according to a driving current Ids flowing in the channel of the first transistor T1. The amount of light emitted from the light-emitting element LE can be proportional to the driving current Ids. The first electrode of the light-emitting element LE can be an anode electrode, and the second electrode of the light-emitting element LE can be a cathode electrode. The light-emitting element LE can be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer located between the first electrode and the second electrode. However, it should be understood that this disclosure is not limited thereto. For example, the light-emitting element LE can be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor located between the first electrode and the second electrode. In this case, the light-emitting element LE can be a micro light-emitting diode.

[0063] The first transistor T1 may be a drive transistor used to control the source-drain current Ids (also known as "drive current") flowing between the source and drain electrodes according to the voltage applied to the gate electrode.

[0064] The second transistor T2 can be located between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by a write scan signal from the write scan line GWL, and connects one electrode of the first capacitor CP1 to the data line DL. Therefore, the data voltage of the data line DL can be applied to one electrode of the first capacitor CP1.

[0065] The third transistor T3 can be connected between the first node N1 and the second node N2. The third transistor T3 is turned on by the control scan signal controlling the scan line GCL, and connects the first node N1 to the second node N2. Therefore, if the gate electrode and source electrode of the first transistor T1 are connected to each other, the first transistor T1 can function like a diode.

[0066] The fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first emitter control signal of the first emitter control line ECL1, and connects the second node N2 to the third node N3. Therefore, the drive current Ids of the first transistor T1 can be supplied to the light-emitting element LE. The fifth transistor T5 can be located between the third node N3 and the third drive voltage line VIL. The fifth transistor T5 is turned on by the bias scan signal of the bias scan line GBL, and connects the third node N3 to the third drive voltage line VIL. Therefore, the third drive voltage VINT of the third drive voltage line VIL can be applied to the first electrode of the light-emitting element LE.

[0067] The sixth transistor T6 can be located between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 is turned on by the second emitter control signal of the second emitter control line ECL2, and connects the source electrode of the first transistor T1 to the second drive voltage line VDL. Therefore, the second drive voltage VDD of the second drive voltage line VDL can be applied to the source electrode of the first transistor T1.

[0068] A first capacitor CP1 is formed between the first node N1 and the drain electrode of the second transistor T2. A second capacitor CP2 is formed between the gate electrode of the first transistor T1 and the second drive voltage line VDL.

[0069] Each of the first transistors T1 to the sixth transistor T6 can be a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, each of the first transistors T1 to the sixth transistor T6 can be a p-type MOSFET, but is not limited thereto. Each of the first transistors T1 to the sixth transistor T6 can be an n-type MOSFET. Optionally, some of the first transistors T1 to the sixth transistor T6 can be p-type MOSFETs, and the other transistors can be n-type MOSFETs.

[0070] Despite Figure 3 In the example shown, the first sub-pixel SP1 includes six transistors T1 to T6 and two capacitors CP1 and CP2. However, it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to... Figure 3 The equivalent circuit diagram is shown. For example, the number of transistors and capacitors in the first sub-pixel SP1 is not limited to... Figure 3 The quantities shown.

[0071] Additionally, the equivalent circuit diagrams for the second sub-pixel SP2 and the third sub-pixel SP3 can be referenced above. Figure 3 The equivalent circuit diagram of the first sub-pixel SP1 is basically the same, and therefore, some redundant descriptions can be omitted.

[0072] Figure 4 It is shown Figure 1 A floor plan of an example display panel shown.

[0073] Reference Figure 4 According to some embodiments, the display area DAA of the display panel 100 includes a plurality of pixels PX arranged in a matrix. According to some embodiments, the non-display area NDA of the display panel 100 includes a scan driver 610, a transmit driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad area PDA1, and a second pad area PDA2.

[0074] The scan driver 610 can be located on a first side of the display area DAA, and the transmit driver 620 can be located on a second side of the display area DAA. For example, the scan driver 610 can be located on one side of the display area DAA in the first direction DR1, and the transmit driver 620 can be located on the opposite side of the display area DAA in the first direction DR1. However, it should be understood that the embodiments of this disclosure are not limited thereto. The scan driver 610 and the transmit driver 620 can be located on opposite sides of the first and second sides of the display area DAA.

[0075] The first pad region PDA1 may include a plurality of first pads PD1 connected to the circuit board 300 by a conductive adhesive member. The first pad region PDA1 may be located on the third side of the display area DAA. For example, the first pad region PDA1 may be located on one side of the display area DAA in the second direction DR2. The first pad region PDA1 may be located on the outside of the data driver 700 in the second direction DR2.

[0076] The second pad area PDA2 may include multiple second pads PD2, which are inspection pads used to test whether the display panel 100 is operating correctly. The multiple second pads PD2 may be connected to a fixture or probe pins during the inspection process, or they may be connected to a circuit board used for inspection. The circuit board used for inspection may be a rigid printed circuit board made of a rigid material or a flexible printed circuit board made of a flexible material.

[0077] The second pad region PDA2 can be located on the fourth side of the display region DAA. For example, the second pad region PDA2 can be located on the opposite side of the display region DAA in the second direction DR2. The second pad region PDA2 can be located on the outer side of the second distribution circuit 720 in the second direction DR2.

[0078] The first distribution circuit 710 distributes the data voltage applied via the first pad region PDA1 to multiple data lines DL. For example, the first distribution circuit 710 can distribute the data voltage applied via one first pad PD1 of the first pad region PDA1 to P data lines DL, thereby reducing the number of multiple first pads PD1, where P is a positive integer equal to or greater than two. The first distribution circuit 710 may be located on the third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 may be located on one side of the display area DAA in the second direction DR2.

[0079] The second distribution circuit 720 distributes the signal applied through the second pad region PDA2 to the scan driver 610, the transmit driver 620, and the data line DL. The second pad region PDA2 and the second distribution circuit 720 can be elements for testing the operation of each pixel PX in the display area DAA. The second distribution circuit 720 can be located on the fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be located on the opposite side of the display area DAA in the second direction DR2.

[0080] In the cathode connection region (CCA), the element layer (EML) is displayed (see...). Figure 7 The second electrode CAT (see) Figure 7 The cathode connection area (CCA) can be connected to the first drive voltage line (VSL) in the non-display area (NDA). The cathode connection area (CCA) can be located on at least one outer side of the display area (DAA). For example, the cathode connection area (CCA) can be located on the outer side of at least one of the left, right, top, and bottom sides of the display area (DAA). Optionally, the cathode connection area (CCA) can be as follows: Figure 4 The positioning shown is around the display area DAA to reduce the deviation of the first drive voltage VSS due to the voltage drop (IR drop) or voltage rise (IR rise) of the second electrode CAT in the display area DAA.

[0081] Figure 5 It is shown Figure 4 An enlarged plan view of an example of the display area. Figure 6 It is shown Figure 4 A magnified plan view of another example of the display area.

[0082] Reference Figure 5 and Figure 6 Each of the multiple pixels PX includes a first emission region EA1 as the emission region of a first sub-pixel SP1, a second emission region EA2 as the emission region of a second sub-pixel SP2, and a third emission region EA3 as the emission region of a third sub-pixel SP3. Furthermore, Figure 6 The pixel PX shown also includes a fourth emission region EA4, which is the emission region of the fourth sub-pixel SP4.

[0083] When viewed from above (e.g., in a plan view), the first emission region EA1, the second emission region EA2, and the third emission region EA3 can have the following characteristics: Figure 5 and Figure 6The rectangular or hexagonal shapes shown are not applicable. However, it should be understood that the embodiments of this disclosure are not limited thereto. When viewed from above (e.g., in a plan view), the first emission region EA1, the second emission region EA2, and the third emission region EA3 may have polygonal, circular, elliptical, or irregular shapes other than rectangular or hexagonal.

[0084] like Figure 5 As shown, in each of the plurality of pixels PX, the first emission region EA1 and the second emission region EA2 may be adjacent to each other in the first direction DR1. Additionally, the first emission region EA1 and the third emission region EA3 may be adjacent to each other in the first direction DR1. Furthermore, the second emission region EA2 and the third emission region EA3 may be adjacent to each other in the second direction DR2. The first emission region EA1, the second emission region EA2, and the third emission region EA3 may have different areas.

[0085] Optionally, such as Figure 6 As shown, when viewed from above (e.g., in a plan view), the emission regions EA1, EA2, EA3, and EA4 can have a hexagonal shape. In this case, the first emission region EA1 and the third emission region EA3 can be adjacent to each other in the first direction DR1, and the second emission region EA2 and the fourth emission region EA4 can be adjacent to each other in the second direction DR2. Additionally, the first emission region EA1 and the second emission region EA2 can be adjacent to each other in the first diagonal direction DD1, and the second emission region EA2 and the third emission region EA3 can be adjacent to each other in the second diagonal direction DD2. Furthermore, the first emission region EA1 and the fourth emission region EA4 can be adjacent to each other in the second diagonal direction DD2, and the third emission region EA3 and the fourth emission region EA4 can be adjacent to each other in the first diagonal direction DD1. The first diagonal direction DD1 refers to the direction between the first direction DR1 and the second direction DR2, and is a direction inclined at 45 degrees relative to the first direction DR1 and the second direction DR2. The second diagonal direction DD2 can be orthogonal to the first diagonal direction DD1.

[0086] The first sub-pixel SP1 can output the first light, the second sub-pixel SP2 can output the second light, and the third sub-pixel SP3 can output the third light. The first light can be blue wavelength light, the second light can be green wavelength light, and the third light can be red wavelength light. For example, blue wavelength can refer to the wavelength range where the main peak wavelength of the light is approximately 370nm to 460nm, green wavelength can refer to the wavelength range where the main peak wavelength of the light is approximately 480nm to 560nm, and red wavelength can refer to the wavelength range where the main peak wavelength of the light is approximately 600nm to 750nm.

[0087] Each of the multiple pixels PX can include, for example Figure 5 The three launch regions EA1, EA2, and EA3 shown may include, for example, Figure 6 The four emission regions EA1, EA2, EA3, and EA4 are shown. In this case, the fourth emission region EA4 can output the same second light as the second emission region EA2. However, it should be understood that the embodiments of this disclosure are not limited thereto.

[0088] The emission regions of multiple pixels PX can have a stripe pattern in which the emission regions are arranged in a first direction DR1, wherein the emission regions are arranged as follows: Figure 6 The PenTile shown has a diamond pattern arrangement. ® A matrix, or a hexagonal structure in which the emission regions are arranged in a hexagonal pattern.

[0089] Figure 7 It shows along Figure 5 A cross-sectional view of an example display panel taken by line I1-I1'.

[0090] Reference Figure 7 The display panel 100 includes a semiconductor backplane (SBP), a light-emitting element backplane (EBP), a display element layer (EML), a packaging layer (TFE), an optical layer (OPL), a cover layer (CVL), and a polarizer (POL).

[0091] The semiconductor backplane (SBP) includes a semiconductor substrate (SSUB) containing multiple pixel transistors (PTRs), multiple semiconductor insulating films covering the multiple pixel transistors (PTRs), and multiple contact terminals (CTEs) electrically connected to the pixel transistors (PTRs). The multiple pixel transistors (PTRs) can be as described above. Figure 3 The first transistor T1 to the sixth transistor T6 are described.

[0092] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a first type of impurity. Multiple well regions WA can be located on the upper surface of the semiconductor substrate SSUB. The well regions WA can be doped with a second type of impurity. The second type of impurity can be different from the first type of impurity. For example, when the first type of impurity is a p-type impurity, the second type of impurity can be an n-type impurity. Optionally, when the first type of impurity is an n-type impurity, the second type of impurity can be a p-type impurity.

[0093] Each of the well regions WA includes a source region SA associated with the source electrode of the pixel transistor PTR, a drain region DA associated with the drain electrode of the pixel transistor PTR, and a channel region CH between the source region SA and the drain region DA.

[0094] The bottom insulating film (BINS) can be located between the gate electrode GE and the well region WA. The side insulating film (SINS) can be located on the side surface of the gate electrode GE. The side insulating film (SINS) can also be located on the bottom insulating film (BINS).

[0095] Each of the source region SA and drain region DA may be doped with type I impurities. The gate electrode GE of the pixel transistor PTR may be stacked with the well region WA on the third direction DR3, which is the thickness direction of the semiconductor substrate SSUB. The channel region CH may be stacked with the gate electrode GE on the third direction DR3. The source region SA may be located on one side of the gate electrode GE, and the drain region DA may be located on the opposite side of the gate electrode GE.

[0096] Each of the multiple well regions WA may further include a first low-concentration impurity region LDD1 located between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 located between the channel region CH and the drain region DA. Due to the bottom insulating film BINS, the first low-concentration impurity region LDD1 can have an impurity concentration lower than that of the source region SA. Due to the bottom insulating film BINS, the second low-concentration impurity region LDD2 can have an impurity concentration lower than that of the drain region DA. The distance between the source region SA and the drain region DA can be increased by the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2. Therefore, the length of the channel region CH in each of the pixel transistors PTR can be increased.

[0097] The first semiconductor insulating film SINS1 can be located on the semiconductor substrate SSUB. The second semiconductor insulating film SINS2 can be located on the first semiconductor insulating film SINS1.

[0098] Multiple contact terminals (CTEs) may be located on the second semiconductor insulating film (SINS2). Each of the multiple contact terminals (CTEs) can be connected to one of the gate electrode (GE), source region (SA), and drain region (DA) of each pixel transistor (PTR) through a hole penetrating the first semiconductor insulating film (SINS1) and the second semiconductor insulating film (SINS2). The contact terminals (CTEs) may be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any of them.

[0099] The third semiconductor insulating film (SINS3) may be located on the side surface of each of the contact terminals (CTEs). The upper surface of each of the contact terminals (CTEs) may not be covered by the third semiconductor insulating film (SINS3) and may be exposed.

[0100] Each of the first semiconductor insulating film SINS1, the second semiconductor insulating film SINS2, and the third semiconductor insulating film SINS3 can be made of silicon carbonitride (SiCN) or silicon oxide (SiO2). x Inorganic membranes can be formed, but are not limited to this.

[0101] The semiconductor substrate SSUB can be replaced by a glass substrate or a polymer resin substrate such as polyimide. In this case, the thin-film transistor can be located on either the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that does not bend, while the polymer resin substrate can be a flexible substrate that can be bent or folded.

[0102] The backplane (EBP) of the light-emitting element includes multiple conductive layers ML1 to ML8, multiple vias VA1 to VA9, and multiple insulating films INS1 to INS9. Specifically, the backplane (EBP) of the light-emitting element includes a second insulating film INS2 to an eighth insulating film INS8 located between the first conductive layers ML1 to the eighth conductive layers ML8, a first insulating film INS1 located below the second insulating film INS2, and a ninth insulating film INS9 located on the eighth insulating film INS8.

[0103] The first insulating film INS1 to the eighth insulating film INS8 can insulate the first conductive layer ML1 to the eighth conductive layer ML8. The first conductive layer ML1 to the eighth conductive layer ML8 can be achieved by connecting multiple contact terminals CTE exposed from the semiconductor backplane SBP. Figure 3 The circuit of the first sub-pixel SP1 shown.

[0104] For example, transistors T1 to T6 are formed only in the semiconductor backplane SBP, and the connection between transistors T1 to T6 and the first capacitor CP1 and the second capacitor CP2 is accomplished through the first conductive layer ML1 to the eighth conductive layer ML8. Furthermore, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode AND of the light-emitting element LE is also accomplished through the first conductive layer ML1 to the eighth conductive layer ML8.

[0105] The first conductive layers ML1 to ML8 and the first vias VA1 to VA8 can be made of substantially the same material. The first conductive layers ML1 to ML8 and the first vias VA1 to VA8 can be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any of these. The first vias VA1 to VA8 can be made of substantially the same material. The first insulating film INS1 to INS8 can be made of silicon oxide (SiO2). xInorganic membranes may be formed, but the embodiments described in this specification are not limited thereto.

[0106] The ninth insulating film INS9 can be located above the eighth insulating film INS8 and the eighth conductive layer ML8. The ninth insulating film INS9 can be made of silicon oxide (SiO2). x Inorganic membranes are formed, but the embodiments disclosed herein are not limited thereto.

[0107] Each of the ninth vias VA9 can penetrate the ninth insulating film INS9 to connect to the exposed eighth conductive layer ML8. The ninth via VA9 can be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any of them.

[0108] The display element layer (EML) can be located on the backplane (EBP) of the light-emitting element. The display element layer (EML) may include a tenth insulating film (INS10) and an eleventh insulating film (INS11), a reflective electrode (RL), a first electrode (AND), a light-emitting stack (IL), a second electrode (CAT), a pixel defining layer (PDL), and multiple trenches (TRC).

[0109] The reflective electrode RL can be located on the ninth insulating film INS9. The reflective electrode RL can include one or more reflective electrodes RL1, RL2, RL3, and RL4. For example, the reflective electrode RL can include... Figure 7 The first reflective electrode RL1, the second reflective electrode RL2, the third reflective electrode RL3, and the fourth reflective electrode RL4 are shown in the figure.

[0110] The first reflective electrode RL1 can be located on the ninth insulating film INS9 and can be connected to the ninth via VA9. The second reflective electrode RL2 can be located on the first reflective electrode RL1. The third reflective electrode RL3 can be located on the second reflective electrode RL2. The fourth reflective electrode RL4 can be located on the third reflective electrode RL3.

[0111] Because the second reflective electrode RL2 is essentially the electrode that reflects light from the light-emitting element LE, the thickness of the second reflective electrode RL2 can be greater than the thickness of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4.

[0112] The first reflective electrode RL1 may be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or compound containing any of them. For example, the first reflective electrode RL1 may include titanium nitride (TiN), the second reflective electrode RL2 may include aluminum (Al), the third reflective electrode RL3 may include titanium nitride (TiN), and the fourth reflective electrode RL4 may include titanium (Ti).

[0113] The tenth insulating film INS10 may be located on the ninth insulating film INS9. The tenth insulating film INS10 may be located between adjacent reflective electrodes RL. The tenth insulating film INS10 may be a film used to provide a flat surface to the reflective electrode RL. The eleventh insulating film INS11 may be located on the tenth insulating film INS10 and the reflective electrode RL.

[0114] The tenth insulating film INS10 and the eleventh insulating film INS11 can be made of silicon dioxide (SiO2). x Inorganic membranes are formed, but the embodiments disclosed herein are not limited thereto.

[0115] The eleventh insulating film INS11 can be an optical auxiliary layer used to adjust the resonant distance of light emitted from the light-emitting stack IL in at least one of the first sub-pixels SP1, SP2, and SP3. The thickness of the eleventh insulating film INS11 can be different in the first sub-pixels SP1, SP2, and SP3. For example, in order to adjust the distance from the reflective electrode RL to the first electrode AND according to the dominant wavelength of light emitted from each of the first sub-pixels SP1, SP2, and SP3, the thickness of the eleventh insulating film INS11 can be determined in each of the first sub-pixels SP1, SP2, and SP3.

[0116] For example, such as Figure 7 As shown, the thickness of the eleventh insulating film INS11 in the first sub-pixel SP1 can be greater than the thickness of the eleventh insulating film INS11 in the second sub-pixel SP2, and the thickness of the eleventh insulating film INS11 in the second sub-pixel SP2 can be greater than the thickness of the eleventh insulating film INS11 in the third sub-pixel SP3. In this case, the distance between the first electrode AND and the reflective electrode RL in the first sub-pixel SP1 can be greater than the distance between the first electrode AND and the reflective electrode RL in the second sub-pixel SP2. Furthermore, the distance between the first electrode AND and the reflective electrode RL in the second sub-pixel SP2 can be greater than the distance between the first electrode AND and the reflective electrode RL in the third sub-pixel SP3.

[0117] The tenth via VA10 can penetrate the eleventh insulating film INS11 to connect to the exposed fourth reflective electrode RL4. The tenth via VA10 can be made of one or an alloy containing copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). The thickness of the tenth via VA10 in the first sub-pixel SP1 can be greater than the thickness of the tenth via VA10 in the second sub-pixel SP2, and the thickness of the tenth via VA10 in the second sub-pixel SP2 can be greater than the thickness of the tenth via VA10 in the third sub-pixel SP3.

[0118] The first electrode AND of each of the light-emitting elements LE can be located on the eleventh insulating film INS11 and can be connected to the tenth via VA10. The first electrode AND of each of the light-emitting elements LE can be connected to the drain region DA or source region SA of the pixel transistor PTR through the tenth via VA10, the reflective electrode RL, the first vias VA1 to the ninth vias VA9, the first conductive layers ML1 to the eighth conductive layers ML8, and the contact terminal CTE. The first electrode AND of each of the light-emitting elements LE can be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or compound containing any of them. For example, the first electrode AND of each of the light-emitting elements LE can be titanium nitride (TiN).

[0119] A pixel-defining layer (PDL) may be partially located on the first electrode AND of each of the light-emitting elements (LEs). The PDL may cover the edge of the first electrode AND of each of the light-emitting elements (LEs). The PDL may define a first emission region EA1, a second emission region EA2, and a third emission region EA3. In each of the first emission region EA1, the second emission region EA2, and the third emission region EA3, a light-emitting element (LE) including a first electrode AND, a light-emitting stack IL, and a second electrode CAT is provided.

[0120] The first emission region EA1 can be defined as the area in the first sub-pixel SP1 where the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked to emit light. The second emission region EA2 can be defined as the area in the second sub-pixel SP2 where the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked to emit light. The third emission region EA3 can be defined as the area in the third sub-pixel SP3 where the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked to emit light.

[0121] The pixel definition layer (PDL) may include a first pixel definition layer (PDL1), a second pixel definition layer (PDL2), and a third pixel definition layer (PDL3). The first pixel definition layer (PDL1) may be located on the edge of the first electrode AND of each of the light-emitting elements (LEs), the second pixel definition layer (PDL2) may be located on the first pixel definition layer (PDL1), and the third pixel definition layer (PDL3) may be located on the second pixel definition layer (PDL2). The first pixel definition layer (PDL1), the second pixel definition layer (PDL2), and the third pixel definition layer (PDL3) may be made of silicon oxide (SiO2). x An inorganic film based on silicon nitride (SiN) is formed. Optionally, the first pixel defining layer PDL1 and the third pixel defining layer PDL3 can be formed from silicon nitride (SiN). x The second pixel defining layer PDL2 can be formed from silicon oxide (SiO2) and an inorganic film is formed on it. x An inorganic film is formed. The thicknesses of the first pixel-defining layer PDL1, the second pixel-defining layer PDL2, and the third pixel-defining layer PDL3 can all be approximately 500 Å.

[0122] To prevent or reduce the likelihood of the first inorganic encapsulation film TFE1 cracking due to step coverage, the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may have a stepped cross-sectional structure. Here, step coverage refers to the ratio of the film applied to the inclined portion to the film applied to the flat portion. The lower the step coverage, the more likely the film is to crack at the inclined portion.

[0123] Each of the plurality of trench TRCs can penetrate the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3. At least a portion of the eleventh insulating film INS11 can be partially recessed at each of the plurality of trench TRCs.

[0124] At least one trench TRC can be formed between adjacent sub-pixels in sub-pixels SP1, SP2, and SP3. Although in Figure 7 In the example shown, two trenches TRC are formed between adjacent sub-pixels in sub-pixels SP1, SP2 and SP3, but the embodiments of this disclosure are not limited thereto.

[0125] The light-emitting stack IL can include multiple stacked layers IL1, IL2, and IL3. Although in Figure 7 The example shown has a three-tiered structure comprising a first stacked layer IL1, a second stacked layer IL2, and a third stacked layer IL3, but the embodiments disclosed herein are not limited thereto. For example, the light-emitting stack IL may have, as shown in the example below. Figure 8 The diagram shows a dual-tandem structure comprising two stacked layers.

[0126] In a three-tiered structure, the light-emitting stack IL can have a series structure comprising multiple stacked layers IL1, IL2, and IL3 that emit different lights. For example, the light-emitting stack IL may include a first stacked layer IL1 that outputs a first light, a second stacked layer IL2 that outputs a second light, and a third stacked layer IL3 that outputs a third light. The first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 can be stacked sequentially on top of each other.

[0127] The first stacked layer IL1 may have a structure in which a first hole transport layer, a first emission layer emitting first light, and a first electron transport layer are stacked sequentially on top of each other. The second stacked layer IL2 may have a structure in which a second hole transport layer, a second emission layer emitting second light, and a second electron transport layer are stacked sequentially on top of each other. The third stacked layer IL3 may have a structure in which a third hole transport layer, a third emission layer emitting third light, and a third electron transport layer are stacked sequentially on top of each other.

[0128] A first charge generation layer may be located between a first stacked layer IL1 and a second stacked layer IL2 to supply holes to the second stacked layer IL2 and electrons to the first stacked layer IL1. The first charge generation layer may include an n-type charge generation layer that supplies electrons to the first stacked layer IL1 and a p-type charge generation layer that supplies holes to the second stacked layer IL2. The n-type charge generation layer may include a dopant of a metallic material.

[0129] The second charge generation layer may be located between the second stacked layer IL2 and the third stacked layer IL3 to supply holes to the third stacked layer IL3 and electrons to the second stacked layer IL2. The second charge generation layer may include an n-type charge generation layer that supplies electrons to the second stacked layer IL2 and a p-type charge generation layer that supplies holes to the third stacked layer IL3.

[0130] A first stacked layer IL1 may be located on the first electrode AND and the pixel defining layer PDL. In each of the trench TRCs, a residual film RIL located at the bottom of the trench TRC may be made of the same material as the first stacked layer IL1. Due to the trench TRC, the first stacked layer IL1 may be disconnected between adjacent sub-pixels SP1, SP2, and SP3. A second stacked layer IL2 may be located on the first stacked layer IL1. Due to the trench TRC, the second stacked layer IL2 may be disconnected between adjacent sub-pixels SP1, SP2, and SP3. In the trench TRC, a cavity ESS or empty space may be located between the residual film RIL and the second stacked layer IL2. A third stacked layer IL3 may be located on the second stacked layer IL2. The third stacked layer IL3 may not be disconnected by the trench TRC and may be arranged to cover the second stacked layer IL2 in each of the trench TRCs.

[0131] In a three-series structure, each of the multiple trench TRCs may feature a first hole transport layer to a third hole transport layer, a first charge generation layer, and a second charge generation layer of the display element layers EML between adjacent sub-pixels SP1, SP2, and SP3. Additionally, in a two-series structure, each of the multiple trench TRCs may feature a structure that disconnects the charge generation layer and the lower stacked layer located between the lower and upper stacked layers.

[0132] To stably disconnect the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, the height of each of the plurality of trench TRCs can be greater than the height of the pixel defining layer PDL. The height of each of the plurality of trench TRCs refers to the length measured on the third direction DR3. The height of the pixel defining layer PDL refers to the length of the pixel defining layer PDL on the third direction DR3. To disconnect the hole transport layer and charge generation layer of the light-emitting stack IL of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, other features besides trench TRCs can exist. For example, instead of trench TRCs, inverted conical partition walls can be located on the pixel defining layer PDL.

[0133] In addition, although in Figure 7 In the example shown, the light-emitting stack IL is located in all of the first emission region EA1, the second emission region EA2, and the third emission region EA3; however, the embodiments of this disclosure are not limited thereto. For example, instead of the light-emitting stack IL, the first emission layer may be located in the first emission region EA1, but not in the second emission region EA2 or the third emission region EA3. Additionally, the second emission layer may be located in the second emission region EA2, but not in the first emission region EA1 or the third emission region EA3. Furthermore, the third emission layer may be located in the third emission region EA3, but not in the first emission region EA1 or the second emission region EA2. In this case, the first color filter CF1, the second color filter CF2, and the third color filter CF3 of the optical layer OPL can be removed.

[0134] The second electrode CAT can be located on the light-emitting stack IL. The second electrode CAT can also be located on the third stacked layer IL3 in each of the multiple trench TRCs. The second electrode CAT can be formed of a transparent conductive material (TCO) capable of transmitting light, such as ITO and IZO, or a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), or alloys of magnesium (Mg) and silver (Ag). When the second electrode CAT is formed of a semi-transmissive conductive material, light extraction efficiency can be improved by using microcavities in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0135] The encapsulation layer TFE can be located on the display element layer EML. The encapsulation layer TFE may include one or more inorganic films TFE1 and TFE3 to prevent or reduce the penetration of contaminants such as oxygen or moisture into the display element layer EML. For example, the first inorganic encapsulation film TFE1 may be located on the second electrode CAT, and the second inorganic encapsulation film TFE3 may be located on the first inorganic encapsulation film TFE1. The first inorganic encapsulation film TFE1 and the second inorganic encapsulation film TFE3 may be made of silicon nitride (SiN). x ), silicon oxynitride (SiON), silicon oxide (SiO) x Titanium oxide (TiO) x ) and aluminum oxide (AlO x A multilayer structure consisting of one or more inorganic layers stacked alternately on top of each other.

[0136] Additionally, the encapsulation layer TFE may include at least one organic film TFE2 to protect the display element layer EML from particles such as dust. For example, the organic encapsulation film TFE2 may be located between a first inorganic encapsulation film TFE1 and a second inorganic encapsulation film TFE3. The organic encapsulation film TFE2 may be a monomer. Optionally, the organic encapsulation film TFE2 may be an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0137] The adhesive layer (ADL) can adhere the encapsulation layer (TFE) to the optical layer (OPL). The adhesive layer (ADL) can be a double-sided adhesive component. Alternatively, the adhesive layer (ADL) can be a transparent adhesive component, such as a transparent adhesive or a transparent adhesive resin.

[0138] The optical layer OPL includes multiple color filters CF1, CF2, and CF3, multiple lenses LNS, and a filler layer FIL. The multiple color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be located on the adhesive layer ADL.

[0139] The first color filter CF1 can be aligned with the first emission region EA1 of the first sub-pixel SP1. The first color filter CF1 can transmit light of the first color (i.e., light in the blue band). The blue band can be approximately 370nm to 460nm. Therefore, the first color filter CF1 can transmit light of the first color emitted from the first emission region EA1.

[0140] The second color filter CF2 can be aligned with the second emission region EA2 of the second sub-pixel SP2. The second color filter CF2 can transmit light of the second color (i.e., light in the green band). The green band can be approximately 480nm to 560nm. Therefore, the second color filter CF2 can transmit light of the second color emitted from the second emission region EA2.

[0141] The third color filter CF3 can be aligned with the third emission region EA3 of the third sub-pixel SP3. The third color filter CF3 can transmit light of the third color (i.e., light in the red band). The red band can be approximately 600nm to 750nm. Therefore, the third color filter CF3 can transmit light of the third color emitted from the third emission region EA3.

[0142] Lenses LNS can be located on the first color filter CF1, the second color filter CF2, and the third color filter CF3, respectively. Each of the lenses LNS can be a structure for increasing the ratio of light directed to the front side of the display device 10. Each of the lenses LNS can have an upwardly projecting cross-sectional shape.

[0143] The filler layer (FIL) can be located on multiple lens lenses (LNS). The filler layer (FIL) can have a predetermined refractive index, such that light travels along the third direction (DR3) at the interface between the multiple lens lenses (LNS) and the filler layer (FIL). Alternatively, the filler layer (FIL) can be a planarization layer. The filler layer (FIL) can be an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0144] The cover layer CVL can be located on the filler layer FIL. The cover layer CVL can be a glass substrate or a polymer resin. If the cover layer CVL is a glass substrate, it can be attached to the filler layer FIL. In this case, the filler layer FIL can be used to bond the cover layer CVL. When the cover layer CVL is a glass substrate, it can be used as an encapsulation substrate. When the cover layer CVL is a polymer resin, it can be applied directly to the filler layer FIL.

[0145] The polarizer POL can be located on one surface of the CVL cover layer. The polarizer POL can be a structure used to reduce or prevent visibility degradation caused by reflection of external light. The polarizer POL can include a linear polarizer and a phase retardation film. For example, the phase retardation film can be a λ / 4 plate (quarter-wave plate), but embodiments of this disclosure are not limited thereto. However, the polarizer POL can be omitted when visibility degradation caused by reflection of external light is sufficiently overcome by the first color filter CF1, the second color filter CF2, and the third color filter CF3.

[0146] Figure 8 It shows along Figure 5Another example of a cross-sectional view of the display panel, taken by line I1-I1'.

[0147] Figure 8 Implementation examples and Figure 7 The embodiment differs in that the first electrode AND of each of the light-emitting elements LE is electrically connected to the side surface of the connection electrode ANC, which is connected to the eighth conductive layer ML8. Additionally, Figure 8 Implementation examples and Figure 7 The difference in this embodiment is that the trench TRC is eliminated, and instead, the third pixel defining layer PDL3 and the fourth pixel defining layer PDL4 have a cross-sectional structure in the shape of an eaves or a mushroom. Some redundant descriptions may be omitted.

[0148] Reference Figure 8 Multiple connecting electrodes ANC can be located on the first portion AA1 of the ninth insulating film INS9. The multiple connecting electrodes ANC can be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or alloys or compounds containing any of them, or transparent conductive oxides. For example, the connecting electrodes ANC may include titanium (Ti), titanium nitride (TiN), indium tin oxide (ITO), or indium zinc oxide (IZO), but are not limited to these.

[0149] Multiple reflective electrodes RL can be located on multiple connecting electrodes ANC. The multiple reflective electrodes RL can be made of one or an alloy of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). For example, each of the multiple reflective electrodes RL may include aluminum (Al) with high reflectivity.

[0150] Multiple optical auxiliary layers (OAL) can be located on multiple reflective electrodes (RL). The optical auxiliary layers (OAL) can be made of silicon oxide (SiO2). x Inorganic membranes such as those formed by the formation of inorganic membranes, but the embodiments disclosed herein are not limited thereto.

[0151] The stepped layer STPL can be located on the reflective electrode RL in each of the first emission region EA1 and the third emission region EA3, and the optical auxiliary layer OAL can be located on the stepped layer STPL. In the second emission region EA2, only the optical auxiliary layer OAL can be located on the reflective electrode RL. The thickness of the optical auxiliary layer OAL can be substantially constant in the first emission region EA1, the second emission region EA2, and the third emission region EA3.

[0152] Due to the stepped layer STPL, the distance between the reflective electrode RL and the first electrode AND in the third direction DR3 in the first emission region EA1 and the third emission region EA3 can be greater than the distance between the reflective electrode RL and the first electrode AND in the third direction DR3 in the second emission region EA2. The thickness of the stepped layer STPL and the thickness of the optical auxiliary layer OAL can be determined based on the wavelength and resonant distance of the light emitted from the first stacked layer IL1 of the light-emitting stack IL and the wavelength and resonant distance of the light emitted from the second stacked layer IL2.

[0153] Each of the light-emitting elements LE may include a first electrode AND, a light-emitting stack IL, and a second electrode CAT.

[0154] The first electrode AND of each of the light-emitting elements LE can be located on the corresponding optical auxiliary layer OAL. Because the connecting electrode ANC, the reflective electrode RL, and the optical auxiliary layer OAL are stacked sequentially on top of each other, the first electrode AND of each of the light-emitting elements LE can be located on the upper and side surfaces of the optical auxiliary layer OAL, the side surface of the reflective electrode RL, and the side surface of the connecting electrode ANC. In this way, the first electrode AND of each of the light-emitting elements LE can contact and be electrically connected to the side surfaces of the reflective electrode RL and the connecting electrode ANC. Therefore, compared to a structure where the first electrode AND of each of the light-emitting elements LE is connected to the reflective electrode RL exposed through a hole penetrating the optical auxiliary layer OAL, masking processes can be reduced. Therefore, there are advantages in terms of reduced manufacturing costs and increased manufacturing efficiency.

[0155] The first electrode AND of each of the light-emitting elements LE can be connected to the drain region DA or source region SA of the pixel transistor PTR through the connection electrode ANC, the first via VA1 to the ninth via VA9, the first conductive layer ML1 to the eighth conductive layer ML8 and the contact terminal CTE.

[0156] The ninth insulating film INS9 may include a first portion AA1 superimposed on the third-direction DR3 with the connecting electrode ANC, and a second portion AA2 superimposed on the third-direction DR3 without being superimposed on the connecting electrode ANC. The thickness of the first portion AA1 and the thickness of the second portion AA2 of the ninth insulating film INS9 may be substantially equal to each other.

[0157] Optionally, the thickness of the first portion AA1 of the ninth insulating film INS9 can be greater than the thickness of the second portion AA2. In this case, the side surface of the first portion AA1 of the ninth insulating film INS9 can be exposed, and the first electrode AND of each of the light-emitting elements LE can be located on the exposed side surface of the first portion AA1 of the ninth insulating film INS9.

[0158] The first electrode AND of each of the light-emitting elements LE can be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or compound containing any of them, or a transparent conductive oxide. For example, the first electrode AND of each of the light-emitting elements LE may include, but is not limited to, titanium nitride (TiN), indium tin oxide (ITO), or indium zinc oxide (IZO).

[0159] The pixel defining layer (PDL) may be partially located on the first electrode AND of each of the light-emitting elements (LEs). The pixel defining layer (PDL) may cover the edge of the first electrode AND of each of the light-emitting elements (LEs). The pixel defining layer (PDL) may define a first emission region EA1, a second emission region EA2, and a third emission region EA3.

[0160] The pixel limiting layer (PDL) may include a first pixel limiting layer (PDL1), a second pixel limiting layer (PDL2), a third pixel limiting layer (PDL3), and a fourth pixel limiting layer (PDL4).

[0161] The first pixel defining layer PDL1 may be located on the first electrode AND of each of the light-emitting elements LE. For example, the first pixel defining layer PDL1 may cover a portion of the upper surface of the first electrode AND located on the optical auxiliary layer OAL. Additionally, the first pixel defining layer PDL1 may cover the first electrode AND located on the side surface of the connecting electrode ANC, the side surface of the reflective electrode RL, and the side surface of the optical auxiliary layer OAL. The first pixel defining layer PDL1 may be located on the upper surface of the second portion AA2 of the ninth insulating film INS9.

[0162] The planarization film PNS is a film used to provide a flat surface on the connecting electrode ANC, the reflective electrode RL, and the optical auxiliary layer OAL.

[0163] The planarization film PNS can be located on the first pixel defining layer PDL1, which covers the first electrode AND located on the side surface of the connecting electrode ANC, the side surface of the reflective electrode RL, and the side surface of the optical auxiliary layer OAL. The planarization film PNS can be located on the first pixel defining layer PDL1 positioned on the second portion AA2 of the ninth insulating film INS9.

[0164] The planarization film PNS can be located between adjacent connecting electrodes ANC on the first direction DR1 or the second direction DR2. The planarization film PNS can be located between adjacent reflecting electrodes RL on the first direction DR1 or the second direction DR2. The planarization film PNS can be located between adjacent optical auxiliary layers OAL on the first direction DR1 or the second direction DR2.

[0165] Although there is no step layer STPL in the second emission region EA2, the step layer STPL is located in each of the first emission region EA1 and the third emission region EA3. Therefore, the height of the connecting electrode ANC, the reflective electrode RL, and the optical auxiliary layer OAL in the second emission region EA2 can be smaller than the height of the connecting electrode ANC, the reflective electrode RL, the step layer STPL, and the optical auxiliary layer OAL in each of the first emission region EA1 and the third emission region EA3. Therefore, the planarization film PNS can cover the upper surface of the first pixel defining layer PDL1 located on the upper surface of the first electrode AND positioned in the second emission region EA2.

[0166] Conversely, the upper surface of the planarization film PNS can be flatly connected to the upper surface of the first electrode AND located in the first emission region EA1 and the third emission region EA3. That is, the planarization film PNS may not cover the upper surface of the first pixel defining layer PDL1 located on the upper surface of the first electrode AND located in each of the first emission region EA1 and the third emission region EA3.

[0167] The second pixel-defining layer PDL2 can be located on the first pixel-defining layer PDL1 and the planarization film PNS, the third pixel-defining layer PDL3 can be located on the second pixel-defining layer PDL2, and the fourth pixel-defining layer PDL4 can be located on the third pixel-defining layer PDL3. The first pixel-defining layer PDL1 and the third pixel-defining layer PDL3 are made of materials such as silicon nitride (SiN). x The inorganic film is formed from an inorganic film based on silicon dioxide (SiO2), while the second pixel defining layer PDL2, the fourth pixel defining layer PDL4, and the planarization film PNS can be formed from silicon dioxide (SiO2). x Inorganic film formation. Because the first pixel defining layer PDL1 is made of a different material than the planarization film PNS, the first pixel defining layer PDL1 can be used as a stop in the chemical polishing and mechanical polishing processes of the planarization film PNS.

[0168] When the planarization film PNS and the second pixel defining layer PDL2 are made of silicon oxide (SiO) x When the inorganic film is formed, the planarization film PNS and the second pixel defining layer PDL2 can be formed as a single film.

[0169] Because the length of the third pixel-defining layer PDL3 in one direction is less than the length of the fourth pixel-defining layer PDL4 in that same direction, the lower surface of the fourth pixel-defining layer PDL4 can be exposed by the third pixel-defining layer PDL3 without being covered by it. In other words, the third pixel-defining layer PDL3 and the fourth pixel-defining layer PDL4 can have a cross-sectional structure in the shape of an eave or a mushroom.

[0170] The light-emitting stack IL can be located on the first electrode AND and the pixel defining layer PDL. The light-emitting stack IL can include a first stacked layer IL1 and a second stacked layer IL2 that emit different lights. When the light-emitting stack IL has a dual-tandem structure, one of the first stacked layer IL1 and the second stacked layer IL2 can emit light in a wavelength range including one of a first light, a second light, and a third light, while the other can emit light in a wavelength range including the other two light sources. For example, the first stacked layer IL1 can emit light including the wavelength range of the first light and the wavelength range of the third light, while the second stacked layer IL2 can emit light including the wavelength range of the second light. The first light can be blue light, the second light can be green light, and the third light can be red light.

[0171] A charge generation layer may be located between a first stacked layer IL1 and a second stacked layer IL2 to supply holes to the second stacked layer IL2 and electrons to the first stacked layer IL1. The charge generation layer may include an n-type charge generation layer that supplies electrons to the first stacked layer IL1 and a p-type charge generation layer that supplies holes to the second stacked layer IL2. The n-type charge generation layer may include a dopant of a metallic material.

[0172] Because the first stacked layer IL1 is not formed on the lower surface of the fourth pixel-defining layer PDL4 that is exposed but not covered by the third pixel-defining layer PDL3, the first stacked layer IL1 can be disrupted by the eaves- or mushroom-shaped cross-sectional structure of the third pixel-defining layer PDL3 and the fourth pixel-defining layer PDL4. When this occurs, the first hole transport layer of the first stacked layer IL1 and the charge generation layer located between the first stacked layer IL1 and the second stacked layer IL2 can also be disconnected. Additionally, although in Figure 8 In the example shown, the second stacked layer IL2 is connected without being disconnected, but the second hole transport layer of the second stacked layer IL2 can be disconnected, while the second electron transport layer of the second stacked layer IL2 can be connected without being disconnected. Therefore, leakage current can be prevented or reduced from flowing through the first hole transport layer of the first stacked layer IL1, the second hole transport layer of the second stacked layer IL2, and the charge generation layer between adjacent emitting regions EA1, EA2, and EA3. Thus, the light-emitting stacks IL in adjacent emitting regions EA1, EA2, and EA3 can be prevented from being affected by current and from emitting light other than the initially intended light.

[0173] Despite Figure 8 The example shown has a dual-tandem structure comprising two stacked layers IL1 and IL2, but the embodiments of this disclosure are not limited thereto. For example, the light-emitting stack IL may have, for instance, a dual-tandem structure comprising two stacked layers IL1 and IL2. Figure 7The diagram shows a three-tiered structure comprising three stacked layers. In this case, the height of the third pixel-defining layer PDL3 can be adjusted to disconnect the charge-generating layers between the first stacked layer IL1 and the second stacked layer IL2, and between the second stacked layer IL2 and the third stacked layer IL3. Optionally, a trench TRC can be added penetrating the first pixel-defining layer PDL1, the planarization film PNS, the second pixel-defining layer PDL2, and the third pixel-defining layer PDL3, as shown. Figure 7 As shown in the diagram. In this case, the trench TRC can at least partially penetrate the ninth insulating film INS9, but the embodiments of this disclosure are not limited thereto.

[0174] Figure 9 This is a perspective view showing an example of an electronic device. Figure 10 It is used to show Figure 9 An exploded perspective view of an electronic device.

[0175] Reference Figure 9 and Figure 10 According to some embodiments, the electronic device 1000 includes a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head strap 1300, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600.

[0176] The first display device 10_1 provides an image to the user's left eye, and the second display device 10_2 provides an image to the user's right eye. The first display device 10_1 and the second display device 10_2 are as described above. Figures 1 to 8 The display device 10 described is basically the same, and therefore, some redundant descriptions can be omitted.

[0177] The first optical component 1510 may be located between the first display device 10_1 and the first eyepiece 1210. The second optical component 1520 may be located between the second display device 10_2 and the second eyepiece 1220. Each of the first optical component 1510 and the second optical component 1520 may include at least one convex lens.

[0178] The intermediate frame 1400 can be located between the first display device 10_1 and the control circuit board 1600, and can also be located between the second display device 10_2 and the control circuit board 1600. The intermediate frame 1400 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0179] The control circuit board 1600 can be located between the intermediate frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 10_1 and the second display device 10_2 via connectors. The control circuit board 1600 can convert externally input image sources into digital video data DATA, and can transmit the digital video data DATA to the first display device 10_1 and the second display device 10_2 via connectors.

[0180] The control circuit board 1600 can transmit digital video data DATA associated with a left-eye image optimized for the user's left eye to a first display device 10_1, and can transmit digital video data DATA associated with a right-eye image optimized for the user's right eye to a second display device 10_2. Optionally, the control circuit board 1600 can transmit the same digital video data DATA to both the first display device 10_1 and the second display device 10_2.

[0181] The display device housing 1100 houses a first display device 10_1, a second display device 10_2, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600. A housing cover 1200 is arranged to cover the open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 for placing the user's left eye and a second eyepiece 1220 for placing the user's right eye. Although in Figure 9 and Figure 10 In the example shown, the first eyepiece 1210 and the second eyepiece 1220 are arranged separately, but the embodiments of this disclosure are not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 can be combined into a single element.

[0182] The first eyepiece 1210 can be aligned with the first display device 10_1 and the first optical component 1510, and the second eyepiece 1220 can be aligned with the second display device 10_2 and the second optical component 1520. Therefore, the user can see a virtual image of the image on the first display device 10_1 magnified by the first optical component 1510 through the first eyepiece 1210, and a virtual image of the image on the second display device 10_2 magnified by the second optical component 1520 through the second eyepiece 1220.

[0183] A head strap 1300 secures the display device housing 1100 to the user's head, such that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are aligned with the user's left and right eyes, respectively. By achieving a lightweight and small display device housing 1100, the electronic device 1000 can include, for example... Figure 11 The eyeglasses frame shown replaces the headband 1300.

[0184] Figure 11 This is a perspective view showing another example of an electronic device.

[0185] Reference Figure 11 According to some embodiments, the electronic device 1000_1 may be an eyeglass-type display device having a lightweight and small display device housing 1200_1. According to some embodiments, the electronic device 1000_1 may include a display device 10_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical component 1060, a light path conversion component 1070, and a display device housing 1200_1.

[0186] The display device housing 1200_1 can accommodate the display device 10_3, the optical component 1060, and the light path conversion component 1070. The image displayed on the display device 10_3 can be magnified by the optical component 1060, and the light path of the image can be converted by the light path conversion component 1070 to be provided to the user's right eye through the right eye lens 1020. As a result, the user can see an augmented reality image that combines the virtual image displayed on the display device 10_3 with the real-world image viewed through the right eye lens 1020.

[0187] Despite Figure 11 In the example shown, the display device housing 1200_1 is located at the right end of the support frame 1030, but the embodiments of this disclosure are not limited thereto. For example, the display device housing 1200_1 may be located at the left end of the support frame 1030. In this case, the image displayed on the display device 10_3 can be provided to the user's left eye. Alternatively, the display device housing 1200_1 may be located at both the left and right ends of the support frame 1030. In this case, the user can view the image displayed on the display device 10_3 through both the left and right eyes.

[0188] Figure 12 This is a view illustrating a deposition apparatus according to some embodiments of the present disclosure.

[0189] Reference Figure 12 The deposition equipment 3000 can be used to manufacture the display panel 100 (see Figure 1 In the process of forming a light-emitting material layer on the backplane substrate 3002, a light-emitting material layer is formed. For example, such as... Figure 7As shown, the semiconductor backplane SBP and the light-emitting element backplane EBP can be located on the backplane substrate 3002, and the reflective electrode RL and the tenth insulating film INS10 can be located on the light-emitting element backplane EBP. The eleventh insulating film INS11 can be located on the tenth insulating film INS10. The electrode pattern (e.g., the anode electrode AND) can be located on the eleventh insulating film INS11, and the anode electrode AND can be electrically connected to the reflective electrode RL through the tenth via VA10. The deposition apparatus 3000 can be used to form the light-emitting stack IL on the electrode pattern.

[0190] The deposition apparatus 3000 may include a deposition source 3200 for providing vapor-phase deposition material on a backplane substrate 3002, a deposition mask 2000 located above the deposition source 3200, and a substrate chuck 3300 located above the deposition mask 2000 to support the backplane substrate 3002 with the backplane substrate 3002 facing the deposition mask 2000. Specifically, the substrate chuck 3300 can support the backplane substrate 3002 with its front surface facing down, and the backplane substrate 3002 can be placed above the deposition mask 2000 to perform the deposition process. The substrate chuck 3300 may be supported by a support member 3310, and a permanent magnet may be located inside the support member 3310.

[0191] The deposition source 3200, deposition mask 2000, and substrate chuck 3300 may be located within the processing chamber 3100. The processing chamber 3100 may have an internal space, and a deposition process for forming a layer of deposited material on a backing substrate 3002 can be performed within the internal space of the processing chamber 3100. According to some embodiments, the processing chamber 3100 may be connected to a vacuum pump. A vacuum atmosphere can be generated within the internal space of the processing chamber 3100 by the vacuum pump. Openings can be formed on the sidewalls of the processing chamber 3100 for the backing substrate 3002 and deposition mask 2000 to enter and exit, and these openings can be opened and closed by gate valves.

[0192] The deposition material can be stored in the deposition source 3200. The deposition source 3200 can evaporate the deposition material (such as organic, inorganic, and conductive materials) onto the backplane substrate 3002. The evaporated deposition material can be deposited on the backplane substrate 3002 through the deposition mask 2000. For example, the deposition source 3200 can evaporate organic materials used to form a light-emitting material layer on the backplane substrate 3002, and the evaporated organic materials can be deposited on an electrode pattern on the backplane substrate 3002 through the deposition mask 2000.

[0193] Figure 13 It is shown Figure 12 The bottom view of the back panel base shown.

[0194] Reference Figure 13The back panel substrate 3002 may include multiple display unit areas 3010 and scribed areas 3020 between the display unit areas 3010. For example... Figure 13 As shown, the display unit region 3010 can be arranged in a matrix along the first direction DR1 and the second direction DR2. After the manufacturing process of the display has been completed, the display unit region 3010 can be cut into multiple individual display panels 100 (see Figure 1). Figure 1 For example, the display unit area 3010 can be arranged in a matrix along a first horizontal direction (also called the first direction) DR1 and a second horizontal direction (also called the second direction) DR2 perpendicular to the first horizontal direction DR1.

[0195] Each of the display unit regions 3010 may include a semiconductor backplane SBP, a light-emitting element backplane EBP located on the semiconductor backplane SBP, a reflective electrode RL located on the light-emitting element backplane EBP, and an eleventh insulating film INS11 located on the reflective electrode RL. Additionally, each of the display unit regions 3010 may include multiple electrode patterns (e.g., multiple anode electrodes AND) arranged on the eleventh insulating film INS11, and the anode electrodes AND can be connected to the reflective electrode RL through multiple tenth vias VA10. The electrode patterns of the display unit regions 3010 may be arranged on the front surface of the backplane substrate 3002. The substrate chuck 3300 may clamp the rear surface of the backplane substrate 3002 such that the electrode patterns of the display unit regions 3010 face downwards, i.e., towards the deposition source 3200.

[0196] Figure 14 This is a plan view illustrating a deposition mask according to some embodiments of the present disclosure. Figure 15 It is shown Figure 14 An enlarged plan view of the mask unit region shown. Figure 16 It shows along Figure 15 A cross-sectional view of an example of a deposition mask cut by line I2-I2'. Figure 17 yes Figure 16 A magnified view of part A.

[0197] Reference Figures 14 to 17 According to some embodiments of the present disclosure, a deposition mask 2000 may include a mask frame 2100, a film 2200, a first back inorganic layer 2400, a second back inorganic layer 2500, and an electrode pattern portion 2600.

[0198] The mask frame 2100 may have cell openings 2110. Multiple cell openings 2110 may be provided, and these openings may be spaced apart from each other along a first direction DR1 and a second direction DR2. In other words, the multiple cell openings 2110 may be arranged in a matrix along the first direction DR1 and the second direction DR2. The multiple cell openings 2110 may be superimposed on the mask cell region 2310, which will be described later. The mask frame 2100 may be a single-crystal silicon substrate. The cell openings 2110 may be formed using a wet etching process with tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH). The crystal orientation of the single-crystal silicon substrate used as the mask frame 2100 may be the third direction DR3 of the deposition mask 2000.

[0199] The membrane 2200 may be located on the upper part of the mask frame 2100. The membrane 2200 may include a mask unit region 2310 corresponding to the display unit region 3010 of the back plate substrate 3002, and a grid region 2320 excluding the mask unit region 2310.

[0200] like Figure 14 As shown, the mask unit regions 2310 can be arranged in a matrix along a first direction DR1 and a second direction DR2. For example, the mask unit regions 2310 can be arranged in a matrix along a first horizontal direction DR1 and a second horizontal direction DR2 perpendicular to the first horizontal direction DR1, and can be arranged to correspond to the display unit regions 3010 respectively. In addition, the mask unit regions 2310 can be superimposed on the unit openings 2110.

[0201] The mesh region 2320 can be a region in the membrane 2200 that does not include the mask unit region 2310. The mesh region 2320 can be located between the mask unit regions 2310.

[0202] In addition, membrane 2200 may include an inorganic layer 2210 and a nitride layer 2220.

[0203] The inorganic layer 2210 may be located on the upper part of the mask frame 2100. In other words, the inorganic layer 2210 may be located on the upper part of the mask frame 2100 such that the lower surface of the inorganic layer 2210 contacts the upper surface of the mask frame 2100. The inorganic layer 2210 may be formed of a material that has etch selectivity relative to the nitride layer 2220 and the mask frame 2100. For example, the inorganic layer 2210 may include silicon oxide (SiO2). x ).

[0204] The nitride layer 2220 may be located on top of the inorganic layer 2210. In other words, the nitride layer 2220 may be located on top of the inorganic layer 2210, such that its lower surface is in contact with the upper surface of the inorganic layer 2210. The nitride layer 2220 may include silicon nitride (SiN). x ).

[0205] Each of the mask unit regions 2310 of the film 2200 may include a plurality of pixel openings 2312 that expose the anode electrode AND during the deposition process. The mask unit regions 2310 may be exposed toward the deposition source 3200 through the unit openings 2110, and the pixel openings 2312 may penetrate the film 2200 to connect to the unit openings 2110. In other words, the pixel openings 2312 may be formed to penetrate the inorganic layer 2210 and the nitride layer 2220 to connect to the unit openings 2110.

[0206] The first post-inorganic layer 2400 may be located on the lower part of the mask frame 2100. In other words, the first post-inorganic layer 2400 may be located on the lower part of the mask frame 2100 such that its upper surface contacts the lower surface of the mask frame 2100. A first post-opening 2410 communicating with the cell opening 2110 may be formed in the first post-inorganic layer 2400. The first post-inorganic layer 2400 may include the same material as the inorganic layer 2210 of the film 2200. For example, the first post-inorganic layer 2400 may include silicon oxide (SiO₂). x ).

[0207] The second post-inorganic layer 2500 can be located below the first post-inorganic layer 2400. In other words, the second post-inorganic layer 2500 can be located below the first post-inorganic layer 2400, such that its upper surface contacts the lower surface of the first post-inorganic layer 2400. In the second post-inorganic layer 2500, a second post-opening 2510 communicating with the cell opening 2110 and the first post-opening 2410 can be formed. The second post-inorganic layer 2500 can include the same material as the nitride layer 2220 of the film 2200. For example, the second post-inorganic layer 2500 can include silicon nitride (SiN). x ).

[0208] Electrode pattern portions 2600 may be located on mask frame 2100. Electrode pattern portions 2600 may be arranged to surround a plurality of cell openings 2110 while being spaced apart from the cell openings 2110. For example, electrode pattern portions 2600 may extend on mask frame 2100 in a first direction DR1 and a second direction DR2 to surround cell openings 2110. Electrode pattern portions 2600 may extend between cell openings 2110 in the first direction DR1 and the second direction DR2 to surround cell openings 2110. Because electrode pattern portions 2600 are arranged to surround cell openings 2110, electrode pattern portions 2600 may be superimposed on grid regions 2320 of film 2200.

[0209] The electrode pattern portion 2600 may include a first electrode pattern 2610 and a second electrode pattern 2620.

[0210] The first electrode pattern 2610 may be located on the mask frame 2100, spaced apart from the cell openings 2110, thereby surrounding a plurality of cell openings 2110. For example, the first electrode pattern 2610 may extend on the mask frame 2100 in a first direction DR1 and a second direction DR2 to surround the cell openings 2110. The first electrode pattern 2610 may be arranged to extend from the upper surface of the mask frame 2100 into the interior of the mask frame 2100. For example, the first electrode pattern 2610 may be introduced into the mask frame 2100 in the thickness direction from the upper surface of the mask frame 2100 by a doping process. Because the first electrode pattern 2610 extends from the upper surface of the mask frame 2100 into the interior of the mask frame 2100, the first electrode pattern 2610 may be located on the lower portion of the inorganic layer 2210 of the film 2200.

[0211] The first electrode pattern 2610 can be configured as a pattern formed of a conductive metal material and can receive current from a separate power supply unit. For example, the first electrode pattern 2610 can receive positive current from a separate power supply unit.

[0212] The second electrode pattern 2620 can be located on the mask frame 2100, spaced apart from the cell openings 2110 and the first electrode pattern 2610, thereby surrounding a plurality of cell openings 2110. For example, the second electrode pattern 2620 can extend in a first direction DR1 and a second direction DR2 to surround the cell openings 2110, while being spaced apart from the first electrode pattern 2610 on the mask frame 2100. The second electrode pattern 2620 can be formed to be introduced into the interior of the mask frame 2100 from the upper surface of the mask frame 2100. For example, the second electrode pattern 2620 can be introduced into the mask frame 2100 in the thickness direction from the upper surface of the mask frame 2100 by a doping process. Because the second electrode pattern 2620 is introduced into the interior of the mask frame 2100 from the upper surface of the mask frame 2100, the second electrode pattern 2620 can be located on the lower portion of the inorganic layer 2210 of the film 2200.

[0213] The second electrode pattern 2620 can be configured as a pattern formed of a conductive metallic material and can receive current from a separate power supply unit. For example, the second electrode pattern 2620 can receive current with the opposite polarity to the first electrode pattern 2610. For example, the second electrode pattern 2620 can receive negative current from a separate power supply unit.

[0214] As described above, currents of different polarities are supplied to the first electrode pattern 2610 and the second electrode pattern 2620, and an electric field can be generated near the first electrode pattern 2610 and the second electrode pattern 2620, thereby forming electrostatic attraction.

[0215] The first electrode pattern 2610 and the second electrode pattern 2620 can extend linearly in the first direction DR1 and the second direction DR2. Alternatively, the first electrode pattern 2610 and the second electrode pattern 2620 can extend in a curved shape or a shape with multiple bends in the first direction DR1 and the second direction DR2. Because the extension length of the first electrode pattern 2610 and the second electrode pattern 2620 is longer when extended in a curved shape or a shape with multiple bends than when extended linearly, a higher electrostatic attraction can be formed when the first electrode pattern 2610 and the second electrode pattern 2620 extend in a curved shape or a shape with multiple bends.

[0216] Figure 18 It shows along Figure 15 Another example of a cross-sectional view of a deposition mask cut by line I2-I2'. Figure 19 yes Figure 18 A magnified view of part B.

[0217] Reference Figure 18 and Figure 19 The electrode pattern portion 2600 may also include an insulating pattern 2630.

[0218] An insulating pattern 2630 may be located between the first electrode pattern 2610 and the second electrode pattern 2620 on the mask frame 2100. The insulating pattern 2630 may be introduced from the upper surface of the mask frame 2100 into the interior of the mask frame 2100 and located between the first electrode pattern 2610 and the second electrode pattern 2620. The insulating pattern 2630 may extend in a first direction DR1 and a second direction DR2 to insulate the first electrode pattern 2610 and the second electrode pattern 2620. The insulating pattern 2630 may include an insulating material. For example, the insulating pattern 2630 may include silicon oxide (SiO2). x The insulating pattern 2630 can prevent or reduce current leakage between the first electrode pattern 2610 and the second electrode pattern 2620.

[0219] Figure 20 This is a cross-sectional view showing the state of contact between a deposition mask and a backing substrate according to some embodiments of the present disclosure.

[0220] Reference Figure 20 The deposition mask 2000 can contact the backing substrate 3002 to deposit a deposition material on the backing substrate 3002. When current is supplied to the electrode pattern portion 2600 while the deposition mask 2000 is in contact with the backing substrate 3002, an electric field can be generated in the electrode pattern portion 2600 to form electrostatic attraction. For example, when a positive current is supplied to the first electrode pattern 2610 and a negative current is supplied to the second electrode pattern 2620, an electric field can be generated near the first electrode pattern 2610 and the second electrode pattern 2620 by supplying currents of different polarities. As described above, the electric field generated near the first electrode pattern 2610 and the second electrode pattern 2620 can form electrostatic attraction, and the adhesion between the film 2200 of the deposition mask 2000 and the backing substrate 3002 can be increased by the electrostatic attraction formed by the generated electric field.

[0221] Display devices manufactured using a deposition mask 2000 according to some embodiments of the present disclosure can be applied to various electronic devices. Electronic devices according to some embodiments include the aforementioned display device, and may also include modules or devices with additional features in addition to the display device.

[0222] Figure 21 This is a block diagram of an electronic device according to some embodiments of the present disclosure.

[0223] According to some embodiments, the electronic device 10000 may include a display module 10001, a processor 10002, a memory 10003, and a power module 10004.

[0224] The processor 10002 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0225] The data information required for the operation of the processor 10002 or the display module 10001 can be stored in the memory 10003. When the processor 10002 executes the application stored in the memory 10003, image data signals and / or input control signals can be sent to the display module 10001, and the display module 10001 can process the provided signals and output image information through the display screen.

[0226] The power module 10004 may include a power module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power module to generate the power required for the operation of the electronic device 10000.

[0227] At least one of the components of the electronic device 10000 described above may be included in the display device according to the above example embodiment. Furthermore, some modules that are functionally included within the electronic device may be included within the display device, while other modules may be provided separately from the display device. For example, the display device includes a display module 10001, and the processor 10002, memory 10003, and power module 10004 may be provided as other devices within the electronic device 10000 besides the display device.

[0228] Figure 22 This is a view illustrating an electronic device according to various embodiments of the present disclosure.

[0229] Reference Figure 22 Various electronic devices employing the display device according to the example embodiments may include not only image display electronic devices (such as smartphones 10000_1a, tablet PCs 10000_1b, laptop computers 10000_1c, TVs 10000_1d, and desktop monitors 10000_1e), but also wearable electronic devices (such as smart glasses 10000_2a, head-mounted displays 10000_2b, smartwatches 10000_2c, etc.) that include a display module, and vehicle electronic devices 10000_3 that include a display module (such as a central information display (CID) located on the vehicle's instrument panel, central dashboard, or dashboard, interior mirror display, etc.).

[0230] However, it should be understood that the aspects and features of the embodiments of this disclosure are not limited to those set forth herein. These and other aspects of this disclosure will become more apparent to those skilled in the art to which this disclosure pertains by referring to the claims and their equivalents, which will be included therein.

Claims

1. A deposition mask, the deposition mask comprising: A mask frame having unit openings formed therein; A membrane, on the upper part of the mask frame; as well as The electrode pattern portion is on the mask frame.

2. The deposition mask according to claim 1, wherein, The electrode pattern portion surrounds the unit opening while being spaced apart from it.

3. The deposition mask according to claim 1, wherein, The unit opening is configured as multiple unit openings, and The electrode pattern portion is located between the openings in the unit.

4. The deposition mask according to claim 1, wherein, The electrode pattern portion extends from the upper surface of the mask frame into the interior of the mask frame.

5. The deposition mask according to claim 1, in, The membrane is divided into a mask unit region on the upper part of the unit opening and a grid region on the upper part of the mask frame that does not include the mask unit region. The electrode pattern portion overlaps with the grid area.

6. The deposition mask according to claim 1, in, The membrane comprises: An inorganic layer on the upper part of the mask frame; and A nitride layer is placed on top of the inorganic layer. The electrode pattern portion is located on the lower part of the inorganic layer.

7. The deposition mask according to claim 1, in, The electrode pattern portion includes: First electrode pattern; and The second electrode pattern is spaced apart from the first electrode pattern and has the opposite polarity to the first electrode pattern.

8. The deposition mask according to claim 7, wherein, The electrode pattern portion also includes: An insulating pattern is located between the first electrode pattern and the second electrode pattern.

9. The deposition mask according to claim 1, in, The unit opening is configured as multiple unit openings. The plurality of unit openings are spaced apart in a first direction and in a second direction intersecting the first direction, and The electrode pattern portion extends in the first and second directions to surround the plurality of cell openings.

10. The deposition mask according to claim 9, wherein, The electrode pattern portion extends linearly in the first direction and the second direction.

11. The deposition mask according to claim 9, in, The electrode pattern portion extends in a curved shape in the first direction and the second direction.

12. An electronic device comprising a display device manufactured by a deposition mask. in, The deposition mask includes: A mask frame having unit openings formed therein; The membrane, on the upper part of the mask frame; and The electrode pattern portion is on the mask frame.

13. The electronic device according to claim 12, wherein, The electrode pattern portion surrounds the unit opening while being spaced apart from it.

14. The electronic device according to claim 12, wherein, The unit opening is configured as multiple unit openings, and The electrode pattern portion is located between the openings in the unit.

15. The electronic device according to claim 12, wherein, The electrode pattern portion extends from the upper surface of the mask frame into the interior of the mask frame.

16. The electronic device according to claim 12, wherein, The electrode pattern portion includes: First electrode pattern; and The second electrode pattern is spaced apart from the first electrode pattern and has the opposite polarity to the first electrode pattern.

17. The electronic device according to claim 16, wherein, The electrode pattern portion also includes: An insulating pattern is located between the first electrode pattern and the second electrode pattern.

18. The electronic device according to claim 12, wherein, The unit opening is configured as multiple unit openings. The plurality of unit openings are spaced apart in a first direction and in a second direction intersecting the first direction, and The electrode pattern portion extends in the first and second directions to surround the plurality of cell openings.

19. The electronic device according to claim 18, wherein, The electrode pattern portion extends linearly in the first direction and the second direction.

20. The electronic device according to claim 18, wherein, The electrode pattern portion extends in a curved shape in the first direction and the second direction.

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