Memory management method and memory controller

Abstract

A memory management method and a memory controller, the memory management method is applied to a storage device configured with a memory controller and a memory module. The method comprises: obtaining a write instruction, wherein the write instruction comprises to-be-written data and a first grade identifier of the to-be-written data; maintaining a plurality of free block queues of a grade table; determining a second grade identifier from the grade table according to the first grade identifier; matching the free block queue of the second grade identifier as a target free block queue, obtaining a first target free block from the target free block queue to write the to-be-written data into the first target free block. Through the above method, the write position can be allocated based on the mapping relationship between the data activity and the storage block wear degree, thereby reducing the triggering frequency of the wear leveling operation and reducing the performance overhead and life loss caused by the wear leveling operation.

Description

Technical Field

[0001] This disclosure relates to the field of data storage technology, and in particular to a memory management method and memory controller for optimizing data storage. Background Technology

[0002] In NAND flash memory storage devices, storage cells have a limited erase / write lifespan. After a certain number of erase / write cycles, the reliability of each storage block gradually decreases, potentially leading to data storage failure. Therefore, the number of erase / write cycles a storage block can undergo directly affects the lifespan of the entire storage device.

[0003] To extend the overall lifespan of storage devices, the Flash Translation Layer (FTL) typically employs a wear leveling strategy to balance the differences in write cycles between storage blocks. The basic principle of wear leveling is that when the difference in write cycles between certain storage blocks and other blocks exceeds a preset threshold, a data migration operation is triggered. This moves data from the storage blocks with lower write cycles to the storage blocks with higher write cycles, thus freeing up the lower-cycle-cycle blocks for subsequent writes.

[0004] However, existing wear leveling mechanisms have several problems. First, wear leveling involves reading and rewriting data, which consumes memory input / output (I / O) bandwidth, thus affecting normal read and write performance. Second, frequent wear leveling increases the write amplification factor (WAF), causing the actual number of erase / write operations on the storage block to exceed the number of writes requested by the host, thereby accelerating the wear of the storage block. Furthermore, existing technologies cannot control the data type subsequently written to the released block after the wear leveling operation is completed. If cold data with a low update frequency is written to a storage block with a low number of erase / write operations, wear leveling may be triggered again in a short period of time, creating a vicious cycle. Summary of the Invention

[0005] In view of this, this disclosure provides a memory management method and a memory controller, which reduces the accumulation of differences in the number of erase and write operations between memory blocks by establishing a reverse matching mechanism between data activity and memory block wear, thereby reducing the triggering frequency of wear leveling operations and reducing the performance loss and lifespan loss caused by wear leveling operations.

[0006] According to one aspect of this disclosure, a memory management method is provided, applied to a storage device configured with a memory controller and a memory module. The method includes: acquiring a write instruction, the write instruction including data to be written and a first level identifier of the data to be written; maintaining multiple free block queues of a level table; determining a second level identifier from the level table according to the first level identifier; using the free block queue matching the second level identifier as a target free block queue; acquiring a first target free block from the target free block queue to write the data to be written to the first target free block.

[0007] According to another aspect of this disclosure, a memory controller is provided, suitable for a storage device configured with a memory module, comprising: a memory interface control circuit for electrically connecting to the memory module; and a processor electrically connected to the memory interface control circuit, wherein the processor is configured to: acquire a write instruction, the write instruction including data to be written and a first level identifier of the data to be written; maintain a plurality of free block queues of a level table; determine a second level identifier from the level table according to the first level identifier; use the free block queue matching the second level identifier as a target free block queue; acquire a first target free block from the target free block queue to write the data to be written to the first target free block.

[0008] Based on the above, the memory management method and memory controller provided in this disclosure enable the memory controller to know the activity attribute of the data to be written by obtaining a write instruction carrying a first level identifier. The memory controller establishes a correspondence between storage blocks and wear levels by maintaining multiple free block queues in a level table. Upon receiving a write instruction, the memory controller determines a second level identifier from the level table based on the first level identifier, and uses the free block queue matching the second level identifier as the target free block queue, from which a first target free block is obtained to write the data to be written. Through this mechanism, data with high activity can be written to storage blocks with low wear, while data with low activity can be written to storage blocks with high wear. Because data with high activity has a high update frequency, the storage block containing it can be erased and reused through subsequent normal write operations, allowing the write / erase cycles of storage blocks with low wear to gradually increase. Simultaneously, because data with low activity is updated less frequently, the storage block containing it with high wear will not frequently generate new write / erase operations. Through the above reverse matching strategy, the difference in the number of erases and writes between storage blocks can gradually reach equilibrium during normal data writing, thereby reducing the need to trigger wear leveling operations, reducing the write amplification factor, and reducing the impact of wear leveling operations on input / output performance. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating a storage device and a host system according to an embodiment of the present invention;

[0010] Figure 2 This is a main flowchart of a memory management method according to an embodiment of the present invention;

[0011] Figure 3 This is a schematic diagram illustrating the reverse mapping relationship between a first-level identifier and a second-level identifier according to an embodiment of the present invention;

[0012] Figure 4 This is a schematic diagram of the mapping architecture from the first-level identifier to the free block queue according to an embodiment of the present invention;

[0013] Figure 5 This is a schematic diagram illustrating the process of hierarchical sorting and group initialization of free blocks according to an embodiment of the present invention;

[0014] Figure 6 This is a schematic diagram illustrating a scenario of downgraded allocation and subsequent correction when the target free block queue is insufficient, according to an embodiment of the present invention.

[0015] Figure 7 This is a flowchart illustrating the downgrade allocation and mismatch correction according to an embodiment of the present invention;

[0016] Figure 8 This is a schematic diagram illustrating dynamic hierarchical boundary adjustment based on queue water level according to an embodiment of the present invention;

[0017] Figure 9 This is a flowchart illustrating an adaptive storage strategy based on a data volume-based hierarchy table according to an embodiment of the present invention;

[0018] Figure 10 This is a timing diagram of a memory management method according to an embodiment of the present invention;

[0019] Figure 11 This is a schematic diagram of a mismatch data tracking table T111 shown according to an embodiment of the present disclosure. Detailed Implementation

[0020] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0021] Figure 1 This is a block diagram illustrating a host system and storage device according to embodiments of the present disclosure. Please refer to... Figure 1The host system 10 is, for example, a personal computer, a laptop computer, or a server. The host system 10 includes a processor 110 (also called a second processor), host memory 120 (also called host RAM), and a data transfer interface circuit 130. In this embodiment, the processor 110 is coupled (also called electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 are electrically connected to each other via a system bus. In this embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 may be disposed on the motherboard of the host system 10.

[0022] The storage device 20 includes a memory controller 210, a memory module 220 (also known as a rewritable non-volatile memory module), and a connection interface circuit 230. The memory controller 210 includes a processor 211 (also known as a first processor), a data management circuit 212, a memory interface control circuit 213, and a buffer memory 214.

[0023] In this embodiment, the host system 10 is electrically connected to the storage device 20 via a data transmission interface circuit 130 and a connection interface circuit 230 to perform data access operations. For example, the host system 10 can store data to or read data from the storage device 20 via the data transmission interface circuit 130.

[0024] In this embodiment, the number of data transmission interface circuits 130 can be one or more. Through the data transmission interface circuits 130, the motherboard can be electrically connected to the storage device 20 via wired or wireless means. The storage device 20 can be, for example, a USB flash drive, memory card, solid-state drive (SSD), or wireless storage device. The wireless storage device can be, for example, a Near Field Communication (NFC) storage device, a WiFi storage device, a Bluetooth storage device, or a Bluetooth Low Energy storage device (e.g., iBeacon), or other storage devices based on various wireless communication technologies. Furthermore, the motherboard can also be electrically connected via the system bus to various I / O devices such as a Global Positioning System (GPS) module, network interface card, wireless transmission device, keyboard, screen, and speaker.

[0025] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the Peripheral Component Interconnect Express (PCI Express) standard. Furthermore, data transmission between the data transmission interface circuit 130 and the connection interface circuit 230 utilizes the Non-Volatile Memory Express (NVMe) communication protocol.

[0026] In another embodiment, the connection interface circuit 230 may be packaged in a chip with the memory controller 210, or the connection interface circuit 230 may be disposed outside a chip containing the memory controller 210.

[0027] In this embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. In this embodiment, the host memory 120 may be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. However, it should be understood that this disclosure is not limited to this, and the host memory 120 may also be other suitable memories.

[0028] The memory controller 210 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the memory module 220 according to the instructions of the host system 10, and to execute the memory management method provided in this disclosure.

[0029] More specifically, the processor 211 in the memory controller 210 is hardware with computing capabilities, used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed with multiple control instructions / program codes, and these control instructions / program codes are executed when the storage device 20 is operating to perform operations such as writing, reading, and erasing data.

[0030] Furthermore, the processor 211 is configured to execute the memory management method provided in this disclosure. Specifically, the processor 211 is configured to obtain a write instruction, the write instruction including data to be written and a first level identifier of the data to be written; maintain multiple free block queues of a level table; determine a second level identifier from the level table according to the first level identifier; use the free block queue matching the second level identifier as a target free block queue; obtain a first target free block from the target free block queue to write the data to be written to the first target free block.

[0031] It is worth mentioning that, in this embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor, or other programmable processing units (microprocessor), digital signal processor (DSP), programmable controller, application specific integrated circuits (ASIC), programmable logic device (PLD), or other similar circuit components, and this disclosure is not limited thereto.

[0032] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by each component of the memory controller 210 can also be considered as operations performed by the memory controller 210 itself.

[0033] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213, and the connection interface circuit 230. The data management circuit 212 receives instructions from the processor 211 to perform data transmission. For example, it reads data from the host system 10 (e.g., host memory 120) via the connection interface circuit 230 and writes the read data into the memory module 220 via the memory interface control circuit 213. Alternatively, it performs a read operation according to a read instruction from the host system 10, reads data from one or more physical units of the memory module 220 via the memory interface control circuit 213, and writes the read data into the host system 10 via the connection interface circuit 230. In one embodiment, the data management circuit 212, in cooperation with the processor 211, writes the data to be written to the first target free block in the memory module 220 via the memory interface control circuit 213 after the processor 211 determines a first target free block from the target free block queue.

[0034] In another embodiment, the data management circuit 212 may also be integrated into the processor 211. The memory interface control circuit 213 is used to receive instructions from the processor 211 and cooperate with the data management circuit 212 to perform write (also known as programming) operations, read operations, or erase operations on the memory module 220.

[0035] Furthermore, data to be written to memory module 220 is converted into a format acceptable to memory module 220 via memory interface control circuit 213. Specifically, if processor 211 needs to access memory module 220, processor 211 transmits a corresponding instruction sequence to memory interface control circuit 213 to instruct memory interface control circuit 213 to perform the corresponding operation. For example, these instruction sequences may include write instruction sequences indicating the writing of data, read instruction sequences indicating the reading of data, erase instruction sequences indicating the erasure of data, and corresponding instruction sequences for indicating various memory operations. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, a read instruction sequence may include information such as the read identification code, memory address, and physical address.

[0036] Furthermore, the memory controller 210 establishes a logical-to-physical address mapping table and a physical-to-logical address mapping table to record the mapping relationship between the logical addresses of logical units (e.g., logical blocks, logical pages) and the physical addresses (physical addresses) of physical units (e.g., physical erase units / physical blocks, physical pages) configured for the memory module 220. In other words, the memory controller 210 can use the logical-to-physical address mapping table (also called the logical-to-physical mapping table) to look up the physical unit mapped to a logical unit (e.g., look up the physical page mapped to a logical page; look up the physical address mapped to a logical address), and the memory controller 210 can use the physical-to-logical address mapping table (also called the physical-to-logical mapping table) to look up the logical unit mapped to a physical unit (e.g., look up the logical page mapped to a physical page; look up the logical address mapped to a physical address).

[0037] Buffer memory 214 is electrically connected to processor 211 and is used to temporarily store data and instructions from host system 10, data from memory module 220, and various system data for managing storage device 20. In this embodiment, buffer memory 214 is also used to store a grading table required by this disclosure. The grading table records the mapping relationship between multiple free block queues and corresponding second grading identifiers, as well as the mapping relationship between first grading identifiers and second grading identifiers. In another embodiment, buffer memory 214 may also store mismatch information, which records that specific write data is not written to a suitable physical block / free block, that is, the wear level of the physical block used to store the mismatched data is not compatible with the (access) activity level of the mismatched data.

[0038] The memory module 220 is electrically connected to the memory controller 210 (specifically, electrically connected to the memory interface control circuit 213) and is used to store user data sent by the host system 10. In this disclosure, the memory module 220 includes multiple free blocks, which are divided into multiple free block queues in a grading table according to their respective erase / write cycles, and serve as targets for writing data. The processor 211 selects a first target free block from the corresponding free block queue according to the first grading identifier in the write instruction to write the data. It should be noted that the grading table can also be stored within the memory module 220.

[0039] In one embodiment, the memory cell structure of the memory module 220 can be understood as a multi-layered physical organization architecture. Specifically, the memory module 220 includes multiple chips, each chip has multiple planes, and each plane contains multiple physical blocks, each physical block consisting of multiple physical pages. It should be noted that this disclosure is not limited to the specific size of each physical page and logical page.

[0040] Reference Figure 2 In step S210, the processor 211 obtains a write instruction, which includes data to be written and a first-level identifier of the data to be written. Specifically, in one embodiment, the write instruction comes from the host system 10. When sending the write instruction, the host system 10 determines the corresponding first-level identifier based on the data activity of the data to be written, and encapsulates the first-level identifier and the data to be written together in the write instruction. The first-level identifier is used to indicate the activity level of the data to be written. For example, the higher the value of the first-level identifier, the higher the update frequency of the data to be written; the lower the value of the first-level identifier, the lower the update frequency of the data to be written.

[0041] In step S220, the processor 211 maintains multiple free block queues in a grading table. Specifically, in one embodiment, the processor 211 manages multiple free blocks in the memory module 220 and allocates them to corresponding free block queues according to their respective wear levels. The grading table records the mapping relationship between first-level identifiers and second-level identifiers, and the multiple free block queues correspond to different second-level identifiers. By maintaining multiple free block queues, the processor 211 can understand the wear status of each free block in the memory module 220 and its corresponding grading classification.

[0042] In step S230, the processor 211 determines the second level identifier from the level table based on the first level identifier. Specifically, in one embodiment, the processor 211 queries the level table based on the first level identifier carried in the write instruction to determine the second level identifier corresponding to the first level identifier. A mapping relationship between the first level identifier and the second level identifier is pre-established in the level table, enabling the processor 211 to quickly locate the corresponding second level identifier based on the first level identifier.

[0043] In step S240, the processor 211 selects the free block queue matching the second-level identifier as the target free block queue, retrieves the first target free block from the target free block queue, and writes the data to be written into the first target free block. Specifically, in one embodiment, the processor 211 locks the corresponding free block queue among multiple free block queues according to the second-level identifier determined in step S230, and determines the free block queue as the target free block queue. Subsequently, the processor 211 selects a free block from the target free block queue as the first target free block, and writes the data to be written into the first target free block in the memory module 220 through the memory interface control circuit 213.

[0044] Through steps S210 to S240, the processor 211 can write the data to be written to a free block that matches its activity level, based on the first level identifier of the data to be written. Since the level table establishes a correspondence between data activity and storage block wear level, data with higher activity can be allocated to free blocks with lower wear levels, while data with lower activity can be allocated to free blocks with higher wear levels. This mechanism allows the differences in write / erase counts between storage blocks to gradually balance out during normal data writing, thereby reducing the need to trigger passive wear leveling operations.

[0045] It is worth mentioning that, in one embodiment, to enable the host system 10 to transmit the first-level identifier of the data to be written to the storage device 20, this disclosure designs an extended write instruction format. Specifically, based on the standard write instruction, a preset field is added to carry the first-level identifier. In this embodiment, the size of the preset field is one byte, and its value ranges from 0 to 5. When the value of the preset field is 1 to 5, it corresponds to the five levels of the first-level identifier, where a larger value indicates a higher level of the data to be written (i.e., higher activity); when the value of the preset field is 0, it indicates that the host system 10 cannot determine the level of the data to be written, or the host system 10 has not provided level information, i.e., it corresponds to an unknown level.

[0046] In another embodiment, the extended write command format can be implemented based on the Non-Volatile Memory Express (NVMe) protocol. Specifically, the processor 211 can obtain the first-level identifier by parsing a reserved field or a vendor-specific field in the NVMe write command. In yet another embodiment, the host system 10 can transmit the first-level identifier to the storage device 20 via a vendor-specific command of the NVMe protocol.

[0047] When processor 211 receives a write command, it checks the value of the first level identifier field carried in the write command. If the value is 1 to 5, processor 211 executes the memory management method of this disclosure according to the first level identifier, writing the data to be written to a free block that matches its level; if the value is 0, processor 211 does not perform the matching step based on the level table, but processes the data to be written according to a preset write strategy. In one embodiment, the preset write strategy may be to allocate the data to be written to a free block queue with a medium wear level; in another embodiment, the preset write strategy may be to process the data to be written according to a traditional wear leveling algorithm, without considering the level matching of the data to be written.

[0048] Reference Figure 3 , Figure 3 Explain the mapping relationship between the first-level identifier and the second-level identifier recorded in the rating table T31.

[0049] Specifically, such as Figure 3 As shown in block B310 on the left, the first-level identifier is used to indicate the data activity of the data to be written. In this embodiment, the processor 211 divides the first-level identifier into five levels, namely LV1 to LV5. LV1 corresponds to extremely cold data, i.e., data with a very low update frequency or almost no update; LV2 corresponds to cold data, i.e., data with a low update frequency; LV3 corresponds to warm data, i.e., data with a medium update frequency; LV4 corresponds to hot data, i.e., data with a relatively high update frequency; and LV5 corresponds to extremely hot data, i.e., data with an extremely high update frequency. Figure 3 As indicated by the arrow on the left, the higher the value of the first-level identifier, the higher the activity level of the data to be written.

[0050] like Figure 3 As shown in block B320 on the right, the second-level identifier is used to indicate the wear level corresponding to the free block queue. In this embodiment, the processor 211 divides the second-level identifier into five levels, namely LVA to LVE. LVA corresponds to a low wear level, that is, the level corresponding to free blocks with a low write / erase cycle (P / E cycle); LVE corresponds to a high wear level, that is, the level corresponding to free blocks with a high write / erase cycle; LVB, LVC, and LVD represent intermediate wear levels between LVA and LVE, respectively. Figure 3 As indicated by the arrow on the right, the second level is marked from LVA to LVE, with the corresponding wear levels gradually increasing.

[0051] like Figure 3As shown in the central level table T31, the processor 211 determines the second level identifier based on the mapping relationship between the first level identifier and the second level identifier. Specifically, as shown by arrow A31, when the first level identifier is LV5 (extremely hot data), the processor 211 maps it to the second level identifier LVA (low wear); as shown by arrow A32, when the first level identifier is LV4 (hot data), the processor 211 maps it to the second level identifier LVB; as shown by arrow A33, when the first level identifier is LV3 (warm data), the processor 211 maps it to the second level identifier LVC; as shown by arrow A34, when the first level identifier is LV2 (cold data), the processor 211 maps it to the second level identifier LVD; and as shown by arrow A35, when the first level identifier is LV1 (extremely cold data), the processor 211 maps it to the second level identifier LVE (high wear).

[0052] As shown in the mapping relationship above, the higher the data activity indicated by the first-level identifier, the lower the wear level corresponding to the mapped second-level identifier. The core principle of this reverse mapping strategy is that data with high activity (hot data) is allocated to free blocks with low wear levels. Because hot data has a high update frequency, the free blocks where it resides will be frequently erased and reused through subsequent normal write operations, thereby gradually increasing the number of erase / write operations on the free blocks with low wear levels. Conversely, data with low activity (cold data) is allocated to free blocks with high wear levels. Because cold data is updated less frequently, the free blocks where it resides will not generate new erase / write operations frequently, thus preventing the free blocks with high wear levels from further accumulating erase / write operations.

[0053] In a practical application scenario, let's take solid-state drive (SSD) storage of the operating system and user files as an example. Operating system temporary files, page files, and browser caches have a high update frequency. The host system 10 can mark this type of data as LV5 or LV4, allowing it to be written to free blocks with lower write cycles. Conversely, operating system kernel image files, installed application files, and user history archives are typically not modified after being written. The host system 10 can mark this type of data as LV1 or LV2, allowing it to be written to free blocks with higher write cycles. Through this allocation strategy, frequently updated hot data can continuously consume the remaining lifespan of low-wear free blocks, while long-term stagnant cold data will not impose additional write burdens on high-wear free blocks, thus gradually balancing the differences in write cycles between free blocks during normal use.

[0054] In another embodiment, when the host system 10 does not provide a first-level identifier or the provided first-level identifier value is 0, the processor 211 can independently determine the activity level of the data to be written and determine the corresponding level. Specifically, the processor 211 can infer the activity level of the data to be written based on the historical write frequency, write interval time, or write mode characteristics of the logical block address (LBA) of the data to be written. Taking a solid-state drive controller as an example, the processor 211 can maintain a logical address access statistics table (LBA Access Table) in the buffer memory 214 to record the number of writes to each logical address within a specific time window or the timestamp of the most recent write.

[0055] When processor 211 receives a write command without a first-level identifier, it queries the access statistics table. If the target logical address of the data to be written has accumulated multiple write records in a short period of time (e.g., within the past 10 minutes), or if the write interval is less than a preset threshold, processor 211 can determine that the data has high activity (hot data) and allocate it to the free block queue corresponding to the low wear level. Conversely, if the target logical address has not had any write records in a long period of time (e.g., within the past 24 hours), or if it is a large-capacity sequential write for the first time, processor 211 can determine that the data has low activity (cold data) and allocate it to the free block queue corresponding to the high wear level. Through this statistical mechanism based on historical behavior, even in the absence of explicit host tags, storage device 20 can still achieve a certain degree of active wear leveling.

[0056] In another embodiment, the processor 211 can determine the activity level based on the characteristic patterns of write requests. For example, small random write requests typically correspond to data with high activity levels (such as database transaction logs), while large sequential write requests typically correspond to data with low activity levels (such as multimedia files or backup data). Through this mechanism, even if the host system 10 does not provide data activity information, the storage device 20 can still execute the memory management method of this disclosure based on its own observation and analysis.

[0057] In another embodiment, the number of levels disclosed herein is not limited to five. Depending on the capacity of the storage device 20, the number of free blocks in the memory module 220, and the level of detail in the data activity information provided by the host system 10, the processor 211 may divide the first level identifier and the second level identifier into more or fewer levels. For example, in a storage device with a smaller storage capacity, the processor 211 may simplify the number of levels to three (e.g., hot, warm, cold); in a storage device with a larger storage capacity and requiring more granular management, the processor 211 may expand the number of levels to seven or more. Furthermore, the terms used to describe data activity are not limited to expressions such as "extremely hot," "hot," "warm," "cold," and "extremely cold" used in this embodiment; numerical ranges, frequency intervals, or other terms with equivalent meanings may also be used. However, regardless of the number of levels or the terminology, the inverse correspondence between the data activity indicated by the first level identifier and the wear level corresponding to the second level identifier remains unchanged; that is, the higher the data activity, the lower the mapped wear level.

[0058] It should be noted that in another embodiment, the number of first-level identifiers may not be equal to the number of second-level identifiers. Specifically, the number of first-level identifiers provided by the host system 10 may be more or less than the number of second-level identifiers maintained internally by the storage device 20, and the mapping relationship in the level table T31 may be configured accordingly as a many-to-one mapping or a one-to-many mapping. Taking a many-to-one mapping as an example, assuming that the host system 10 divides data activity into seven first-level identifiers (LV1 to LV7), and the storage device 20 maintains only three free block queues (corresponding to three second-level identifiers LVA, LVB, and LVC) based on the distribution of free blocks in the memory module 220, then the level table T31 can be configured with the following mapping relationship: LV7, LV6, and LV5 are mapped to LVA; LV4 and LV3 are mapped to LVB; and LV2 and LV1 are mapped to LVC. Through this many-to-one mapping, the processor 211 can integrate the activity levels provided by the host system 10 to the number of free block queues that the storage device 20 can support. Taking a one-to-many mapping as an example, assuming the host system 10 provides only three first-level identifiers (high, medium, and low), and the storage device 20 maintains five free block queues, the processor 211 can dynamically map the same first-level identifier to different second-level identifiers based on the current number of free blocks in each free block queue. For example, when the first-level identifier is "high" and there are enough available free blocks in free block queue A, the processor 211 maps it to LV A; when the number of available free blocks in free block queue A is lower than a preset threshold, the processor 211 can map it to LV B. Through this flexible mapping mechanism, the memory management method of this disclosure can adapt to situations where the granularity of level division is inconsistent between different host systems and storage devices, while maintaining the inverse correspondence between data activity and wear level.

[0059] In another embodiment, the storage method of the mapping relationship disclosed herein is not limited to using a hierarchy table as the data structure. The processor 211 may employ other suitable data structures to record the mapping relationship between the first-level identifier and the second-level identifier, such as a hash table, a binary search tree, or a direct addressing array. In some embodiments, the processor 211 may even directly calculate the corresponding second-level identifier based on the first-level identifier using a preset mapping function or mapping algorithm, without needing to query the mapping table stored in the buffer memory 214.

[0060] In another embodiment, although this disclosure primarily describes an indirect mapping mechanism based on first-level identifiers and second-level identifiers, in certain specific application scenarios, the processor 211 may also adopt a more direct data placement strategy. Specifically, the processor 211 may predefine a direct correspondence between specific data types (such as system temporary files, user documents, multimedia files, etc.) and target free block queues. In this case, when the host system 10 sends a write command, it can directly encode the data type as a second-level identifier, and the storage device 20 internally maps the second-level identifier directly to the corresponding free block queue, thereby simplifying the mapping process. Although this modified implementation omits the identifier conversion / mapping between the two levels, it essentially still follows the core idea of ​​selecting different wear level queues based on data characteristics.

[0061] It should be noted that, to support the aforementioned queue management, the processor 211 maintains a free block mapping table in the buffer memory 214. The free block mapping table records each free block queue (corresponding to different wear levels or data types) and a list of physical addresses of the specific free blocks currently contained in each queue. When the processor 211 determines the target free block queue, it queries the free block mapping table and retrieves an available free block from the corresponding physical address list to perform a write operation. Although this modified implementation omits the explicit second-level identifier conversion, it essentially still follows the core idea of ​​selecting different wear level queues based on data characteristics and ensures accurate allocation of physical blocks by maintaining a specific mapping table.

[0062] As can be seen from the above embodiments, this disclosure establishes a reverse mapping relationship between the first-level identifier and the second-level identifier, so that data with higher activity is written to free blocks with lower wear levels, while data with lower activity is written to free blocks with higher wear levels. This strategy allows the number of erase / write operations of each free block in the memory module 220 to gradually reach a balance during normal data writing, thereby reducing the need to trigger passive wear leveling operations from the source.

[0063] Reference Figure 4 ,like Figure 4 As shown above, the process of mapping the first level identifier B410 to the second level identifier B420 through the level table T41 has been described above. Figure 3 As illustrated in this embodiment, this embodiment will focus on explaining the correspondence between the second-level identifier B420 and the multiple free block queues B430.

[0064] like Figure 4As shown in block B420 on the right, the second-level identifier is used to indicate the wear level corresponding to the idle block queue. In this embodiment, multiple idle block queues correspond to different second-level identifiers. Specifically, as shown by arrow A43, after the processor 211 determines the second-level identifier from the level table T41 based on the first-level identifier, the processor 211 uses the idle block queue matching the second-level identifier as the target idle block queue.

[0065] like Figure 4 As shown in block B430 below, multiple free block queues include Free Block Queue A, Free Block Queue B, Free Block Queue C, Free Block Queue D, and Free Block Queue E, corresponding to identifiers A, B, C, D, and E, respectively. Free Block Queue A corresponds to identifier A (low wear), and the free blocks in Free Block Queue A have a low write / erase cycle count. Free Block Queue E corresponds to identifier E (high wear), and the free blocks in Free Block Queue E have a high write / erase cycle count. Free Block Queues B, C, and D correspond to intermediate wear levels between identifiers A and E. Each free block queue contains one or more free blocks, which are recorded in the corresponding queue entry of the level table T41 in the form of Physical Block Address (PBA). The Physical Block Address is an address at the Flash Translation Layer (FTL) level, which masks factory-damaged blocks and blocks damaged during operation.

[0066] In this embodiment, after locating the corresponding free block queue according to the second level identifier, the processor 211 obtains the first target free block from the target free block queue. Specifically, when the second level identifier is identifier A, the processor 211 uses free block queue A as the target free block queue and selects a free block from free block queue A as the first target free block; when the second level identifier is identifier E, the processor 211 uses free block queue E as the target free block queue and selects a free block from free block queue E as the first target free block. Subsequently, the processor 211 writes the data to be written to the first target free block in the memory module 220 through the memory interface control circuit 213. After the data is successfully written to the first target free block, the processor 211 removes the physical block address of the first target free block from the corresponding free block queue in the level table T41 to reflect the state that the free block has been occupied.

[0067] For example, when host system 10 sends a transaction log write request carrying identifier 5 (extremely high activity), processor 211 queries level table T41 to determine that the second level identifier is identifier A, and then selects free block queue A as the target free block queue. Assuming that free block queue A currently contains five free blocks with physical block addresses PBA_001, PBA_015, PBA_023, PBA_042, and PBA_056, processor 211 selects PBA_001 as the first target free block, writes the transaction log to this free block, and removes PBA_001 from free block queue A. Subsequently, when the transaction log is marked as invalid data due to subsequent updates, and the free block it resides in is erased by garbage collection, processor 211 reclassifies it into the free block queue corresponding to the wear level based on the number of writes and erases the updated free block.

[0068] Through the correspondence between the second-level identifier and multiple free block queues, the processor 211 can quickly locate the queue containing free blocks of the corresponding wear level according to the second-level identifier, and thus write the data to be written to the storage location that matches its activity level.

[0069] Reference Figure 5 This embodiment will describe how the processor 211 maintains multiple free block queues in the grading table, including the complete process of obtaining the erase / write counts of each of the multiple free blocks, sorting the multiple free blocks, and dividing the multiple free blocks into the corresponding multiple free block queues.

[0070] like Figure 5 As shown in block B510 above, in step 1, processor 211 obtains the erase / write counts of each of the multiple free blocks in memory module 220. In this embodiment, memory module 220 contains nine free blocks, namely free blocks B1 to free blocks B9, with the following erase / write counts for each free block: 150 erase / write times for free block B1, 50 erase / write times for free block B2, 400 erase / write times for free block B3, 200 erase / write times for free block B4, 30 erase / write times for free block B5, 250 erase / write times for free block B6, 80 erase / write times for free block B7, 350 erase / write times for free block B8, and 100 erase / write times for free block B9. Processor 211 sends a query request to memory module 220 through memory interface control circuit 213 to obtain the erase / write count information of each of the multiple free blocks. The erase / write count information can be stored in a specific management area of ​​the memory module 220, or continuously tracked and recorded in the buffer memory 214 by the memory controller 210 during operation.

[0071] As shown by arrow A51, in step 2, processor 211 sorts multiple free blocks according to the number of erase / write cycles. Figure 5 As shown in central block B520, processor 211 performs a sorting operation, arranging multiple free blocks in ascending order of erase / write counts. After sorting, the order of the free blocks is as follows: free block B5 (30 erases), free block B2 (50 erases), free block B7 (80 erases), free block B9 (100 erases), free block B1 (150 erases), free block B4 (200 erases), free block B6 (250 erases), free block B8 (350 erases), and free block B3 (400 erases). Figure 5 As shown by the gradient color bar in the center, the sorted sequence of free blocks exhibits a continuous distribution from low erase counts to high erase counts.

[0072] As shown by arrow A52, in step 3, the processor 211 divides the multiple free blocks into multiple groups according to a preset method based on the sorting result, and maps each group into a multiple free block queue. In this embodiment, the processor 211 uses an equal division method. Specifically, the processor 211 divides the nine sorted free blocks into three groups (assuming there are three wear levels), with each group containing three free blocks. Figure 5 As shown in the lower block BQ, the first group contains idle blocks B5 (30 times), B2 (50 times), and B7 (80 times). The first group is mapped to idle block queue 1 (BQ1) and corresponds to the second level identifier A (low wear). The second group contains idle blocks B9 (100 times), B1 (150 times), and B4 (200 times). The second group is mapped to idle block queue 2 (BQ2) and corresponds to the second level identifier B. The third group contains idle blocks B6 (250 times), B8 (350 times), and B3 (400 times). The third group is mapped to idle block queue 3 (BQ3) and corresponds to the second level identifier C (high wear).

[0073] By using the above-described equal distribution method, processor 211 can ensure that each free block queue has available free blocks in the initial state.

[0074] In a practical application scenario, the initialization process of a solid-state drive (SSD) controller will be used as an example. When the SSD is powered on for the first time or after a formatting operation, the processor 211 scans all free blocks in the memory module 220 and obtains the erase / write count of each free block. Assuming the memory module 220 contains 3000 free blocks, the processor 211 sorts these 3000 free blocks by erase / write count and divides them into five groups, each containing 600 free blocks. The 600 free blocks with the lowest erase / write count are assigned to free block queue A, the 600 free blocks with the highest erase / write count are assigned to free block queue E, and the remaining free blocks are assigned to free block queues B, C, and D in sequence. Through this equal allocation mechanism, even during the initial operation phase of the storage device 20, the processor 211 can provide sufficient target free blocks for various levels of write requests.

[0075] It should be noted that, in another embodiment, multiple free blocks are divided into multiple groups according to a preset method. When the total number of multiple free blocks cannot be divided evenly by the number of free block queues, the processor 211 can allocate the remaining free blocks to specific free block queues. For example, when the memory module 220 contains 100 free blocks and needs to be divided into three free block queues, the processor 211 can allocate 33 free blocks to free block queue 1, 33 free blocks to free block queue 2, and 34 free blocks to free block queue 3.

[0076] A specific free block queue can be defined as follows. In one embodiment, the specific free block queue is the free block queue corresponding to the lowest wear level. Since the write frequency of highly active data is relatively high, the free block queue corresponding to the lowest wear level is usually consumed faster. Allocating the remaining free blocks to the free block queue can increase its initial capacity, thereby delaying the timing when the free block queue will trigger a downgrade allocation due to exhaustion.

[0077] In another embodiment, the specific free block queue is the free block queue corresponding to the highest wear level. Since low-activity data is rarely updated after being written, the free blocks in the free block queue corresponding to the highest wear level are difficult to release back to the idle state through the normal data update process after being used. Allocating the remaining free blocks to the free block queue can provide more initial storage resources for low-activity data.

[0078] In another embodiment, a specific idle block queue is an idle block queue corresponding to an intermediate wear level. This allocation method can balance the initial capacity of the idle block queues for each wear level, avoiding the impact of excessively large or small initial capacity of the idle block queues for extreme wear levels on the overall wear leveling effect.

[0079] In another embodiment, the processor 211 determines a specific free block queue based on the expected workload distribution. Specifically, the processor 211 can predict the proportion of write requests for each first-level identifier based on the expected usage scenarios or historical write patterns of the storage device 20, and preferentially allocate the remaining free blocks to the free block queues with expected faster consumption rates. For example, when the expected proportion of write requests for highly active data is 60%, the proportion of moderately active data is 30%, and the proportion of low-active data is 10%, the processor 211 can allocate the remaining free blocks to the corresponding free block queue for highly active data.

[0080] In another embodiment, when the number of remaining free blocks is greater than 1, the processor 211 can distribute the remaining free blocks among multiple free block queues instead of concentrating them into a single free block queue. For example, when the memory module 220 contains 103 free blocks and needs to be divided into five free block queues, the processor 211 can allocate 21 free blocks to free block queue 1, 21 free blocks to free block queue 2, 21 free blocks to free block queue 3, 20 free blocks to free block queue 4, and 20 free blocks to free block queue 5, thus distributing the remaining 3 free blocks among the first three free block queues. This distributed allocation method can maintain a relatively balanced initial capacity among the free block queues.

[0081] In another embodiment, the preset method includes a preset ratio, whereby the processor 211 divides the sorted free blocks into multiple groups according to the preset ratio. Specifically, the processor 211 can set the proportion of free blocks in each free block queue based on the expected usage scenario of the storage device 20 or the data activity distribution characteristics of the host system 10. For example, when a large proportion of write requests are expected to be highly active, the processor 211 can allocate more free blocks to the corresponding low-wear level free block queue. Taking nine free blocks as an example, the processor 211 can divide the free blocks into four groups according to a ratio of 3:3:2:1, such that free block queue A contains three free blocks, free block queue B contains three free blocks, free block queue C contains two free blocks, and free block queue D contains one free block.

[0082] In another embodiment, the preset method includes preset thresholds, and the processor 211 divides multiple free blocks into multiple groups according to the number of erase / write cycles. Specifically, the processor 211 presets multiple erase / write cycle thresholds and assigns each free block to a corresponding group based on its erase / write cycle count. For example, the processor 211 can set the threshold sequence to 100, 200, and 300 cycles. Then, free blocks with erase / write cycles between 0 and 100 are assigned to free block queue A, free blocks with erase / write cycles between 101 and 200 are assigned to free block queue B, free blocks with erase / write cycles between 201 and 300 are assigned to free block queue C, and free blocks with erase / write cycles exceeding 300 are assigned to free block queue D. This threshold grouping method can ensure that the free blocks in each free block queue have similar wear levels, but may result in an uneven distribution of the number of free blocks in each queue.

[0083] In another embodiment, the preset method includes preset percentiles, whereby the processor 211 divides multiple free blocks into multiple groups according to percentiles. Specifically, based on the sorted sequence of free blocks, the processor 211 assigns free blocks with the top 20% of erase / write counts to free block queue A, free blocks with erase / write counts between 20% and 40% to free block queue B, and so on. This percentile grouping method ensures that each free block queue contains the same proportion of free blocks, and its effect is similar to the equal distribution method, but it is more intuitive to describe.

[0084] Regardless of the grouping method used, the goal of the processor 211 is to establish a correspondence between the number of erase / write operations and the free block queue, so that free blocks with a lower number of erase / write operations are assigned to the free block queue corresponding to the low wear level, and free blocks with a higher number of erase / write operations are assigned to the free block queue corresponding to the high wear level, thereby supporting the reverse matching strategy based on data activity and wear level disclosed herein.

[0085] It is worth mentioning that, in another embodiment, when the first target free block in the target free block queue is insufficient, the data to be written that has not yet been written to the first target free block can be borrowed according to the bidirectional borrowing strategy of the queue level executed by the processor 211. Specifically, the processor 211 can borrow from adjacent queues with higher wear levels (degradation allocation) and also borrow from adjacent queues with lower wear levels (upgradation allocation), and the specific borrowing direction depends on the number of free blocks in the adjacent queues. More specifically, when the first target free block is insufficient, the processor 211, based on the target free block queue, confirms the free blocks of adjacent queues with higher wear levels (first adjacent queue) and adjacent queues with lower wear levels (second adjacent queue), compares them, reconfirms the target free block queue according to the comparison result, and writes the data to be written that has not yet been written to the first target free block to the second target free block to continue writing the data to be written, ensuring that the data writing is successful.

[0086] For example, assuming the first level identifier of the write instruction corresponds to warm data, processor 211 determines the target free block queue as free block queue C corresponding to the medium wear level. If free block queue C is insufficient, processor 211 simultaneously checks the current number of free blocks in adjacent free block queues B and D with lower wear levels and higher wear levels. Specifically, processor 211 uses free block queue B as the second adjacent queue and free block queue D as the first adjacent queue, and compares the number of free blocks in the first adjacent queue with the number in the second adjacent queue.

[0087] When processor 211 detects that the number of free blocks in free block queue B is greater than that in free block queue D, or when the number of free blocks in free block queue B is higher than a preset water level threshold while the number of free blocks in free block queue D is lower than the preset water level threshold, processor 211 selects to execute an upgrade allocation strategy. In this scenario, processor 211 obtains a second target free block from free block queue B with a lower wear level and writes the warm data to the second target free block. This upgrade allocation strategy can prioritize the use of surplus storage resources to ensure the continuity of write operations when resource allocation among free block queues is uneven, avoiding write delays caused by waiting for a specific free block queue to release free blocks.

[0088] Similar to the downgrade allocation, processor 211 marks the warm data written to free block queue B as temporary mismatch data. In subsequent garbage collection operations, when a free block is released from the original target free block queue C, processor 211 migrates the temporary mismatch data from free block queue B to free block queue C to restore the matching relationship between data placement and wear level.

[0089] In another embodiment, the processor 211 can dynamically adjust its processing strategy based on the actual access behavior of temporary mismatched data during storage. Specifically, if the processor 211 detects an increase in the access frequency of temporary mismatched data after it is written to the free block queue B through the access behavior tracking table, indicating that the actual activity of the data has changed from warm data to hot data, the processor 211 can determine that the data is currently stored in the free block queue B with a lower wear level, which is consistent with its actual activity attribute. In this case, the processor 211 removes the tag of the temporary mismatched data and updates the first-level identifier corresponding to the data in the level table, so that the data is retained in the free block queue B without performing a migration operation. Through this dynamic adjustment mechanism, the processor 211 can adaptively optimize based on the actual access behavior of the data in the upgrade allocation scenario, reducing unnecessary data migration operations. It should be noted that, in another embodiment, in order to achieve full wear leveling more deeply, the processor 211 can be configured to uniformly adopt the "upgrade allocation" strategy when the target free block queue is insufficient. Specifically, when a free block cannot be obtained from the target free block queue that matches the data level, the processor 211 does not borrow from the queue with a higher wear level (i.e., does not perform degradation), but instead forces the acquisition of a second target free block from the free block queue with a lower wear level than the target free block queue (i.e., the "young" queue with fewer erase / write cycles).

[0090] The technical consideration behind this strategy is that when the target queue (typically corresponding to a certain intermediate or higher wear level) is exhausted, using a degradation strategy to borrow from a higher wear queue would further exacerbate the wear of those "older" physical blocks, leading to a widening wear gap. Conversely, while an upgrade strategy might result in cold data being written to low-wear blocks (seemingly a resource mismatch), this actually provides a valuable opportunity to actively consume the write / erase cycle (P / E cycle) of low-wear physical blocks. Through this mechanism, the system can take advantage of every instance of queue shortage to force low-wear physical blocks to participate in write operations, accelerating their write / erase cycles to catch up with high-wear physical blocks, thereby macroscopically causing the wear levels of all physical blocks in memory module 220 to converge more quickly.

[0091] Reference Figure 6 This embodiment will explain how the processor 211 obtains a second target free block from the adjacent free block queue to continue writing the data to be written when the first target free block in the target free block queue is insufficient.

[0092] like Figure 6As shown in block B610 above, this embodiment describes the following scenario: Processor 211 receives a write instruction, the first level identifier of which is LV5 (extremely hot data). According to the reverse mapping strategy of the aforementioned embodiment, processor 211 queries the level table to determine that the target second level identifier is LVA, and uses free block queue A (BQA) as the target free block queue. However, as Figure 6 As shown in block BQA, the free block queue A is currently empty or insufficient, and cannot provide available free blocks for writing data. In this case, processor 211 triggers a degraded allocation mechanism to ensure that the write operation can continue.

[0093] like Figure 6 As shown in the middle block BQ (set of free block queues), multiple free block queues include free block queue A (BQA), free block queue B (BQB), free block queue C (BQC), and free block queue E (BQE). Free block queue A is the target free block queue, corresponding to the lowest wear level; free block queue B is the free block queue adjacent to free block queue A, with a wear level higher than free block queue A but lower than free block queue C. When processor 211 detects that the target free block queue is insufficient, as shown by arrow A61, processor 211 performs a downgrade allocation operation, downgrading the target for acquiring free blocks from free block queue A to the adjacent free block queue B.

[0094] As shown by arrow A62, processor 211 obtains a second target free block from the adjacent free block queue B (BQB) to continue writing the data to be written. Specifically, processor 211 selects an available free block in free block queue B as the second target free block, and writes the data to be written into the second target free block in memory module 220 through memory interface control circuit 213. Figure 6 As shown in the lower left block TB, the second target free block is obtained from the adjacent free block queue B. After completing the write operation, the processor 211 marks the data to be written into the second target free block as temporary mismatch data. The marking information of the temporary mismatch data can be stored in the mismatch data tracking table in the buffer memory 214 for use in subsequent migration correction operations.

[0095] like Figure 6As shown in block B620 on the lower right, processor 211 performs a migration correction operation in the background. Specifically, when processor 211 performs garbage collection, it identifies temporary mismatched data and migrates it to a free block that matches the first-level identifier. In this embodiment, since the first-level identifier of the data to be written is LV5, after a free block becomes available in free block queue A, processor 211 migrates the temporary mismatched data from the second target free block to a free block in free block queue A. After the migration is completed, processor 211 removes the marker from the temporary mismatched data, ensuring that the data to be written is ultimately stored in a storage location that matches its activity level.

[0096] Through the aforementioned degraded allocation mechanism, processor 211 can maintain continuous write service even in extreme cases where the target free block queue is insufficient, thereby eliminating the risk of write blocking. Simultaneously, through the marking of temporary mismatched data and the background migration correction mechanism, processor 211 can migrate mismatched hot data back to the correct level of free block after a free block in free block queue A is released, avoiding permanent impact on the wear leveling strategy due to degraded allocation.

[0097] In another embodiment, when the free block queue B is also insufficient, the processor 211 can continue to degrade to the free block queue C to obtain free blocks, and so on, until a queue with available free blocks is found to complete the write operation. This multi-level continuous degradation mechanism can further improve the write availability of the storage device 20 under extreme resource imbalance conditions.

[0098] In a practical application scenario, the handling of sudden hot data writes by a solid-state drive controller is illustrated as an example. When the host system 10 performs a large number of database transaction commit operations, a large number of hot data write requests carrying LV5 identifiers will be generated in a short period of time. Assuming that the free block queue A initially contains 100 free blocks, when the continuous hot data write requests exhaust all the free blocks in the free block queue A, the processor 211 triggers a degradation allocation mechanism, acquiring free blocks from the free block queue B to continue serving subsequent write requests. At the same time, the hot data previously written to the free block queue A is gradually marked as invalid data due to frequent updates. When the processor 211 performs garbage collection operations on these free blocks, the erased free blocks will be reassigned to the corresponding free block queues according to their updated erase / write counts, thereby gradually restoring the number of available free blocks in the free block queue A. During this process, the processor 211 also identifies temporary mismatched data stored in the free block queue B and migrates it to newly released free blocks in the free block queue A, completing the mismatch correction.

[0099] Reference Figure 7 , Figure 7This is a flowchart illustrating the degraded allocation and mismatch data processing according to an embodiment of this disclosure. This embodiment will describe the complete process of processor 211 performing degraded allocation when the target free block queue is insufficient, and the mechanism for subsequently migrating and correcting temporary mismatch data through garbage collection operations.

[0100] In step S700, processor 211 obtains a write instruction. The write instruction includes the data to be written and a first-level identifier of the data to be written. Processor 211 queries the level table based on the first-level identifier, determines a second-level identifier, and selects the free block queue that matches the second-level identifier as the target free block queue.

[0101] In step S710, the processor 211 determines whether the target free block queue is insufficient. Specifically, the processor 211 checks the number of currently available free blocks in the target free block queue to determine whether it is sufficient to meet the writing requirements of the data to be written. When the number of available free blocks in the target free block queue is zero or lower than a preset minimum threshold, the processor 211 determines that the target free block queue is insufficient.

[0102] If the result of step S710 is negative (i.e., the target free block queue is sufficient), the process proceeds to step S720. In step S720, the processor 211 retrieves the first target free block from the target free block queue and writes the data to be written to the first target free block in the memory module 220 through the memory interface control circuit 213. This is the normal write path, where the data to be written is written to the free block that matches its first-level identifier.

[0103] When the judgment result of step S710 is yes (i.e., the target free block queue is insufficient), the process proceeds to step S730. In step S730, processor 211 obtains a second target free block from the free block queue adjacent to the target free block queue. Specifically, processor 211 locates the free block queue adjacent to the target free block queue according to the arrangement order of multiple free block queues in the grading table, and selects an available free block from the adjacent free block queue as the second target free block. The wear level corresponding to the adjacent free block queue is similar to the wear level of the target free block queue, thereby minimizing the impact of degraded allocation on the wear leveling strategy.

[0104] In step S740, the processor 211 writes the data to be written to the second target free block. Specifically, the processor 211 writes the data to be written to the second target free block in the memory module 220 through the memory interface control circuit 213 to continue the write operation. Through this demotion allocation mechanism, the processor 211 can maintain continuous write service even when the target free block queue is insufficient.

[0105] In step S750, the processor 211 marks the data to be written that has already been written into the second target free block as temporary mismatch data. For example... Figure 7 As shown in the dashed box of step S750, this marking operation is an internal management operation used to record data that failed to be written to the correct wear level free block due to downgrade allocation. Specifically, the processor 211 maintains a mismatch data tracking table in the buffer memory 214. The mismatch data tracking table records the storage location of the temporary mismatch data (i.e., the physical block address of the second target free block), the first level identifier that the temporary mismatch data should have matched, and the corresponding second level identifier. The marking information is used by subsequent migration correction operations.

[0106] In step S760, processor 211 determines whether to perform a garbage collection operation. For example... Figure 7 As shown, step S760 is a background operation. The processor 211 triggers garbage collection when the system is idle or when the available space of the memory module 220 is lower than a preset threshold. When the judgment result of step S760 is negative, the processor 211 enters a waiting state and will execute the judgment again when the garbage collection triggering condition is met later; when the judgment result of step S760 is positive, the process proceeds to step S770.

[0107] In step S770, processor 211 identifies temporary mismatch data and migrates it to a free block that matches the first-level identifier. Specifically, when performing garbage collection, processor 211 queries the mismatch data tracking table in buffer memory 214 to identify currently existing temporary mismatch data. For each piece of temporary mismatch data, processor 211 checks whether an available free block has been released in the target free block queue that it should have matched. If an available free block is available, processor 211 reads the temporary mismatch data from the second target free block and writes it to the newly released free block in the target free block queue. After the migration is complete, processor 211 removes the tag information of the temporary mismatch data from the mismatch data tracking table and marks the second target free block that originally stored the temporary mismatch data as reclaimable. The following utilizes... Figure 11 This describes the relevant details of the mismatch data tracking table.

[0108] Reference Figure 11 , Figure 11 This is a schematic diagram of a mismatch data tracking table T111 according to an embodiment of the present disclosure. In one embodiment, the processor 211 maintains the mismatch data tracking table T111 in a buffer memory 214 for recording information related to temporary mismatch data caused by downgrade allocation.

[0109] like Figure 11As shown, in one embodiment, each entry in the mismatch data tracking table T111 includes the following fields: physical block address of the temporary mismatch data, target second-level identifier, actual written second-level identifier, degradation depth, write timestamp, and migration priority. Specifically, the physical block address records the physical block address of the second target free block where the temporary mismatch data resides; the target second-level identifier records the second-level identifier that the temporary mismatch data should have matched; the actual written second-level identifier records the second-level identifier corresponding to the free block queue actually written due to degradation allocation; the degradation depth records the number of levels crossed between the target second-level identifier and the actual written second-level identifier; the write timestamp records the time when the degradation write operation occurred; and the migration priority records the priority of the processor 211 in performing migration correction on the temporary mismatch data during subsequent garbage collection operations.

[0110] In one embodiment, the processor 211 determines the migration priority based on the degradation depth. The degradation depth represents the degree to which temporary mismatched data deviates from the target free block queue it should have matched. A greater degradation depth indicates a larger deviation between the wear level and activity attribute of the free block containing the temporary mismatched data, resulting in a greater impact on the wear leveling strategy and thus a higher migration priority. Specifically, when the degradation depth is greater than or equal to a preset depth threshold, the processor 211 sets the migration priority of the temporary mismatched data to high; when the degradation depth is less than the preset depth threshold, the processor 211 sets the migration priority of the temporary mismatched data to medium or low. Figure 11 Taking entries 1 and 2 as examples, entry 1 records temporary mismatch data at physical block address PBA_0x03A7. The target second-level identifier for the temporary mismatch data is LV A, while the actual written second-level identifier is LV C. The degradation depth is 2, and the migration priority is high. Entry 2 records temporary mismatch data at physical block address PBA_0x0B12. The target second-level identifier for the temporary mismatch data is LV B, while the actual written second-level identifier is LV D. The degradation depth is 2, and the migration priority is high. Since the degradation depth of both entries 1 and 2 is 2, which is greater than or equal to the preset depth threshold (level 2 in this embodiment), the migration priority of both is set to high.

[0111] In one embodiment, when multiple entries have the same downgrade depth, the processor 211 further distinguishes the migration order based on the write timestamp. Entries with earlier write timestamps indicate that the temporary mismatched data has been in a mismatched state for a longer period, and the processor 211 prioritizes processing entries with earlier write timestamps when performing migration operations. For example, with entries 1 and 2, the write timestamp of entry 1 is 2025-01-15 14:28, and the write timestamp of entry 2 is 2025-01-15 14:32. Therefore, when both entries are to be migrated, the processor 211 prioritizes processing entry 1.

[0112] like Figure 11 As shown in entries 3 and 4, entry 3 records temporary mismatch data with physical block address PBA_0x1F05. The target second-level identifier of the temporary mismatch data is LV A, the actual written second-level identifier is LV B, the degradation depth is 1, and the migration priority is medium. Entrance 4 records temporary mismatch data with physical block address PBA_0x22C1. The target second-level identifier of the temporary mismatch data is LV C, the actual written second-level identifier is LV D, the degradation depth is 1, and the migration priority is low. The degradation depth of both entries 3 and 4 is 1, which is less than the preset depth threshold. The processor 211 further distinguishes them based on the write timestamp: the write timestamp of entry 3 is 2025-01-15 15:01, which is earlier than the write timestamp of entry 4 2025-01-15 15:10. Therefore, the migration priority of entry 3 is set to medium, and the migration priority of entry 4 is set to low.

[0113] In another embodiment, when performing garbage collection, the processor 211 determines the migration order based on the migration priority of each entry in the mismatch data tracking table T111. The processor 211 prioritizes migrating temporary mismatch data with high migration priority, then migrates temporary mismatch data with medium migration priority, and finally migrates temporary mismatch data with low migration priority. After the processor 211 completes the migration operation of the temporary mismatch data corresponding to a certain entry, the processor 211 deletes the entry from the mismatch data tracking table T111 and marks the second target free block that originally stored the temporary mismatch data as reclaimable.

[0114] It should be noted that, in another embodiment, the determination of migration priority is not limited to the two factors of degradation depth and write timestamp mentioned above. The processor 211 can also incorporate the level position of the target second-level identifier itself into the determination of migration priority. Specifically, when the target second-level identifier of the temporary mismatch data corresponds to a lower wear level (e.g., LVA), it indicates that the data to be written corresponding to the temporary mismatch data has high activity. If such data is stored for a long time in a non-target, higher-wear-level free block, its frequent update operations will continuously consume the resources of the non-target free block queue, and its impact on the wear leveling strategy is more prominent than that of mismatches involving moderately active data. Therefore, the processor 211 can set a higher migration priority for entries with lower wear levels corresponding to the target second-level identifier when the degradation depth is the same. Furthermore, the processor 211 can also incorporate other factors into the determination of migration priority, such as the current number of free blocks in the target free block queue, the current write load characteristics of the storage device 20, or the actual access frequency of the temporary mismatch data during the mismatch period. The processor 211 can determine the migration priority by combining one or more of the above factors according to the needs of the actual application scenario.

[0115] In a practical application scenario, the handling of virtual machine storage write requests by a solid-state drive controller is used as an example. In a virtual machine environment, multiple virtual machine instances may simultaneously generate a large number of hot data write requests, causing the corresponding low-wear free block queue A to be exhausted in a short period of time. When the processor 211 detects that the free block queue A is insufficient in step S710, the processor 211 performs a degraded allocation, obtains a second target free block from the free block queue B to continue serving the write requests, and marks these data as temporary mismatch data in step S750. As the virtual machine runs, the hot data previously written to the free block queue A gradually becomes invalid due to frequent updates. When the processor 211 performs garbage collection when the system load is low, the erased free blocks will be added back to the free block queue. At this time, the processor 211 identifies the temporary mismatch data stored in the free block queue B in step S770 and migrates it to the newly released free blocks in the free block queue A, thereby completing the mismatch correction and ensuring that the hot data is finally stored in a low-wear free block that matches its activity level.

[0116] Through steps S700 to S770, processor 211 can maintain the continuity of write service through a degraded allocation mechanism when the target free block queue is insufficient. Through the marking of temporary mismatched data and the background migration correction mechanism, it can ensure that mismatched data caused by degraded allocation can be migrated to the correct level of free blocks in the future, thereby avoiding long-term impact on the wear leveling strategy.

[0117] Reference Figure 8 In one embodiment, Figure 8 This is a schematic diagram illustrating dynamic hierarchical boundary adjustment according to an embodiment of the present disclosure. This embodiment will explain how the processor 211 monitors the number of free blocks in each of multiple free block queues, and how, when the number of free blocks in a particular free block queue is lower than a preset threshold, the multiple free block queues are re-divided by adjusting the hierarchical boundaries.

[0118] In this embodiment, the processor 211 continuously monitors the number of free blocks in each of the multiple free block queues in the background. Specifically, the processor 211 periodically checks the current status of each free block queue in the grading table, counts the number of available free blocks in each free block queue, and compares the number with a preset number threshold. The preset number threshold can be configured according to the capacity of the storage device 20, the expected write load characteristics, and the importance of each free block queue.

[0119] like Figure 8As shown in block BQ on the left, before adjustment, queue A has fewer free blocks, while queue B has more. The hierarchical boundary between queue A and queue B is defined by a boundary value X, which represents the erase / write count threshold used to distinguish between two adjacent free block queues. Specifically, free blocks with erase / write counts below the boundary value X are assigned to queue A, and free blocks with erase / write counts equal to or greater than the boundary value X are assigned to queue B. After the storage device 20 has been running for a period of time, because a large proportion of write requests sent by the host system 10 carry higher first-level identifiers (such as LV 5), the free blocks in queue A are frequently consumed, causing the number of free blocks in queue A to gradually decrease and fall below the preset threshold.

[0120] When processor 211 detects that the number of free blocks in a specific free block queue (queue A in this embodiment) is lower than a preset threshold, processor 211 triggers a dynamic hierarchical boundary adjustment mechanism. As shown by arrow A81, processor 211 performs a re-partitioning operation, adjusting the hierarchical boundary value between queue A and queue B, changing the boundary value from X to Y, where boundary value Y is greater than boundary value X. Through this adjustment, some free blocks that originally belonged to queue B (i.e., free blocks whose erase / write counts are between boundary value X and boundary value Y) are re-partitioned to queue A.

[0121] like Figure 8 As shown in block BQ' on the right, in the adjusted state, the number of free blocks in queue A increases, and free blocks in other free block queues (queue B) are reassigned to queue A. Specifically, processor 211 traverses the free blocks in queue B, removing free blocks with a write / erase count lower than the new boundary value Y from queue B and adding them to queue A. Through this reassignment operation, the number of available free blocks in queue A is replenished, thereby reducing the likelihood of subsequent write requests triggering a degradation allocation mechanism.

[0122] For example, suppose that before the adjustment, the write / erase count range for queue A is 0 to 100 times (i.e., boundary value X is 100), and the write / erase count range for queue B is 101 to 200 times. When processor 211 detects that the number of free blocks in queue A is lower than a preset threshold, processor 211 adjusts the boundary value from 100 to 150 (i.e., boundary value Y is 150). After the adjustment, the write / erase count range for queue A expands to 0 to 150 times, and the write / erase count range for queue B correspondingly shrinks to 151 to 200 times. Free blocks that originally belonged to queue B and had write / erase counts between 101 and 150 times are reassigned to queue A, thereby increasing the number of free blocks in queue A.

[0123] In another embodiment, when the processor 211 adjusts the hierarchical boundary of a specific free block queue, the hierarchical boundaries of other free block queues adjacent to that specific free block queue are also adaptively adjusted. Specifically, when the boundary value between queue A and queue B is adjusted from X to Y, the boundary value between queue B and queue C can also be adjusted accordingly to maintain the relative balance among the free block queues. This cascading adjustment mechanism can prevent other free block queues from having insufficient free blocks due to a single boundary adjustment.

[0124] In a real-world application scenario, let's take the handling of enterprise-level workloads by a solid-state drive (SSD) controller as an example. In a data center environment, SSDs may experience a surge in hot data write requests during specific periods, such as during peak daily business hours when the write volume of database transaction logs and cached data increases dramatically. Assume queue A initially contains 500 free blocks, with a preset threshold of 100. When continuous hot data writes during peak business hours cause the number of free blocks in queue A to drop to 80, processor 211 detects that queue A is below the preset threshold and triggers dynamic tiered boundary adjustment. Processor 211 increases the maximum number of erase / write cycles for queue A from 100 to 150, causing 120 free blocks in queue B with erase / write cycles between 101 and 150 to be reassigned to queue A. After the adjustment, the number of free blocks in queue A increases from 80 to 200, thus enabling it to continue serving subsequent hot data write requests without frequently triggering the degradation allocation mechanism. When the peak business period ends, if the number of free blocks in queue B falls below its preset threshold due to re-division, processor 211 can perform reverse adjustment to restore the boundary value from 150 to a lower value in order to rebalance the number of free blocks in each free block queue.

[0125] Through the aforementioned dynamic hierarchical boundary adjustment mechanism, the processor 211 can smoothly merge excess free blocks from a free block queue into a free block queue with insufficient demand based on real-time write load requirements. This maintains the availability of each free block queue under different workload conditions, reduces the trigger frequency of degraded allocation, and improves the overall write performance of the storage device 20.

[0126] Reference Figure 9 This embodiment will explain how the processor 211 adaptively selects the storage and recovery strategy of the level table based on the amount of data in the level table, so as to effectively manage the level table during the power-off and power-on processes of the storage device 20.

[0127] Before explaining the storage strategy, the generation mechanism of the grading table is first described. When the storage device 20 is initialized for the first time or when a grading table needs to be established, the processor 211 performs the following operations: The processor 211 sends a query request to the memory module 220 through the memory interface control circuit 213 to obtain the erase / write counts of each of the multiple free blocks in the memory module 220; the processor 211 sorts the multiple free blocks according to the erase / write counts; the processor 211 divides the multiple free blocks into multiple groups according to a preset method based on the sorting results, and maps the multiple groups into multiple free block queues; the processor 211 records the mapping relationship between the multiple free block queues and the corresponding second-grade identifiers, as well as the mapping relationship between the first-grade identifiers and the second-grade identifiers, in the grading table, and stores the grading table in the buffer memory 214. The amount of data in the grading table depends on the total number of free blocks in the memory module 220 and the number of free block queues. The more free blocks there are, the more physical block address entries the grading table needs to record, and the larger the amount of data in the grading table.

[0128] In step S910, the processor 211 determines the amount of data in the grading table. Specifically, the processor 211 calculates the storage space occupied by the current grading table. The storage space size is related to the number of free blocks recorded in the grading table, the number of free block queues, and the data structure of each mapping entry. The processor 211 compares the data amount with a preset data amount threshold to determine the storage strategy to be adopted subsequently. The preset data amount threshold can be configured according to the hardware characteristics of the storage device 20, for example, based on a comparison between the speed of reading data from the memory module 220 and the speed of the processor 211 performing the scan reconstruction operation.

[0129] In step S920, the processor 211 determines whether the amount of data in the level table exceeds a preset data amount threshold. This determination step is used to determine whether the level table needs to be persistently stored in the memory module 220 before the storage device 20 is powered off, and whether the level table should be restored by loading or rebuilding when the storage device 20 is powered on.

[0130] When the judgment result of step S920 is negative (i.e., the data volume of the grading table does not exceed the preset data volume threshold), the process proceeds to step S930. In step S930, the processor 211 adopts a scan-reconstruction strategy. Specifically, before the storage device 20 is powered off, the processor 211 does not store the grading table in the memory module 220; the grading table is only retained in the buffer memory 214 and is lost along with the contents of the buffer memory 214 when the power is off. When the storage device 20 is powered on, the processor 211 reconstructs the grading table by scanning the free blocks in the memory module 220. The reconstruction process includes: the processor 211 traverses all storage blocks in the memory module 220 and identifies the storage blocks that are currently in a free state; the processor 211 obtains the erase / write counts of each of the multiple free blocks; the processor 211 sorts the multiple free blocks according to the erase / write counts and assigns them to the corresponding free block queues; the processor 211 writes the reconstructed mapping relationship into the newly created grading table. This strategy is suitable for cases where the amount of rank table data is small, because when the number of free blocks is small, the time required for scanning and reconstruction may be shorter than the time required to read and load the rank table from memory module 220.

[0131] When the judgment result of step S920 is yes (i.e., the data volume of the level table exceeds the preset data volume threshold), the process proceeds to step S940. In step S940, the processor 211 adopts a storage loading strategy. Specifically, before the storage device 20 is powered off, the processor 211 stores the level table from the buffer memory 214 to the reserved management area of ​​the memory module 220. The reserved management area is a dedicated area in the memory module 220 for storing system management data and is isolated from the user data area. When the storage device 20 is powered on, the processor 211 loads the level table from the reserved management area of ​​the memory module 220 to the buffer memory 214, and normal memory management operations can then be resumed. This strategy is suitable for situations where the level table data volume is large, because when the number of free blocks is large, the time required to directly load the stored level table is usually shorter than the time required to rescan all free blocks and rebuild the level table.

[0132] In another embodiment, the processor 211 can dynamically evaluate changes in the data volume of the grading table during the operation of the storage device 20. When the data volume of the grading table exceeds a preset data volume threshold due to changes in the number of free blocks, the processor 211 switches the storage strategy accordingly. For example, when the storage device 20 is newly manufactured, it has a large number of free blocks, and the processor 211 adopts a storage loading strategy; as the storage device 20 is used, if a large number of free blocks are occupied, causing the data volume of the grading table to drop below the preset data volume threshold, the processor 211 can switch to a scan and rebuild strategy to simplify the processing flow before power failure.

[0133] For example, suppose memory module 220 contains 1000 storage blocks, of which approximately 200 are idle. In this case, the grading table needs to record the physical block addresses and queue information of the 200 idle blocks, resulting in a grading table size of approximately several kilobytes. Processor 211 determines that the data size does not exceed a preset data size threshold (assumed to be 64KB), and therefore employs a scan-reconstruction strategy. When storage device 20 is powered on, processor 211 scans the 1000 storage blocks to identify the 200 idle blocks and reconstructs the grading table, requiring approximately tens of milliseconds, a time overhead acceptable for consumer applications. Conversely, for a 4TB enterprise-grade solid-state drive, suppose memory module 220 contains 50,000 storage blocks, of which approximately 15,000 are idle. In this case, the grading table needs to record information about the 15,000 idle blocks, resulting in a grading table size of approximately several hundred kilobytes. Processor 211 determines that the data size exceeds a preset data size threshold, and therefore employs a storage loading strategy. Before the storage device 20 is powered off, the processor 211 stores the level table to the memory module 220; when the storage device 20 is powered on, the processor 211 loads the level table directly from the memory module 220, which takes about a few milliseconds to tens of milliseconds. Compared with the hundreds of milliseconds required to scan 50,000 storage blocks and rebuild the level table, the loading strategy can shorten the startup time of the storage device 20.

[0134] Through the above-mentioned adaptive storage strategy based on data volume, the processor 211 can select an appropriate storage and recovery method according to the actual size of the level table. When the level table data volume is small, unnecessary persistent storage overhead is avoided. When the level table data volume is large, the power-on recovery time is shortened by pre-storing. Thus, better startup efficiency can be achieved in storage devices 20 with different capacity specifications and usage states.

[0135] Reference Figure 10 This embodiment will describe the interaction timing between the host system 10, processor 211, buffer memory 214 and memory module 220 to demonstrate the execution flow of the memory management method.

[0136] In stage S1010, processor 211 receives a write instruction. As shown in step S1011, host system 10 sends a write instruction to processor 211. The write instruction includes the data to be written and a first-level identifier of the data to be written. The first-level identifier is determined by host system 10 based on the activity attribute of the data to be written and is encapsulated in an extended field of the write instruction. Processor 211 receives the write instruction through connection interface circuit 230 and parses the write instruction to extract the data to be written and the first-level identifier.

[0137] In stage S1020, processor 211 maintains multiple free block queues in the grading table. This stage includes multiple sub-steps to complete the grading table update operation. In step S1021, processor 211 sends a query request to memory module 220 through memory interface control circuit 213 to obtain the erase / write counts of each free block in memory module 220. In step S1022, memory module 220 responds to the query request and returns an erase / write count list to processor 211, which records the physical block address of each free block and its corresponding erase / write count. In step S1023, processor 211 sends a read request to buffer memory 214 to read the currently stored grading table. In step S1024, buffer memory 214 returns grading table data to processor 211, which includes the current status of multiple free block queues and their mapping relationships.

[0138] In step S1025, processor 211 internally performs a sorting operation, sorting multiple free blocks according to the erase / write counts obtained in step S1022. In step S1026, processor 211 internally performs a partitioning operation, dividing the multiple free blocks into corresponding free block queues according to the sorting results. Steps S1025 and S1026 are internal operations of processor 211 and do not involve data exchange with other components. In step S1027, processor 211 writes the updated multiple free block queues into buffer memory 214 to complete the maintenance operation of the level table.

[0139] In step S1030, processor 211 determines the second level identifier from the level table based on the first level identifier. In step S1031, processor 211 sends a query request to buffer memory 214 to query the second level identifier corresponding to the first level identifier. In step S1032, buffer memory 214 returns the second level identifier corresponding to the first level identifier to processor 211 according to the mapping relationship recorded in the level table.

[0140] In stage S1040, processor 211 selects the free block queue matching the second-level identifier as the target free block queue. In step S1041, processor 211 internally performs a matching operation, matching the corresponding free block queue among multiple free block queues in the level table based on the second-level identifier obtained in step S1032. In step S1042, processor 211 internally determines the target free block queue, which is the free block queue corresponding to the second-level identifier. Steps S1041 and S1042 are internal operations of processor 211; processor 211 directly locates the corresponding free block queue based on the data structure of the level table, without needing to exchange data with other components.

[0141] In stage S1050, processor 211 retrieves a first target free block from the target free block queue in the level table recorded in buffer memory 214. In step S1051, processor 211 sends a retrieval request to buffer memory 214 to retrieve the first target free block from the target free block queue. In step S1052, processor 211 selects an available free block from the target free block queue and returns the physical block address of the first target free block to processor 211. In one embodiment, processor 211 determines the suitable first target free block in the target free block queue based on a second level identifier. Specifically, in one embodiment, when the second level identifier corresponds to a low wear level, processor 211 selects the free block with the lowest write / erase count in the target free block queue as the first target free block, which is the suitable first target free block; when the second level identifier corresponds to a high wear level, processor 211 selects the free block with the highest write / erase count in the target free block queue as the first target free block, which is the suitable first target free block.

[0142] In step S1060, processor 211 writes the data to be written to the first target free block. In step S1061, processor 211 sends a write request to memory module 220 via memory interface control circuit 213, writing the data to be written to the first target free block acquired in step S1052. In step S1062, after completing the write operation, memory module 220 returns a write completion confirmation to processor 211. In step S1063, processor 211 returns a write operation completion response to host system 10 via connection interface circuit 230, notifying host system 10 that the write instruction has been successfully executed.

[0143] Through the above timing process, the processor 211 can coordinate the interactive operations between the host system 10, the buffer memory 214 and the memory module 220 to complete the complete memory management process from obtaining the write instruction to writing the data.

[0144] It is worth mentioning that, in one embodiment, the processor 211 continuously monitors the actual access behavior of written data in the background and performs a re-matching operation when a change in data activity is detected. Specifically, the processor 211 maintains an access behavior tracking table in the buffer memory 214, which records the number of reads, the most recent read timestamp, and the read frequency of each storage block within a preset monitoring period. The processor 211 periodically analyzes the access behavior tracking table and evaluates the current data level (activity) of each storage block based on its actual read frequency.

[0145] In this embodiment, the processor 211 uses read frequency as an auxiliary basis for activity assessment. Although wear and tear on NAND flash memory mainly stems from write operations, the processor 211 cannot directly observe the "write frequency" of static data already stored in physical blocks (because once a write occurs, the data is updated to a new location). Therefore, read frequency becomes an effective indicator for assessing whether data is still in an "active" state. Generally, if data is frequently read, it indicates that it is still frequently used by the host system 10, and it is reasonable to maintain it in a low-wear level free block (or high-performance area); conversely, if data has not been read for a long time, it indicates that it may have become cold data (archived data).

[0146] When the processor 211 detects that the difference between the current activity level of data in a storage block and the wear level of the storage block exceeds a preset level difference threshold, the processor 211 marks the storage block as an activity mismatch block. The preset level difference threshold can be configured to level 2 or level 3 to avoid over-responding to slight activity fluctuations, thereby preventing unnecessary data migration.

[0147] In another embodiment, when performing garbage collection, the processor 211 prioritizes processing storage blocks marked as mismatched activity levels. Specifically, when the processor 211 performs garbage collection on mismatched activity levels, it reads the valid data in the mismatched block and redetermines the target second-level identifier based on the current activity level of the valid data. The valid data is then written to a free block that matches its current activity level. Through this mechanism, data that was originally marked as high-level (high-activity) but has actually become low-level (low-activity) can be migrated to high-wear-level free blocks, thereby freeing up valuable low-wear-level free block resources that it previously occupied.

[0148] In another embodiment, processor 211 employs different rematching strategies based on the direction of the activity change. When data moves from a high priority to a low priority (becoming cold), since the data is already stored in a low-wear free block and subsequent access frequency decreases, processor 211 can use a delayed migration strategy, only migrating the data incidentally during subsequent garbage collection operations to avoid additional write amplification. When data moves from a low priority to a high priority (becoming hot), processor 211 can decide whether to use an active migration strategy based on system load, migrating the data to a low-wear free block when the system is idle to match its current higher access demand.

[0149] In another embodiment, the processor 211 can combine access statistics at the logical block address level to assist in activity assessment. Specifically, the processor 211 maintains a logical block address access frequency table in the buffer memory 214. The access frequency table records the cumulative number of reads and writes for each logical block address segment within a preset monitoring period. When the processor 211 receives a write request for a specific logical block address, the processor 211 can query the access frequency table, predict the activity of the data to be written based on the historical access patterns of that logical block address segment, and adjust the determination result of the first-level identifier accordingly. This mechanism can serve as a supplement or correction basis for the first-level identifier provided by the host system 10.

[0150] In a practical application scenario, a solid-state drive (SSD) storage enterprise document management system is used as an example. Assume a project document is frequently viewed and edited during project execution. The host system 10 marks it as high-level data and writes it to a low-wear free block. After the project ends, the project document enters an archived state and is no longer viewed or modified. The processor 211 detects through an access behavior tracking table that the project document has been read zero times in the past 30 days, determining that its current activity level has dropped to low. The processor 211 marks the storage block containing the project document as an activity mismatch block and migrates the project document to a high-wear-level free block during subsequent garbage collection, thereby freeing up the low-wear free block for subsequent high-activity data.

[0151] Through the aforementioned dynamic monitoring and rematching mechanism for data activity, the processor 211 can continuously optimize the data placement strategy throughout the entire lifecycle of the storage device 20, ensuring that the actual activity of the data matches the wear level of the storage block it resides in, thereby maintaining the long-term effectiveness of the reverse matching strategy disclosed herein.

[0152] It is worth mentioning that, in one embodiment, when the processor 211 determines the first suitable target free block in the target free block queue based on the second-level identifier, in addition to considering the number of erase / write operations, it also comprehensively considers multiple factors affecting the reliability and performance of the storage block. Specifically, the processor 211 maintains a free block attribute table in the buffer memory 214, which records the number of erase / write operations, bad block proximity, cumulative read interference count, and data retention characteristic indicators of each free block.

[0153] Bad block proximity indicates the physical distance between a free block and a known bad block. Due to the potential correlation between adjacent memory blocks in NAND flash memory due to process defects, the processor 211 can prioritize free blocks with lower bad block proximity when selecting the first target free block to reduce the risk of generating new bad blocks later. Accumulated read interference count indicates the amount of charge interference accumulated in a free block due to read operations from adjacent memory blocks. When the accumulated read interference count approaches a preset interference threshold, the processor 211 can prioritize selecting that free block to reset its interference count through a write operation. Data retention characteristic indicates the ability of a free block to maintain data integrity in a power-off state. The processor 211 can select a free block with matching data retention characteristics based on the expected storage duration of the data to be written.

[0154] Processor 211 can use a weighted scoring mechanism to integrate the above-mentioned multiple factors, calculate the comprehensive fit score of each free block according to the weight of each factor, and select the free block with the highest comprehensive fit score as the first target free block. Through this multi-factor selection strategy, processor 211 can meet the wear leveling target while taking into account the reliability and data integrity of the storage blocks.

[0155] In one embodiment, the processor 211 maintains a mismatch data tracking table in the buffer memory 214 to record information related to temporary mismatch data generated due to downgrade allocation. Each entry in the mismatch data tracking table includes the following fields: the physical block address where the temporary mismatch data is located, the second-level identifier that the temporary mismatch data should have matched, the second-level identifier that was actually written, the downgrade depth, the write timestamp, and the migration priority. The processor 211 identifies and migrates the temporary mismatch data in subsequent garbage collection operations based on the field information.

[0156] The mismatch data tracking table has a preset storage capacity limit, which can be configured based on the available space in the buffer memory 214. When the number of entries in the mismatch data tracking table approaches the storage capacity limit, the processor 211 executes an overflow handling strategy. The overflow handling strategy may include: the processor 211 triggering an emergency migration operation, prioritizing the migration of temporary mismatch data with larger degradation depths or earlier write times to release tracking table entries; or, the processor 211 merging multiple temporary mismatch data entries located in the same storage block to reduce the space occupied by the tracking table.

[0157] During garbage collection, processor 211 queries the mismatch data tracking table to identify whether the storage block to be reclaimed contains temporary mismatch data. If temporary mismatch data is found, processor 211 redetermines the write location based on the second-level identifier of the temporary mismatch data, migrates the temporary mismatch data to a free block of the correct level, and deletes the corresponding entry from the mismatch data tracking table after the migration is complete. Through this data structure and management mechanism, processor 211 can effectively track and correct data mismatches caused by degraded allocation.

[0158] In one embodiment, when the host system 10 does not provide a first-level identifier or the provided first-level identifier value is 0, the processor 211 automatically infers the activity attribute of the data to be written based on the mode characteristics of the write instruction. Specifically, the processor 211 analyzes multiple characteristic parameters of the write instruction, including the size of the data to be written, the write mode (sequential write or random write), the logical block address distribution, and the time interval of the write request, and calculates the inferred activity level of the data to be written based on the characteristic parameters.

[0159] The processor 211 maintains a write pattern analysis module in the buffer memory 214, which records statistical information of recent write requests. When the processor 211 receives a write command, it extracts the characteristic parameters of the write command and inputs them into the write pattern analysis module. The write pattern analysis module calculates the inferred activity level according to preset inference rules. For example, if the write data size is less than a preset small data threshold (e.g., 4KB) and the write mode is random write, the processor 211 infers the data to be written as highly active data; if the write data size is greater than a preset large data threshold (e.g., 128KB) and the write mode is sequential write, the processor 211 infers the data to be written as low-activity data.

[0160] In another embodiment, the processor 211 can perform activity inference by combining historical access records of logical block addresses. The processor 211 maintains a logical block address heat table in the buffer memory 214, which records the cumulative number of accesses for each logical block address segment within a preset time window. When the processor 211 receives a write command, it queries the heat table to obtain the historical heat value of the target logical block address segment and combines the historical heat value with write mode characteristics to calculate the overall inferred activity level of the data to be written. Through this mechanism, the storage device 20 can autonomously execute the memory management method of this disclosure even when the host system 10 does not provide activity information.

[0161] In one embodiment, the processor 211 employs different degrading allocation strategies based on the activity attribute indicated by the first-level identifier of the data to be written, in order to reduce the negative impact of degrading allocation on wear leveling. Specifically, when the data to be written is highly active data and the target free block queue is insufficient, the processor 211 prioritizes degrading allocation towards lower wear levels; when the data to be written is inactive data and the target free block queue is insufficient, the processor 211 prioritizes degrading allocation towards higher wear levels.

[0162] Taking the degraded allocation of highly active data as an example, assuming the first level identifier of the data to be written is LV5, and the corresponding target free block queue is free block queue A (lowest wear level), when free block queue A is insufficient, processor 211 checks whether there are available free blocks in free block queue B (second lowest wear level). If free block queue B is also insufficient, it continues to check free block queue C. This directional strategy ensures that even in the case of degraded allocation, highly active data is still written to free blocks with relatively low wear, so that its subsequent frequent update operations can continue to consume the remaining lifetime of low-wear free blocks.

[0163] Taking the degraded allocation of low-activity data as an example, assuming the first level identifier of the data to be written is LV1, and the corresponding target free block queue is free block queue E (highest wear level), when free block queue E is insufficient, processor 211 checks whether there are available free blocks in free block queue D (second highest wear level). If free block queue D is also insufficient, it continues to check free block queue C. This directional strategy ensures that even in the case of degraded allocation, low-activity data is still written to free blocks with relatively high wear, avoiding low-activity data occupying low-wear free blocks and hindering the normal allocation of high-activity data. Through this differentiated degraded allocation directional strategy, processor 211 can maintain the basic principles of the disclosed reverse matching strategy in degraded allocation scenarios.

[0164] In another embodiment, if the memory module 220 contains different types of storage medium regions, such as single-cell (SLC) mode regions and triple-cell (TLC) mode regions, the processor 211 also establishes independent level tables for these two types of regions. Since the durability (P / E cycle limit) of SLC mode is significantly higher than that of TLC mode (e.g., 100,000 cycles for SLC and 3,000 cycles for TLC), not only are the wear level classification standards different, but the required level classification granularity (i.e., the number of second-level identifiers) can also be different.

[0165] Specifically, to achieve finer wear management over the longer lifespan of the SLC, the processor 211 can configure a larger number of second-level identifiers (e.g., divided into 5 wear levels) for the SLC region, thereby providing higher-resolution free block queue selection. Conversely, for the shorter-lifespan TLC region, the processor 211 can configure a smaller number of second-level identifiers (e.g., divided into 3 wear levels). When data is decided to be written to the SLC region, the processor 211 queries the SLC-specific level table with higher granularity to achieve precise matching between extremely hot data and free blocks with minor wear differences; when data is written to the TLC region, it queries the TLC-specific level table. This differentiated configuration ensures that, in a hybrid media architecture, the reverse matching strategy of this disclosure can adaptively adjust the management granularity according to the physical characteristics of the media, maximizing the utilization efficiency of different media.

[0166] It should be noted that the above embodiments describe specific technical solutions for the memory management method of this disclosure, including a degradation allocation mechanism when the target free block queue is insufficient, a dynamic hierarchical boundary adjustment mechanism, a hierarchical table storage strategy, and a hierarchical table maintenance and update process. These technical solutions involve multiple preset values ​​and triggering conditions that can be flexibly configured according to actual application scenarios. The different configuration methods for these preset values ​​and triggering conditions will be described below.

[0167] In one embodiment, the processor 211 determines that the target free block queue is insufficient when the number of available free blocks in the target free block queue is zero. In another embodiment, the processor 211 determines that the target free block queue is insufficient when the number of available free blocks in the target free block queue is lower than a preset minimum number, which can be configured to 3, 5, or other fixed values. In yet another embodiment, the processor 211 determines that the target free block queue is insufficient when the number of available free blocks in the target free block queue is lower than a preset percentage of the initial capacity of the target free block queue, which can be configured to 10%, 15%, or 20%.

[0168] In one embodiment, the preset threshold for triggering dynamic hierarchical boundary adjustments by the processor 211 is a fixed value, for example, adjusting when the number of free blocks in a specific free block queue is less than 50. In another embodiment, the preset threshold is a percentage of the initial capacity of each free block queue, for example, adjusting when the number of free blocks is less than 20% of the initial capacity. In yet another embodiment, the processor 211 dynamically adjusts the preset threshold based on the current write load, increasing the threshold to trigger adjustments earlier when a high-frequency write request is detected, and decreasing the threshold to reduce the adjustment frequency when a low-frequency write request is detected.

[0169] In one embodiment, the processor 211 configures a preset data volume threshold according to the capacity specification of the buffer memory 214. For example, when the total capacity of the buffer memory 214 is 1MB, the preset data volume threshold is set to 64KB. In another embodiment, the processor 211 configures a preset data volume threshold according to the boot time requirements of the storage device 20. When the boot time requirements are strict, the threshold is lowered to reduce the level table loading time at power-on; when the boot time requirements are lenient, the threshold is raised to reduce storage operations before power-off.

[0170] In one embodiment, the processor 211 performs a level table maintenance operation each time a write instruction is fetched, to ensure that the free block queue information in the level table remains synchronized with the actual state of the memory module 220. In another embodiment, the processor 211 performs the level table maintenance operation periodically, for example, once every 1000 write operations or every 60 seconds. In yet another embodiment, the processor 211 performs the level table maintenance operation when it detects that the change in the number of free blocks exceeds a preset change threshold, for example, when the change in the number of free blocks in any free block queue exceeds 10%, maintenance is triggered.

[0171] This disclosure also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the various steps of the memory management method described above. The computer-readable storage medium can be a non-transitory computer-readable storage medium, such as a read-only memory, random access memory, optical disc read-only memory, magnetic tape, flash memory, hard disk, or solid-state drive. The computer program includes computer-readable instructions, which, when executed by the processor 211, cause the memory controller 210 to perform the memory management method described in the above embodiments.

[0172] In summary, the memory management method and memory controller provided in this disclosure achieve precise matching between data activity and physical storage wear by introducing a level-based mapping mechanism in the data write path. Specifically, the memory controller can determine the corresponding second-level identifier internally by looking up a table based on the first-level identifier provided by the host, and then select a specific free block queue for writing. This reverse matching mechanism allows the system to proactively guide highly active data to physical blocks with lower write cycles, naturally accelerating the write cycle growth of those physical blocks by leveraging the frequent updates of hot data, allowing them to catch up with high-wear physical blocks. Through this proactive management, this disclosure enables the wear levels of various physical blocks within the memory module to become more consistent over long-term operation, thereby fundamentally reducing passive data movement operations performed to balance wear, effectively reducing write amplification of the storage device, and extending the lifespan of the flash memory while improving overall write performance.

[0173] Furthermore, by employing a sorting and grouping initialization strategy (such as equal distribution or proportional allocation) based on the number of erase / write cycles for free blocks, this disclosure ensures that the free block queues corresponding to each wear level have sufficient available resources in the initial state or during system operation, thereby guaranteeing the continuity and stability of the reverse matching strategy execution. For specific situations where the target free block queue is insufficient, the degradation allocation mechanism provided in this disclosure allows free blocks to be obtained from queues of adjacent wear levels, thereby eliminating the risk of write blocking and ensuring business continuity. Combined with the marking of temporary mismatched data and the migration correction mechanism during background garbage collection, the system can meet immediate write requirements while achieving delayed correction of data placement locations, ensuring that the wear leveling strategy under long-term operation is not affected by short-term resource fluctuations.

[0174] Furthermore, the dynamic grading boundary adjustment mechanism introduced in this disclosure can monitor the number of free blocks in each queue in real time and dynamically adjust the erase / write cycle boundary value for grading wear levels according to actual load requirements. This mechanism allows free blocks in the surplus queue to be smoothly reassigned to the shortage queue, thereby improving the system's adaptability to different workload modes. Finally, the adaptive storage strategy based on the grading table can shorten power-on loading time by pre-storing when the grading table data volume is large, and reduce storage overhead before power failure by scanning and rebuilding when the data volume is small, thereby optimizing the startup efficiency and resource utilization of the storage device under different capacity specifications and usage conditions.

[0175] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method applied to a storage device configured with a memory controller and a memory module, the method comprising: Obtain a write instruction, the write instruction including the data to be written and a first-level identifier of the data to be written; Maintain multiple free block queues for the maintenance grading table; Based on the first level identifier, a second level identifier is determined from the level table; The free block queue that matches the second level identifier is used as the target free block queue. The first target free block is obtained from the target free block queue, and the data to be written is written to the first target free block.

2. The memory management method according to claim 1, characterized in that, The steps for the multiple free block queues in the maintenance level table include: Obtain the erase / write counts of each of the multiple free blocks in the memory module, and sort the multiple free blocks accordingly; and Based on the sorting results, the multiple free blocks are respectively divided into the corresponding multiple free block queues.

3. The memory management method according to claim 2, characterized in that, The step of dividing the plurality of free blocks into corresponding queues based on the sorting result includes: The sorted free blocks are divided into multiple groups according to a preset method; and The plurality of groups are mapped to the plurality of free block queues respectively, so that each free block queue has available free blocks in the initial state.

4. The memory management method according to claim 1, characterized in that, The multiple free block queues each correspond to a different second-level identifier.

5. The memory management method according to claim 4, characterized in that, The plurality of free block queues correspond to different wear levels, and the second level identifier corresponds to the wear level. The step of determining the second level identifier from the level table based on the first level identifier includes: The second level identifier is determined based on the mapping relationship between the first level identifier and the second level identifier, wherein the higher the data activity indicated by the first level identifier, the lower the wear level corresponding to the mapped second level identifier.

6. The memory management method according to claim 1, characterized in that, The step of obtaining the first target free block from the target free block queue includes: Based on the second level identifier, the first target free block that is suitable in the target free block queue is determined.

7. The memory management method according to claim 1, characterized in that, The method further includes: When the target free block queue is insufficient, a second target free block is obtained from the adjacent free block queue to continue writing the data to be written.

8. The memory management method according to claim 7, characterized in that, The method further includes: The data to be written that has already been written into the second target free block is marked as temporary mismatch data; When performing a garbage collection operation, the temporary mismatch data is identified and migrated to an idle block that matches the first level identifier.

9. The memory management method according to claim 1, characterized in that, The method further includes: Monitor the number of free blocks in each of the multiple free block queues; and When the number of free blocks in a specific free block queue is lower than a preset threshold, the multiple free block queues are re-divided so that free blocks in other free block queues are re-divided into the specific free block queue, thereby increasing the number of free blocks in the specific free block queue.

10. The memory management method according to claim 1, characterized in that, Also includes: Determine whether the data volume of the grade table exceeds a preset data volume threshold; When the data volume of the level table exceeds the preset data volume threshold, the level table is stored in the memory module before the storage device is powered off, and the level table is loaded from the memory module when the storage device is powered on. as well as When the amount of data in the grading table does not exceed the preset data amount threshold, the grading table is reconstructed by scanning the free blocks in the memory module when the storage device is powered on.

11. A memory controller, suitable for a storage device configured with a memory module, comprising: A memory interface control circuit is used to electrically connect to the memory module; as well as A processor, electrically connected to the memory interface control circuit, wherein the processor is configured to: Obtain a write instruction, the write instruction including the data to be written and a first-level identifier of the data to be written; Maintain multiple free block queues for the maintenance grading table; Based on the first level identifier, a second level identifier is determined from the level table; The free block queue that matches the second level identifier is used as the target free block queue. The first target free block is obtained from the target free block queue, and the data to be written is written to the first target free block.

12. The memory controller according to claim 11, characterized in that, The processor is also configured to: Obtain the erase / write counts of each of the multiple free blocks in the memory module, and sort the multiple free blocks accordingly; and Based on the sorting results, the multiple free blocks are respectively divided into the corresponding multiple free block queues.

13. The memory controller according to claim 12, characterized in that, The processor is also configured to: The sorted free blocks are divided into multiple groups according to a preset method; and The plurality of groups are mapped to the plurality of free block queues respectively, so that each free block queue has available free blocks in the initial state.

14. The memory controller according to claim 11, characterized in that, The multiple free block queues each correspond to a different second-level identifier.

15. The memory controller according to claim 14, characterized in that, The plurality of free block queues correspond to different wear levels, the second level identifier corresponds to the wear level, and the processor is further configured to: The second level identifier is determined based on the mapping relationship between the first level identifier and the second level identifier, wherein the higher the data activity indicated by the first level identifier, the lower the wear level corresponding to the mapped second level identifier.

16. The memory controller according to claim 11, characterized in that, The processor is also configured to: Based on the second level identifier, the first target free block that is suitable in the target free block queue is determined.

17. The memory controller according to claim 11, characterized in that, The processor is also configured to: When the target free block queue is insufficient, a second target free block is obtained from the adjacent free block queue to continue writing the data to be written.

18. The memory controller according to claim 17, characterized in that, The processor is also configured to: The data to be written that has already been written into the second target free block is marked as temporary mismatch data; When performing a garbage collection operation, the temporary mismatch data is identified and migrated to an idle block that matches the first level identifier.

19. The memory controller according to claim 11, characterized in that, The processor is also configured to: Monitor the number of free blocks in each of the multiple free block queues; and When the number of free blocks in a specific free block queue is lower than a preset threshold, the multiple free block queues are re-divided so that free blocks in other free block queues are re-divided into the specific free block queue, thereby increasing the number of free blocks in the specific free block queue.

20. The memory controller according to claim 11, characterized in that, The processor is also configured to: Determine whether the data volume of the grade table exceeds a preset data volume threshold; When the data volume of the level table exceeds the preset data volume threshold, the level table is stored in the memory module before the storage device is powered off, and the level table is loaded from the memory module when the storage device is powered on. as well as When the amount of data in the grading table does not exceed the preset data amount threshold, the grading table is reconstructed by scanning the free blocks in the memory module when the storage device is powered on.

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