Encoding method of backplate, identification method of backplate, and server system

Abstract

The present invention relates to a backplane identification technique in a server system, and more particularly to a backplane encoding method for a server system. The server system includes a motherboard and a backplane. The motherboard includes a first connector. The backplane includes a second connector and a logic circuit. The first connector is coupled to the second connector. The encoding method includes: encoding the backplane through a plurality of pins of the first connector to obtain an identification code corresponding to the backplane; storing the identification code in a firmware of the logic circuit; and storing the identification code in a BIOS of the server system. The present invention further provides a backplane identification method and a server system.

Description

Technical Field

[0001] This invention relates to backplane identification technology in server systems, and more particularly to a method for encoding the backplane. Background Technology

[0002] In existing technology, the indicator lights for SSDs are controlled by software, and the relevant hardware includes a backplane, a motherboard, and the connecting cables between the motherboard and the backplane. The backplane is mainly used to connect the SSDs, and the number of SSDs that can be installed depends on the backplane design. Some SSDs connect their indicator light control signal lines to a Complex Programmable Logic Device (CPLD) on the backplane. In server systems, the motherboard contains at least one Central Processing Unit (CPU), which provides the sequential signals used to control the indicator lights.

[0003] When the server system boots up and detects the status of the SSDs mounted on the backplane, the CPU transmits a sequence of signals to the CPLD on the backplane to control the indicator lights. The CPLD then converts these sequence of signals into parallel signals and transmits them to the SSDs to control the indicator light display. Furthermore, each backplane requires its own independent CPLD firmware to operate.

[0004] As system complexity increases, such as with the number of backplanes or CPUs, the number of connecting cables also increases. This can make what seems like a simple operation potentially problematic, such as incorrect system component installation leading to incorrect indicator displays. To correctly identify the backplane configuration and the number of SSDs, the system typically restricts different backplane and SSD combinations to be installed in specific locations and slots, and the CPU needs to address each connected SSD to control the indicator lights.

[0005] However, when encountering a backplane combination that does not conform to the system connection cable definition, the sequence signals provided by the CPU to control the LEDs may be incorrect, causing the system to fail to recognize them correctly, and thus preventing the system from correctly controlling the LEDs of the SSD. Summary of the Invention

[0006] In some embodiments, a backplane encoding method is applicable to a server system. The server system includes a motherboard and at least one backplane. The motherboard includes at least one first connector. Each of the at least one backplane includes a second connector and a logic circuit. Each of the at least one first connector is coupled to each of the at least one second connector. The encoding method includes: encoding each of the at least one backplane through a plurality of pins of each of the at least one first connector to obtain an identification code corresponding to each of the at least one backplane; storing each of the at least one identification code in firmware of each of the at least one logic circuit; and storing each of the at least one identification code in a BIOS of the server system.

[0007] In some embodiments, the pins are redundant pins of each of the at least one first connector.

[0008] In some embodiments, the number of pins is two. The identification code is two bits long.

[0009] In some embodiments, the at least one first connector and the at least one second connector are MCIO connectors.

[0010] In some embodiments, the at least one first connector includes a third connector and a fourth connector. The third connector is an MCIO connector. The fourth connector is a disk array card. The second connector coupled to the third connector is an MCIO connector, and the second connector coupled to the fourth connector is a SAS connector.

[0011] In some embodiments, the firmware of each of the at least one logic circuit stores the identification code of all the at least one backplane.

[0012] In some embodiments, a backplane identification method is applicable to a server system. The server system includes a motherboard and at least one backplane. The motherboard includes a processing circuit and at least one first connector. The processing circuit is coupled to the at least one first connector. Each of the at least one backplane includes a second connector, a logic circuit, a plurality of hard disk connectors, and a plurality of hard disks. The logic circuit is coupled to the second connector, the hard disk connectors are coupled to the logic circuit, and each hard disk is coupled to its respective hard disk connector. Each of the at least one first connector is coupled to its respective at least one second connector. The logic circuit includes firmware. The identification method includes: the processing circuit of the motherboard providing a first signal to the logic circuit of each of the at least one backplane; the logic circuit of each of the at least one backplane providing a second signal to the hard disks of each of the at least one backplane based on the first signal and an identification code stored in the firmware of the logic circuit of each of the at least one backplane; and the hard disks of each of the at least one backplane controlling their indicator lights based on the second signal.

[0013] In some embodiments, the processing circuit provides the first signal to each of the at least one logic circuit based on the identification code stored in a BIOS of the server system.

[0014] In some embodiments, the processing circuitry further includes a VPP port. The processing circuitry is coupled to the at least one first connector via the VPP port.

[0015] In some embodiments, a backplane identification method is applicable to a server system. The server system includes a motherboard and at least one backplane. The motherboard includes a processing circuit and at least one first connector. The processing circuit is coupled to the at least one first connector. Each of the at least one backplane includes a second connector, a logic circuit, a plurality of hard disk connectors, and a plurality of hard disks. The logic circuit is coupled to the second connector, the hard disk connectors are coupled to the logic circuit, and each hard disk is coupled to its respective hard disk connector. Each of the at least one first connector is coupled to its respective at least one second connector. The logic circuit includes firmware. The identification method includes: encoding each of the at least one backplane through multiple pins of each of the at least one first connector to obtain an identification code corresponding to each of the at least one backplane; storing each of the at least one identification code in the firmware of each of the at least one logic circuit; storing each of the at least one identification code in a BIOS of the server system; the processing circuit of the motherboard providing a first signal to the logic circuit of each of the at least one backplane; the logic circuit of each of the at least one backplane providing a second signal to the hard drives of each of the at least one backplane based on the first signal and the identification code stored in the firmware of the logic circuit of each of the at least one backplane; and the hard drives of each of the at least one backplane controlling their indicator lights based on the second signal.

[0016] The following detailed description of the features and advantages of the present invention is sufficient to enable anyone skilled in the art to understand the technical content of the present invention and implement it accordingly. Based on the content disclosed in this specification, the claims and the accompanying drawings, anyone skilled in the art can easily understand the relevant objectives and advantages of the present invention. Attached Figure Description

[0017] Other features and effects of the present invention will be clearly presented in the embodiments with reference to the accompanying drawings, wherein:

[0018] Figure 1 This is a schematic diagram of one embodiment of a server system;

[0019] Figure 2 A flowchart illustrating one embodiment of a backplane encoding method;

[0020] Figure 3 This is a schematic diagram of one embodiment of step S01;

[0021] Figure 4 A flowchart illustrating one embodiment of a method for identifying a backplate;

[0022] Figure 5 This is a schematic diagram of another embodiment of the server system;

[0023] Figure 6 A flowchart of another embodiment of the backplane encoding method; and

[0024] Figure 7 This is a flowchart of another embodiment of the backplate identification method. Detailed Implementation

[0025] Before the invention is described in detail, it should be noted that similar elements are represented by the same numbers in the following description.

[0026] Figure 1 This is a schematic diagram of one embodiment of server system 1. Please refer to [link / reference]. Figure 1 Server system 1 includes a motherboard 10 and a backplane 11. The motherboard 10 includes processing circuitry 101 and a first connector 102. The processing circuitry 101 includes a VPP port 1011. The first connector 102 is coupled to the VPP port 1011. The backplane 11 includes a second connector 111, logic circuitry 112, multiple hard disk connectors 113, and multiple hard disks 114. The second connector 111 is coupled to the first connector 102. The logic circuitry 112 is coupled to the second connector 111. The multiple hard disk connectors 113 are coupled to the logic circuitry 112. Each of the multiple hard disks 114 is individually coupled to its respective hard disk connector 113.

[0027] In some embodiments, the processing circuit 101 may be, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a microcontroller (MCU), a complex programmable logic device (CPLD), an embedded processor, a network processor, a coprocessor, and other processing units suitable for server systems or electronic devices.

[0028] In some embodiments, the first connector 102 and the second connector 111 may be, but are not limited to, multichannel I / O connectors (MCIO), serial Attached SCSI connectors (SAS), RAID cards, serial advanced technology accessory connectors (SATA), small computer system interface connectors (SCSI), PCIe connectors, M.2 connectors, and other types of connectors suitable for server systems or electronic devices.

[0029] In some embodiments, the second connector 111 is a second connector 111 of a corresponding type to the first connector 102 to which it is connected. For example, if the first connector 102 to which the second connector 111 is connected is an MCIO connector, then the second connector 111 is an MCIO connector. As another example, if the first connector 102 to which the second connector 111 is connected is a SAS connector or a disk array card, then the hard disk connector 113 is a SAS connector.

[0030] In some embodiments, logic circuit 112 may be, but is not limited to, combinational logic circuit, sequential logic circuit, programmable logic device (PLD), field-programmable gate array (FPGA), complex programmable logic device (CPLD), application application-specific integrated circuit (ASIC), and other logic circuits suitable for server systems or electronic devices.

[0031] In some embodiments, the hard disk 114 may be, but is not limited to, a solid-state drive (SSD), a hard disk drive (HDD), a hybrid hard disk drive (SSHD), a small computer system interface hard disk drive (SCSI HDD), a serial advanced technology accessory hard disk drive (SATA HDD), a serial attached SCSI hard disk drive (SAS HDD), a non-volatile memory performance interface hard disk drive (NVMe SSD), a fiber channel hard disk drive (FC HDD), and other storage devices suitable for server systems or electronic devices.

[0032] In some embodiments, the hard drive connector 113 corresponds to different types of hard drives 114 it connects to, and its backplane also corresponds to different identification codes, thus the data format transmitted by the hard drive connector 113 is also different. For example, if the hard drive 114 connected to the hard drive connector 113 is an NVMe SSD, then the hard drive connector 113 transmits data in an NVMe format, such as the Inter-Integrated Circuit (I2C) communication protocol format. As another example, if the hard drive 114 connected to the hard drive connector 113 is a SAS HDD, then the hard drive connector 113 transmits data in a SAS format, such as the Server General Purpose Input / output (SGPIO) format.

[0033] In some embodiments, the VPP port 1011 and the first connector 102, the first connector 102 and the second connector 111, and the second connector 111 and the logic circuit 112 may be, but are not limited to, connected via a system management bus (SMBus), a serial interface device bus (SPI), a high-speed data transmission line, a PCIe bus, or an I / O bus. 2 C-bus, SATA cables, SAS cables, multi-channel I / O cables (MCIO), disk array card cables, and other transmission lines or buses suitable for server systems or electronic devices are interconnected.

[0034] Figure 2 This is a flowchart illustrating one embodiment of the encoding method for the backplane 11. Please refer to... Figure 1 and Figure 2First, the processing circuit 101 encodes the backplane 11 through multiple pins of the first connector 102 to obtain an identification code corresponding to the backplane 11 (step S01). Next, the processing circuit 101 transmits the identification code to the second connector 111 through the first connector 102. When the logic circuit 112 receives the identification code corresponding to the backplane 11 through the second connector 111, the logic circuit 112 stores the identification code in its firmware (step S02). After obtaining the identification code corresponding to the backplane 11, the processing circuit 101 stores the identification code in the BIOS of the server system 1 (step S03).

[0035] In some embodiments, during step S01, the processing circuit 101 obtains the identification code corresponding to the backplane 11 through the redundant pin 1021 of the first connector 102. Figure 3 This is a schematic diagram of one embodiment of step S01. Please refer to [link / reference]. Figure 3 .At Figure 3 In one embodiment, the first connector 102 is an MCIO connector, and the first connector 102 includes 74 pins (B1~B37 and A1~A37). Figure 3 In this embodiment, the first connector 102 obtains the identification code corresponding to the backplane 11 through pins A9 and A27. That is, pins A9 and A27 are redundant pins 1021 on the first connector 102 that do not have special functions. In this embodiment, pins A9 and A27 of the first connector 102 are electrically connected to two general purpose input / output pins (GPIO) of the processing circuit 101 to detect the identification code of the backplane to which the first connector 102 is electrically connected.

[0036] In some embodiments, the number of pins of the first connector 102 used to encode the backplane 11 corresponds to the length of the identification code on the backplane 11. Figure 3 For example, if the number of pins of the first connector 102 used to encode the backplane 11 is two (A9 and A27), then the length of the identification code for the backplane 11 is two bits. Figure 3 In this invention, the number of pins of the first connector 102 used to encode the backplane 11 is two, but the invention is not limited thereto, and the number of pins of the first connector 102 used to encode the backplane 11 can be any positive integer.

[0037] In some embodiments, the identification code is represented in binary. Figure 3For example, if the identification code of backplate 11 is 2 bits long, then the identification code of backplate 11 can be 00, 01, 10, or 11. As another example, if the identification code of backplate 11 is 3 bits long, then the identification code of backplate 11 can be 000, 001, 010, 011, 100, 101, 110, or 111.

[0038] In some embodiments, a plurality of pins of the first connector 102 are configured with pull-up or pull-down resistors via a second connector 111 of the electrically connected backplane 11 to obtain an identification code corresponding to the backplane 11. The configuration of the pull-up or pull-down resistors is based on the type of hard drive 114 inserted on the backplane 11 to provide a corresponding identification code. See also... Figure 3 Pin A9 is electrically connected to a grounded pull-down resistor on the backplane 11. This pull-down resistor causes the processing circuit 101 of the motherboard 10 to obtain a code of 0 from the corresponding pin of the second connector 111 of the backplane 11 via pin A9. Pin A27 is electrically connected to a pull-up resistor connected to Vdd on the backplane 11. This pull-up resistor causes the processing circuit 101 of the motherboard 10 to obtain a code of 1 from the corresponding pin of the second connector 111 of the backplane 11 via pin A27. If the code corresponding to pin A9 on the backplane 11 is the first bit of the identification code of the backplane 11, and the code corresponding to pin A27 on the backplane 11 is the second bit of the identification code of the backplane 11, then the identification code of the backplane 11 is 01.

[0039] In some embodiments, the processing circuit 101 of the motherboard 10 is electrically connected to pins A9 and A27 of the first connector via two GPIO pins, respectively. Similarly, the logic circuit 112 of the backplane 11 is also electrically connected to pins A9 and A27 of the first connector via two different GPIO pins through the second connector 111. Therefore, both the processing circuit 101 and the logic circuit 112 can directly obtain the identification code corresponding to the backplane 11 based on the influence of the pull-up resistors and / or pull-down resistors connected to the second connector 111 of the backplane 11 on the voltage levels of pins A9 and A27. In some embodiments, the processing circuit 101 transmits the identification code as a signal to the second connector 111 via the first connector 102. For example, please refer to... Figure 1 When the processing circuit 101 obtains the identification code corresponding to the backplane 11, the processing circuit 101 transmits the identification code to the second connector 111 through the first connector 102 in the form of signal S3. When the logic circuit 112 receives the signal S3 through the second connector 111, the logic circuit 112 stores the identification code in the firmware of the logic circuit 112.

[0040] In some embodiments, the identification code of the backplane 11 is directly assigned through the processing circuit 101 of the motherboard 10.

[0041] In some embodiments, the method for generating the identification code of the backplane 11 is as follows: the processing circuit 101 of the motherboard 10 transmits an indication signal to an unknown backplane 11 based on a plurality of known backplane 11 identification codes already stored in the BIOS of the server system 1. The unknown backplane 11 detects the hard drive types of the plurality of hard drives 114 contained therein and performs calculations based on the indication signal containing the information of the plurality of known backplane 11 identification codes transmitted by the processing circuit 101 of the motherboard 10 to generate another identification code. The logic circuit 112 of the unknown backplane 11 stores this other identification code in the firmware of the logic circuit 112 and sends this other identification code back to the processing circuit 101 of the motherboard 10. This other identification code is the identification code of the unknown backplane 11.

[0042] For example, suppose the motherboard 10 supports three types of hard drives: NVMe, SAS, and SATA. The logic circuit 112 defines the third bit of the identification code for the backplane 11 based on the type of the multiple hard drives 114 contained within it. For instance, when the backplane 11 contains type 1 hard drives, the third bit of the identification code is 1; when it contains type 2 hard drives, the third bit is 2; and when it contains type 3 hard drives, the third bit is 3. When the motherboard 10 receives a 301 (i.e., an indication signal) for an unknown backplane 11, it means that the motherboard 10 has obtained identification codes 300 and 301 for the multiple known backplanes 11. If the multiple hard drives 114 contained in the unknown backplane 11 are of type 3, then the logic circuit 112 of the unknown backplane 11 will continue the encoding of 301 to generate an identification code with a value of 302 corresponding to the unknown backplane 11, store this identification code in the firmware of the logic circuit 112, and send this identification code back to the processing circuit 101 of the motherboard 10. In the above example, since the motherboard 10 has not yet obtained any identification code of the backplane 11 containing type 1 or type 2 hard drives, the transmitted indication signal does not contain the identification code of the backplane 11 corresponding to type 1 or type 2 hard drives. Therefore, if the multiple hard drives 114 contained in the unknown backplane 11 are type 1 or type 2 hard drives, their corresponding identification code can be 100 or 200.

[0043] Figure 4 This is a flowchart of one embodiment of the identification method for backplane 11. In some embodiments, after the server system 1 completes the following... Figure 2 After the encoding method of the backplane 11 shown is executed, the server system 1 will then execute the following... Figure 4 The identification method for the backplate 11 shown. Please refer to [link / reference]. Figure 1 and Figure 4First, the processing circuit 101 of the motherboard 10 provides a first signal S1 to the logic circuit 112 of the backplane 11 (step S11). Next, the logic circuit 112 of the backplane 11 provides a second signal S2 to the multiple hard drives 114 based on the first signal S1 and the identification code stored in the firmware (step S12). Finally, each hard drive 114 controls its indicator light according to the second signal S2 (step S13).

[0044] In step S11, specifically, the processing circuit 101 of the motherboard 10 first transmits the first signal S1 to the first connector 102 through the VPP port 1011, and the first signal S1 is then transmitted to the logic circuit 112 of the backplane 11 through the first connector 102 and the second connector 111.

[0045] In some embodiments, the processing circuit 101 provides a first signal S1 to the logic circuit 112 based on the identification code stored in the BIOS of the server system 1 after the server system 1 completes step S03.

[0046] In some embodiments, the first signal S1 is a sequential signal. In some embodiments, the second signal S2 is a parallel signal.

[0047] Figure 5 This is a schematic diagram of another embodiment of server system 1. Please refer to [link / reference]. Figure 5 Server system 1 includes a motherboard 20 and multiple backplanes 11. The motherboard 20 includes processing circuitry 101 and multiple first connectors 102. The processing circuitry 101 includes a VPP port 1011. The multiple first connectors 102 are coupled to the VPP port 1011. Each backplane 11 includes a second connector 111, logic circuitry 112, multiple hard disk connectors 113, and multiple hard disks 114. The second connectors 111 are coupled to each of the first connectors 102. The logic circuitry 112 is coupled to the second connectors 111. The multiple hard disk connectors 113 are coupled to the logic circuitry 112. Each of the multiple hard disks 114 is individually coupled to each of the hard disk connectors 113.

[0048] In some embodiments, the number of the plurality of first connectors 102 included in the motherboard 20 corresponds to the number of the plurality of backplanes 11. For example, see [link to relevant documentation]. Figure 5 . Figure 5 The number of first connectors 102 included in the motherboard 20 of the server system 1 shown corresponds to the number of backplanes 11, both being three. Figure 5 In this invention, the motherboard 20 includes three first connectors 102 and three backplates 11, but this invention is not limited thereto. The number of first connectors 102 and the number of backplates 11 included in the motherboard 20 can be any positive integer.

[0049] In some embodiments, the plurality of first connectors 102 include a third connector 103 and a fourth connector 104. The third connector 103 and the fourth connector 104 are different types of connectors. The second connector 111 coupled to the third connector 103 and the second connector 111 coupled to the fourth connector 104 are also therefore different types of connectors. For example, see [link to example]. Figure 5 . Figure 5 The plurality of first connectors 102 shown include two third connectors 103 and one fourth connector 104. The two third connectors 103 are MCIO connectors, and the one fourth connector 104 is a disk array card. At this time, the two second connectors 111 coupled to the two third connectors 103 are MCIO connectors, and the second connector 111 coupled to the fourth connector 104 is a SAS connector.

[0050] Figure 6 This is a flowchart illustrating another embodiment of the encoding method for backplane 11. Please refer to... Figure 5 and Figure 6 First, the processing circuit 101 encodes each backplane 11 through multiple pins of each first connector 102 to obtain an identification code corresponding to each backplane 11 (step S21). Next, the processing circuit 101 transmits the identification code to each second connector 111 through each first connector 102. When each logic circuit 112 receives the identification code corresponding to each backplane 11 through each second connector 111, each logic circuit 112 stores the identification code in its firmware (step S22). After obtaining the identification code corresponding to each backplane 11, the processing circuit 101 stores the identification code in the BIOS of the server system 1 (step S23).

[0051] In some embodiments, during step S21, the processing circuit 101 encodes each backplane 11 through the redundant pins 1021 of each first connector 102 to obtain an identification code corresponding to each backplane 11.

[0052] In some embodiments, the firmware of each logic circuit 112 stores the identification codes of all backplanes 11. In other words, in some embodiments, the identification codes stored in the firmware of each logic circuit 112 are the same, that is, all logic circuits 112 of the backplanes 11 can use the same firmware.

[0053] In some embodiments, the processing circuit 101 transmits the identification code as a signal through each of the first connectors 102 to each of the second connectors 111. For example, please refer to... Figure 5After the processing circuit 101 obtains the identification code corresponding to each backplane 11, the processing circuit 101 transmits the identification code to each second connector 111 through each first connector 102 in the form of signal S3. When each logic circuit 112 receives the signal S3 through each second connector 111, each logic circuit 112 stores the identification code in the firmware of each logic circuit 112.

[0054] Figure 7 This is a flowchart of another embodiment of the identification method for backplane 11. In some embodiments, after the server system 1 completes the following... Figure 6 After the encoding method of the backplane 11 shown is executed, the server system 1 will then execute the following... Figure 7 The identification method for the backplate 11 shown. Please refer to [link / reference]. Figure 5 and Figure 7 First, the processing circuit 101 of the motherboard 20 provides a first signal S1 to the logic circuit 112 of each backplane 11 (step S31). Next, the logic circuit 112 of each backplane 11 provides a second signal S2 to the plurality of hard drives 114 of each backplane 11 based on the first signal S1 and the identification code stored in the firmware of the logic circuit 112 of each backplane 11 (step S32). Finally, the plurality of hard drives 114 of each backplane 11 control their LEDs based on the second signal S2 (step S33).

[0055] In step S31, specifically, the processing circuit 101 of the motherboard 20 first transmits the first signal S1 to each first connector 102 through the VPP port 1011. The first signal S1 is then transmitted to the logic circuit 112 of each backplane 11 through each first connector 102 and each second connector 111.

[0056] In some embodiments, the processing circuit 101 provides a first signal S1 to each logic circuit 112 based on the identification code stored in the BIOS of the server system 1 after the server system 1 completes step S23.

[0057] In summary, in some embodiments, by storing the identification code of each backplane 11 in the BIOS of the server system 1 and the firmware of the logic circuit 112 of each backplane 11, the problem of incorrect indicator light display of the hard drive 114 due to incorrect installation can be effectively avoided, further improving the reliability of the server system 1. Furthermore, all backplanes 11 in the server system 1 can use the same firmware, eliminating the need for individual firmware to support different backplanes 11, thereby simplifying the management of the server system 1. In addition, in some embodiments, by using the redundant pins 1021 of the first connector 102 to encode each backplane 11, the server system 1 can determine the combination of backplanes 11 without using additional connection cables, further improving the flexibility of the server system 1 and helping to reduce the complexity of after-sales service and maintenance of the server system 1.

[0058] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A backplane encoding method, applicable to a server system, the server system comprising a motherboard and at least one backplane, the motherboard comprising at least one first connector, each of the at least one backplane comprising a second connector and a logic circuit, each of the at least one first connector being coupled to each of the at least one second connector, characterized in that, This encoding method includes: Each of the at least one backplane is encoded through a plurality of pins of each of the at least one first connector to obtain an identification code corresponding to each of the at least one backplane; Each of the at least one identification code is stored in the firmware of each of the at least one logic circuit; and Each of the at least one identification code is stored in a BIOS of the server system.

2. The encoding method for the backplane according to claim 1, characterized in that, These pins are redundant pins for each of the at least one first connector.

3. The encoding method for the backplane according to claim 1, characterized in that, There are two pins, and the identification code is two bits long.

4. The encoding method for the backplane according to claim 1, characterized in that, The at least one first connector and the at least one second connector are MCIO connectors.

5. The encoding method for the backplane according to claim 1, characterized in that, The at least one first connector includes a third connector and a fourth connector, the third connector being an MCIO connector, the fourth connector being a disk array card, the second connector coupled to the third connector being an MCIO connector, and the second connector coupled to the fourth connector being a SAS connector.

6. The encoding method for the backplane according to claim 1, characterized in that, The firmware of each of the at least one logic circuit stores the identification code of all the at least one backplane.

7. A method for identifying a backplane, applicable to a server system, the server system comprising a motherboard and at least one backplane, the motherboard comprising a processing circuit and at least one first connector, the processing circuit being coupled to the at least one first connector, each of the at least one backplane comprising a second connector, a logic circuit, a plurality of hard disk connectors and a plurality of hard disks, the logic circuit being coupled to the second connector, the hard disk connectors being coupled to the logic circuit, each hard disk being coupled to its respective hard disk connector, each of the at least one first connector being coupled to its respective at least one second connector, the logic circuit comprising firmware, characterized in that... This identification method includes: The processing circuitry of the motherboard provides a first signal to the logic circuitry of each of the at least one backplane; The logic circuit of each of the at least one backplane provides a second signal to the hard drives of each of the at least one backplane based on the first signal and an identification code stored in the firmware of the logic circuit of each of the at least one backplane; and Each of the hard drives on at least one backplane controls its indicator light according to the second signal.

8. The method for identifying the backplate according to claim 7, characterized in that, The processing circuit provides the first signal to each of the at least one logic circuit based on the identification code stored in a BIOS of the server system.

9. The method for identifying the backplate according to claim 7, characterized in that, The processing circuitry further includes a VPP port, through which the processing circuitry is coupled to the at least one first connector.

10. A method for identifying a backplane, applicable to a server system, the server system comprising a motherboard and at least one backplane, the motherboard comprising a processing circuit and at least one first connector, the processing circuit being coupled to the at least one first connector, each of the at least one backplane comprising a second connector, a logic circuit, a plurality of hard disk connectors and a plurality of hard disks, the logic circuit being coupled to the second connector, the hard disk connectors being coupled to the logic circuit, each hard disk being coupled to its respective hard disk connector, each of the at least one first connector being coupled to its respective at least one second connector, the logic circuit comprising firmware, characterized in that... This identification method includes: Each of the at least one backplane is encoded through a plurality of pins of each of the at least one first connector to obtain an identification code corresponding to each of the at least one backplane; Each of the at least one identification code is stored in the firmware of each of the at least one logic circuit; Each of the at least one identification code is stored in a BIOS of the server system; The processing circuitry of the motherboard provides a first signal to the logic circuitry of each of the at least one backplane; The logic circuit of each of the at least one backplane provides a second signal to the hard drives of each of the at least one backplane based on the first signal and the identification code of the firmware stored in the logic circuit of each of the at least one backplane; and Each of the hard drives on at least one backplane controls its indicator light according to the second signal.

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