Instruction reloading method and device, electronic equipment and storage medium

Abstract

The present disclosure provides a kind of instruction reload method, device, electronic equipment and storage medium, it is related to processor technical field, the method comprises: in response to executing first loading instruction, whether there is the second loading instruction that has been executed based on the identification of data queue, wherein, second loading instruction is located after first loading instruction in program order and exception instruction, first loading instruction and second loading instruction access same physical address;In response to identifying second loading instruction, after first loading instruction execution is completed, re-executes second loading instruction.The present disclosure accurately detects load-load exception and implements partial re-execution recovery mechanism, effectively solves the memory access order error problem caused by instruction rearrangement in multi-core environment without sacrificing out-of-order execution performance, significantly improves the reliability and security of system in multi-thread, high concurrency scenario, while giving consideration to execution efficiency.

Description

Technical Field

[0001] This disclosure relates to the field of processor technology, and in particular to an instruction reloading method, apparatus, electronic device, and storage medium. Background Technology

[0002] With the development of integrated circuit technology and the continuous improvement of performance requirements, modern processors generally adopt a multi-core processor architecture, which integrates multiple independent processor cores on a single chip to achieve parallel computing and improve system throughput. In a multi-core system, each processor core typically shares main memory and uses its own cache to accelerate data access. However, while this shared memory model improves performance, it also introduces the cache coherence problem: when multiple cores access the same memory address simultaneously, if the data copies stored in their respective caches are inconsistent, the program execution result will be unpredictable, seriously compromising the correctness of the program. Summary of the Invention

[0003] This disclosure aims to at least partially address one of the technical problems in the related art.

[0004] Therefore, one objective of this disclosure is to propose an instruction reloading method.

[0005] The second objective of this disclosure is to provide an instruction reloading device.

[0006] The third objective of this disclosure is to propose an electronic device.

[0007] The fourth objective of this disclosure is to provide a non-transitory computer-readable storage medium.

[0008] The fifth objective of this disclosure is to provide a computer program product.

[0009] To achieve the above objectives, a first aspect of this disclosure provides an instruction reloading method applicable to out-of-order execution processors, comprising: in response to executing a first load instruction, identifying, based on a fetch queue, whether a second load instruction has already been executed, wherein the second load instruction is an instruction that is violated after the first load instruction in program order, and the first load instruction and the second load instruction access the same physical address; and in response to identifying the second load instruction, re-executing the second load instruction after the first load instruction has been executed.

[0010] According to one embodiment of this disclosure, the step of identifying whether a second load instruction has been executed based on a data retrieval queue includes: traversing the data retrieval queue to identify whether a candidate second load instruction exists in the data retrieval queue, wherein the candidate second load instruction is a load instruction in the data retrieval queue that is sequentially following the first load instruction in the program order, and the first load instruction and the second load instruction access the same physical address; in response to the existence of a candidate second load instruction, determining whether the candidate second load instruction has been executed and violated; and in response to determining that the candidate second load instruction has been executed and violated, determining that the candidate second load instruction is the second load instruction.

[0011] According to one embodiment of this disclosure, determining whether the candidate second load instruction is violated includes: obtaining a valid bit identifier and a release identifier of the candidate second load instruction; in response to the valid bit identifier indicating that the candidate second load instruction has retrieved data from the space corresponding to the physical address, and the release identifier indicating that the data retrieved by the candidate second load instruction has been released, determining that the candidate second load instruction is violated.

[0012] According to one embodiment of this disclosure, the entry in the reordering buffer where the second load instruction is located follows the entry in the reordering buffer where the first load instruction is located.

[0013] According to one embodiment of this disclosure, determining whether the candidate second load instruction has been executed and violated based on the data retrieval queue includes: obtaining the data validity bit identifier and release identifier of the candidate second load instruction based on the data retrieval queue; and determining that the candidate second load instruction has been executed and violated in response to the data validity bit identifier indicating that data has been retrieved and the release identifier indicating that the cache line has been released by the data cache.

[0014] According to one embodiment of this disclosure, determining that the release flag indicates that a cache line has been released by the data cache includes one of the following situations: in response to receiving an external detection request from another processor core; in response to receiving a replacement request; in response to an invalid or invalid write-back caused by a cache instruction.

[0015] According to one embodiment of this disclosure, the method further includes: after receiving a release signal, setting the release flag of the data retrieval queue entry corresponding to the cache line address of the release signal in the data retrieval queue to be released.

[0016] According to one embodiment of this disclosure, the execution priority of the release signal is higher than that of the violation check instruction.

[0017] According to one embodiment of this disclosure, re-executing the second loading instruction includes: transmitting the second loading instruction and a third instruction through a reserved station, wherein the third instruction is an instruction that is sequentially located after the second loading instruction in the program order.

[0018] According to one embodiment of this disclosure, re-executing the second loading instruction includes: sending a retransmission instruction command to a retention station based on the second loading instruction and the third instruction; and retransmitting the second loading instruction and the third instruction through the retention station.

[0019] According to one embodiment of this disclosure, the third instruction is all instructions following the reordering buffer entry where the second load instruction is located.

[0020] According to one embodiment of this disclosure, the method further includes: updating the data validity bit identifier in the data retrieval queue of the second loading instruction to invalid.

[0021] To achieve the above objectives, a second aspect of this disclosure provides an instruction reloading apparatus suitable for out-of-order execution processors, comprising: an identification module, configured to, in response to the execution of a first load instruction, identify, based on a fetch queue, whether a second load instruction has already been executed, wherein the second load instruction is an instruction that is violated after the first load instruction in program order, and the first load instruction and the second load instruction access the same physical address; and a loading module, configured to, in response to the identification of the second load instruction, re-execute the second load instruction after the first load instruction has been executed.

[0022] To achieve the above objectives, a third aspect of this disclosure provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to implement the instruction reloading method as described in the first aspect of this disclosure.

[0023] To achieve the above objectives, a fourth aspect of this disclosure provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to implement the instruction reloading method as described in the first aspect of this disclosure.

[0024] To achieve the above objectives, a fifth aspect of this disclosure provides a computer program product including a computer program that, when executed by a processor, implements the instruction reloading method as described in the first aspect of this disclosure.

[0025] This disclosure effectively solves the memory access order error caused by instruction reordering in multi-core environments by accurately detecting load-load violations and implementing a partial re-execution recovery mechanism, without sacrificing out-of-order execution performance. It significantly improves the reliability and security of the system in multi-threaded and high-concurrency scenarios, while also taking execution efficiency into account. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of an instruction reloading method according to one embodiment of the present disclosure;

[0027] Figure 2 This is a schematic diagram of another instruction reloading method according to one embodiment of the present disclosure; Figure 3 This is a schematic diagram of another instruction reloading method according to one embodiment of the present disclosure; Figure 4 This is a schematic diagram of an instruction reloading device according to one embodiment of the present disclosure; Figure 5 This is a schematic diagram of an electronic device according to one embodiment of the present disclosure. Detailed Implementation

[0028] Embodiments of this disclosure are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this disclosure, and should not be construed as limiting this disclosure.

[0029] The acquisition, storage, use, and processing of data in this disclosed technical solution all comply with the relevant provisions of relevant laws and regulations.

[0030] It should be noted that in the embodiments of this application, certain software, components, models and other existing solutions in the industry may be mentioned. These should be regarded as exemplary and are only intended to illustrate the feasibility of implementing the technical solution of this application. However, it does not mean that the applicant has used or necessarily used the solution.

[0031] In current technology, ensuring the correct and efficient sharing of accessed data among multiple processor cores in a multi-core processor is essential and crucial, thus requiring the maintenance of cache coherence. Processor memory access instructions include load instructions and store instructions. To ensure correct program execution, the execution order of load instructions must be maintained. If other processor cores may be performing store operations on the same address, the load instructions for that address must not be skipped during out-of-order execution. If a later load instruction skips an earlier one, and other processor cores may be performing store operations on the same address, this is called a load instruction violation, requiring checks and handling.

[0032] For example, a multi-core processor has two cores, Core1 and Core2. In main memory, there's an instruction `int a = 0`. Core1 has two fetch instructions, Load1 and Load2, both reading `a`. Core1 executes out of order, while Load2 skips Load1. Load2 executes first, fetching the data `a` into Core1's cache, where `a` equals 0. Next, Core2 has a store instruction to write `a = 1`. To maintain cache consistency, it first writes `a = 0` from Core1's cache back to main memory and invalidates it. Core2's store instruction then writes `a = 1` into its cache. When Core1's Load1 fetch instruction reads `a`, it retrieves the new result `a = 1`, which has been written by Core2. However, in program order, Load1 precedes Load2. Core1's Load2 reads the value `a = 0` before Core2's Store instruction, while Core1's Load1 reads the value `a = 1` after Core2's Store instruction. For Core1, if the instruction Load2, which is later in the program sequence, reads an older value, while the instruction Load1, which is earlier in the program sequence, reads a newer value, an error will occur.

[0033] To address the aforementioned issues, this disclosure proposes an instruction reloading method. Figure 1 This is a schematic diagram of an instruction reloading method according to one embodiment of the present disclosure, as shown below. Figure 1 As shown, the instruction reloading method includes the following steps: S101, in response to executing the first load instruction, identifies whether there is a second load instruction that has been executed based on the data fetch queue, wherein the second load instruction is an instruction that is violated after the first load instruction in the program order, and the first load instruction and the second load instruction access the same physical address.

[0034] The instruction reloading method of this application embodiment can be applied to scenarios of data fetching instructions and data fetching instruction violation checking and processing. The execution subject of instruction reloading in this application embodiment can be the instruction reloading device of this application embodiment, which can be installed on an electronic device.

[0035] The fetch queue is a hardware structure in the processor used to track all issued but not yet committed load instructions. Each entry in the fetch queue records various information, such as the physical address of the instruction, whether data reading has been completed (Executed), and its order information in the program (usually associated through the Reorder Buffer (ROB) index).

[0036] In one possible implementation, the data retrieval queue may include the contents shown in the table below:

[0037] During the execution of an instruction in the load pipeline, the state of the load queue can be updated at multiple stages. For example, it can be done as follows: (1) Update the state of the data retrieval queue (Load Queue) during data retrieval pipeline stage 2 (Load Stage 2).

[0038] The first stage of the data retrieval pipeline accesses the data cache (DCache). In the second stage, the results and physical addresses of accessing the DCache are written to the Load Queue. The status flags updated at this time include: datavalid, writebacked, miss, and released.

[0039] (2) Update the state of the data retrieval queue (Load Queue) during data retrieval pipeline stage 3 (Load Stage 3).

[0040] In stage 3 of the fetch pipeline, the results of fetch instructions and fetch violation are updated. The Load Queue uses these results to update its state. For example, fetch instructions and fetch violation will trigger a data cache access re-execution event, meaning that the event of resending a fetch instruction's DCache access request from the instruction reservation station will be triggered. This is achieved by updating `miss` and `datavalid` to `false`. This indicates that the instruction will be resent from the reservation station, rather than waiting in the Load Queue for data cache refill to wake it up. Simultaneously, the reservation station feedback operation in stage 3 of the fetch instruction (Load) pipeline is performed, reporting that a fetch instruction and fetch violation have occurred, requiring re-execution of subsequent fetch instructions and all other instructions following this fetch instruction from the reservation station.

[0041] It should be noted that the first load instruction is when the processor is processing (or has just completed) a load instruction. After the first load instruction is detected, a check is triggered to examine the load queue to see if another load instruction (called the second load instruction) has completed the memory read operation.

[0042] Although the second load instruction has finished executing, its position in the program is actually after the first load instruction. This is determined by comparing the order of entries in the Reorder Buffer (ROB) between the first and second load instructions; the ROB entry order equals the original program order. Furthermore, the first and second load instructions access the same physical address; these two load instructions read the same memory address, for example, both reading address 0x1000 (hexadecimal, corresponding to binary 0001 0000 0000 0000).

[0043] It should be noted that both the Load A instruction, which appears earlier in the program sequence, and the Load B instruction, which appears later in the program sequence, read the same address X.

[0044] Under normal circumstances, Load A should first read the value of X, V1, and then Load B should read V2 (which may have been modified by someone else).

[0045] However, if due to out-of-order execution, Load B completes its read (reads V2) before Load A executes, and another CPU core writes a new value V3 after Load B and before Load A, then when Load A finally executes, it might read V3, while Load B reads V2. This would cause Load A, which is earlier in the program sequence, to see the "updated" value, violating program semantics.

[0046] S102, in response to the recognition of the second load instruction, the second load instruction is re-executed after the first load instruction has been executed.

[0047] In this embodiment of the disclosure, the system waits for the first load instruction to actually complete execution (i.e., read the correct data from memory / cache). This ensures that the preceding Load instruction receives the correct value, allowing subsequent instructions to be safely redone.

[0048] After the first load instruction is executed, the processor discards all results produced by the second load instruction and its subsequent instructions, as they were calculated based on erroneous or outdated data. It then re-executes the second load instruction and continues executing all instructions that follow it.

[0049] In this embodiment, in response to the execution of a first load instruction, the system first identifies whether a second load instruction has already been executed based on a data fetch queue. This second load instruction is a violation instruction that follows the first load instruction in the program order and accesses the same physical address as the first load instruction. Then, in response to the identification of the second load instruction, the system re-executes the second load instruction after the first load instruction has finished executing. This disclosure, by accurately detecting load-load violations and implementing a partial re-execution recovery mechanism, effectively solves the memory access order error problem caused by instruction reordering in multi-core environments without sacrificing out-of-order execution performance. This significantly improves the reliability and security of the system in multi-threaded, high-concurrency scenarios while also considering execution efficiency.

[0050] In this embodiment of the disclosure, after determining the second load instruction, the data validity bit flag of the second load instruction in the data retrieval queue is updated to invalid.

[0051] In the above embodiments, based on the data retrieval queue, it can be determined whether a second loading instruction has already been executed. Figure 2 To further explain, the method includes: S201, traverse the data retrieval queue and identify whether there is a candidate second load instruction in the data retrieval queue. The candidate second load instruction is the load instruction in the data retrieval queue that is located after the first load instruction in the program order, and the first load instruction and the second load instruction access the same physical address.

[0052] In this embodiment of the disclosure, when executing the first load instruction, it is checked whether there is another load instruction (referred to as the candidate second load instruction) that is sequentially executed after the first load instruction but may have been executed earlier and accesses the same memory address. If it exists, it may constitute a load-load violation and requires further processing.

[0053] S202, in response to the existence of a candidate second load instruction, determine whether the candidate second load instruction has been executed and violated based on the data fetch queue.

[0054] In this embodiment of the disclosure, one or more candidate second load instructions have been found by traversing the load queue. However, these candidate instructions may not have been executed completely; they may have only been issued and are still waiting for data or execution units.

[0055] In this embodiment of the disclosure, to determine whether a candidate second load instruction has been executed and violated based on the data retrieval queue, the data validity bit identifier and release identifier of the candidate second load instruction can be obtained based on the data retrieval queue. Then, in response to the data validity bit identifier showing that the data has been retrieved and the release identifier indicating that the cache line has been released by the data cache, it is determined that the candidate second load instruction has been executed and violated.

[0056] In one possible implementation, the execution completion flag (such as Executed or DataValid) of each Load entry in the Load Queue can be used to determine whether the instruction has been executed and violated. If the flag is true, it means that the Load instruction has completed data fetching and retrieved the data. At the same time, the release flag indicates that the cache line has been released from the data cache, confirming that the candidate second Load instruction has been executed and violated.

[0057] In one possible implementation, when a processor core of a multi-core processor receives an external probe request from another processor core, a replacement request from the processor core itself, or an invalid or invalid write-back caused by a cache instruction, it will set the released flag to be released.

[0058] In this embodiment of the disclosure, upon receiving a release signal, the release flag of the fetch queue entry corresponding to the cache line address of the release signal in the fetch queue is set to "released". When the data cache (DCache) is released, a Release signal is sent to the load queue to indicate that the DCache has lost read permission for a certain cache line. The generation of the DCache Release signal signifies that the DCache will mark all loads to the same cache line after this cycle as "missed" until the DCache regains permission for this cache line. The DCache Release signal is generated simultaneously with the update of the cache line status bit within the DCache when the DCache is released. After receiving the DCache release signal, the fetch queue sets the release flag of the fetch queue entry corresponding to the cache line address in the fetch queue to "released".

[0059] When the DCache Release signal updates the released status bit in the Load Queue, it matches the port address (Load Paddr) of the load-load violation check contention instruction in the normal Load pipeline. The execution priority of the release signal is higher than that of the violation check instruction. To improve efficiency, if the resource cannot be contented, the Load instruction in the pipeline will be immediately resent from the reserved station.

[0060] S203, in response to determining that the candidate second load instruction has been executed and violated, determines that the candidate second load instruction is the second load instruction.

[0061] In this embodiment, the data fetch queue is first traversed to identify whether a candidate second load instruction exists. A candidate second load instruction is a load instruction in the data fetch queue that follows the first load instruction in the program sequence, and both the first and second load instructions access the same physical address. In response to the existence of a candidate second load instruction, the data fetch queue is used to determine whether the candidate second load instruction has already been executed and violated. In response to the determination that the candidate second load instruction has been executed and violated, it is confirmed as the second load instruction. Therefore, by identifying and confirming executed subsequent load instructions that access the same physical address in the data fetch queue, the correctness of memory access in multi-core processors can be efficiently ensured, redundant memory accesses can be effectively eliminated, power consumption and latency can be reduced, and processor execution efficiency and energy efficiency ratio can be improved.

[0062] It should be noted that the entry in the reordering buffer where the second load instruction is located follows the entry in the reordering buffer where the first load instruction is located.

[0063] In the above embodiments, re-executing the second loading instruction can also be achieved through... Figure 3 To further explain, the method includes: S301 transmits a second loading instruction and a third instruction through a reserved station, wherein the third instruction is the instruction that follows the second loading instruction in the program sequence.

[0064] In this embodiment of the disclosure, the third instruction is all instructions following the reordering buffer entry where the second load instruction is located.

[0065] It should be noted that there may be one or more third instructions. In one possible scenario, there may not be any third instructions. No restrictions are imposed here.

[0066] It should be noted that the Reservation Station (RS) is used to temporarily store instructions that are waiting to be issued or have been issued but not yet completed. Each instruction waits in the RS for its operands to become ready before being dispatched to a functional unit (Arithmetic Logic Unit (ALU), Load / Store Unit, etc.) for execution.

[0067] In this embodiment of the disclosure, the resend instruction command does not fetch the instruction from memory again, but rather re-injects the instruction that already exists in the pipeline but has an invalid result into the execution flow.

[0068] The specific operations include: 1. Mark the second load instruction as invalid in the ROB and execution pipeline.

[0069] In one possible scenario, if the third instruction is a fetch instruction, then the third instruction needs to be marked as invalid in the ROB and execution pipeline.

[0070] 2. Set these instructions to a non-launch execution state in the reserved station (and / or Load / Store Queue), awaiting rescheduled launch.

[0071] This re-execution will be performed after the first load instruction has been completed and the memory state is determined, ensuring that the correct data is read.

[0072] It should be noted that the order of the second load instruction and the third instruction (if the third instruction is a data fetch instruction) in the reserved station is the same as the order of the instructions in the data fetch queue.

[0073] It should be noted that although execution is out of order, data and control dependencies between instructions must respect the original order and be reordered using a reordering buffer. This ensures that subsequent instructions of the second load instruction can correctly wait for the result of the second load instruction.

[0074] In this embodiment of the disclosure, re-executing the second load instruction can first involve sending a retransmission command to the retention station based on the second and third load instructions, and then retransmitting the second and third load instructions through the retention station. Thus, through a closed-loop mechanism of "detecting candidate violations, confirming execution, sending a retransmission command to the retention station, and finally retransmitting execution," efficient, accurate, and low-overhead repair of Load-Load violations is achieved.

[0075] Corresponding to the instruction reloading methods provided in the above embodiments, an embodiment of this disclosure also provides an instruction reloading device. Since the instruction reloading device provided in this disclosure corresponds to the instruction reloading methods provided in the above embodiments, the implementation methods of the above instruction reloading methods are also applicable to the instruction reloading device provided in this disclosure, and will not be described in detail in the following embodiments.

[0076] Figure 4 This is a schematic diagram of an instruction reloading device according to one embodiment of the present disclosure, as shown below. Figure 4 As shown, the instruction reloading device 400 includes an identification module 410 and a loading module 420.

[0077] The identification module 410 is used to identify, in response to the execution of the first load instruction, whether there is a second load instruction that has been executed based on the data retrieval queue, wherein the second load instruction is an instruction that is violated after the first load instruction in the program order, and the first load instruction and the second load instruction access the same physical address.

[0078] The loading module 420 is configured to, in response to the recognition of the second loading instruction, re-execute the second loading instruction after the first loading instruction has been executed.

[0079] According to one embodiment of this disclosure, the step of identifying whether a second load instruction has been executed based on a data retrieval queue includes: traversing the data retrieval queue to identify whether a candidate second load instruction exists in the data retrieval queue, wherein the candidate second load instruction is a load instruction in the data retrieval queue that is sequentially following the first load instruction in the program order, and the first load instruction and the second load instruction access the same physical address; in response to the existence of a candidate second load instruction, determining whether the candidate second load instruction has been executed and violated; and in response to determining that the candidate second load instruction has been executed and violated, determining that the candidate second load instruction is the second load instruction.

[0080] According to one embodiment of this disclosure, determining whether the candidate second load instruction is violated includes: obtaining a valid bit identifier and a release identifier of the candidate second load instruction; in response to the valid bit identifier indicating that the candidate second load instruction has retrieved data from the space corresponding to the physical address, and the release identifier indicating that the candidate second load instruction has released the data, determining that the candidate second load instruction is violated.

[0081] According to one embodiment of this disclosure, the entry in the reordering buffer where the second load instruction is located follows the entry in the reordering buffer where the first load instruction is located.

[0082] According to one embodiment of this disclosure, determining that the release flag indicates that a cache line has been released by the data cache includes one of the following situations: in response to receiving an external detection request from another processor core; in response to receiving a replacement request; in response to an invalid or invalid write-back caused by a cache instruction.

[0083] According to one embodiment of this disclosure, the method further includes: after receiving a release signal, setting the release flag of the data retrieval queue entry corresponding to the cache line address of the release signal in the data retrieval queue to be released.

[0084] According to one embodiment of this disclosure, the execution priority of the release signal is higher than that of the violation check instruction.

[0085] According to one embodiment of this disclosure, determining whether the candidate second load instruction has been executed and violated based on the data retrieval queue includes: obtaining the data validity bit identifier and release identifier of the candidate second load instruction based on the data retrieval queue; and determining that the candidate second load instruction has been executed and violated in response to the data validity bit identifier indicating that data has been retrieved and the release identifier indicating that the cache line has been released by the data cache.

[0086] According to one embodiment of this disclosure, re-executing the second loading instruction includes: transmitting the second loading instruction and a third instruction through a reserved station, wherein the third instruction is an instruction that is sequentially located after the second loading instruction in the program order.

[0087] According to one embodiment of this disclosure, re-executing the second loading instruction includes: sending a retransmission instruction command to a retention station based on the second loading instruction and the third instruction; and retransmitting the second loading instruction and the third instruction through the retention station.

[0088] According to one embodiment of this disclosure, the third instruction is all instructions following the reordering buffer entry where the second load instruction is located.

[0089] According to one embodiment of this disclosure, the method further includes: updating the data validity bit identifier in the data retrieval queue of the second loading instruction to invalid.

[0090] This disclosure effectively solves the memory access order error caused by instruction reordering in multi-core environments by accurately detecting load-load violations and implementing a partial re-execution recovery mechanism, without sacrificing out-of-order execution performance. It significantly improves the reliability and security of the system in multi-threaded and high-concurrency scenarios, while also taking execution efficiency into account.

[0091] To implement the above embodiments, this disclosure also proposes an electronic device 500. Figure 5 This is a schematic diagram of an electronic device according to one embodiment of the present disclosure, such as... Figure 5 As shown, the electronic device 500 includes: a processor 501 and a memory 502 communicatively connected to the processor. The memory 502 stores instructions executable by at least one processor. The instructions are executed by at least one processor 501 to achieve the functions described in this disclosure. Figures 1-3 The instruction reloading method of the embodiment.

[0092] To implement the above embodiments, this disclosure also proposes a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to implement the present disclosure. Figures 1-3 The instruction reloading method of the embodiment.

[0093] To implement the above embodiments, this disclosure also proposes a computer program product, including a computer program, which, when executed by a processor, implements the features of this disclosure. Figures 1-3 The instruction reloading method of the embodiment.

[0094] It should be noted that personal information collected from users should be used for legitimate and reasonable purposes and should not be shared or sold outside of these legitimate uses. Furthermore, such collection / sharing should only be conducted after receiving the user's informed consent, including but not limited to notifying the user to read the user agreement / user notice and sign an agreement / authorization that includes authorization of relevant user information before the user uses the function. In addition, any necessary steps must be taken to protect and safeguard access to such personal information data and ensure that others with access to personal information data comply with their privacy policies and procedures.

[0095] This application is intended to provide an implementation scheme for users to selectively prevent the use or access to their personal information data. Specifically, this disclosure is intended to provide hardware and / or software to prevent or block access to such personal information data. Once personal information data is no longer needed, risks can be minimized by restricting data collection and deleting data. Furthermore, where applicable, such personal information is de-identified to protect user privacy.

[0096] In the foregoing descriptions of the embodiments, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0097] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0098] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0099] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that contains, stores, communicates, propagates, or transmits programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0100] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0101] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0102] Furthermore, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0103] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of this application.

Claims

1. A method for instruction reloading, characterized in that, Applicable to out-of-order execution processors, including: In response to the execution of the first load instruction, the system identifies whether a second load instruction has been executed based on the data fetch queue, wherein the second load instruction is an instruction that is violated after the first load instruction in the program order, and the first load instruction and the second load instruction access the same physical address; In response to the recognition of the second loading instruction, the second loading instruction is re-executed after the first loading instruction has been executed.

2. The method according to claim 1, characterized in that, The method of identifying whether a second loading instruction has been executed based on the data retrieval queue includes: Traverse the data retrieval queue and identify whether there is a candidate second load instruction in the data retrieval queue. The candidate second load instruction is a load instruction in the data retrieval queue that is located after the first load instruction in the program order, and the first load instruction and the second load instruction access the same physical address. In response to the existence of a candidate second load instruction, determine whether the candidate second load instruction has been executed and violated; In response to determining that the candidate second load instruction has been executed and violated, the candidate second load instruction is determined to be the second load instruction.

3. The method according to claim 2, characterized in that, Determining whether the candidate second load instruction is violated includes: Obtain the valid bit identifier and release identifier of the candidate second load instruction; In response to the valid bit flag indicating that the candidate second load instruction has retrieved data from the space corresponding to the physical address, and the release flag indicating that the data retrieved by the candidate second load instruction has been released, the candidate second load instruction is determined to be in violation.

4. The method according to claim 1, characterized in that, The entry in the reordering buffer containing the second load instruction follows the entry in the reordering buffer containing the first load instruction.

5. The method according to claim 2, characterized in that, The step of determining whether the candidate second load instruction has been executed and is invalid based on the data retrieval queue includes: Based on the data retrieval queue, obtain the data validity bit identifier and release identifier of the candidate second load instruction; In response to the data validity flag indicating that data has been retrieved and the release flag indicating that the cache line has been released from the data cache, it is determined that the candidate second load instruction has been executed and is a violation.

6. The method according to claim 5, characterized in that, Determining that the release flag indicates the cache line has been released from the data cache includes one of the following situations: In response to receiving an external detection request from another processor core; In response to receiving a replacement request; In response to invalid or invalid write-backs caused by cache directives.

7. The method according to claim 6, characterized in that, The method further includes: Upon receiving a release signal, the release flag of the data retrieval queue entry corresponding to the cache line address of the release signal in the data retrieval queue is set to "released".

8. The method according to claim 7, characterized in that, The execution priority of the release signal is higher than that of the violation check instruction.

9. The method according to claim 1, characterized in that, The re-execution of the second loading instruction includes: The second loading instruction and the third instruction are transmitted through the reserved station, wherein the third instruction is an instruction that follows the second loading instruction in the program sequence.

10. The method according to claim 9, characterized in that, The re-execution of the second loading instruction includes: Based on the second loading instruction and the third instruction, a retransmission instruction command is sent to the retention station; The second loading command and the third command are re-transmitted through the reserved station.

11. The method according to claim 10, characterized in that, The third instruction is all instructions following the reordering buffer entry where the second load instruction is located.

12. The method according to any one of claims 1-9, characterized in that, The method further includes: The second load instruction updates the data validity bit flag in the data retrieval queue to invalid.

13. An instruction reloading device, characterized in that, Applicable to out-of-order execution processors, including: The identification module is used to identify, in response to the execution of the first load instruction, whether there is a second load instruction that has been executed based on the data retrieval queue, wherein the second load instruction is an instruction that is violated after the first load instruction in the program order, and the first load instruction and the second load instruction access the same physical address; A loading module is configured to, in response to the recognition of the second loading instruction, re-execute the second loading instruction after the first loading instruction has been executed.

14. An electronic device, characterized in that, Including memory and processor; The processor reads executable program code stored in the memory to run a program corresponding to the executable program code, so as to implement the method as described in any one of claims 1-12.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1-12.

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