Link fault repair method, controller, interface, corelet, and computing system
By introducing a physical layer reset mode into the UCIe protocol, which only performs a reset operation on the physical layer, the problems of long reset time and low bandwidth utilization in the whole link are solved, and fast fault recovery and efficient data transmission are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI BIREN TECH CO LTD
- Filing Date
- 2026-05-11
- Publication Date
- 2026-06-05
AI Technical Summary
In the existing UCIe protocol, link failures that cannot be resolved by physical layer retraining can only be addressed by initiating a full-link reset, resulting in long recovery times and low bandwidth utilization. In particular, in scenarios with degraded link quality, unresponsive transactions are severely lost.
A physical layer reset mode is introduced, which only resets the physical layer while keeping the protocol layer and adaptation layer unchanged. The controller's negotiated configuration parameters and data in the retry buffer are preserved, and data transmission is restored through full link training.
It significantly shortens fault recovery time, improves system availability and bandwidth utilization, avoids the loss of incomplete transactions, and reduces the impact on the chip.
Smart Images
Figure CN122152597A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of chip technology, and more specifically, to a link fault repair method, a controller based on a universal chip interconnect standard, a universal chip interconnect interface, a chip, and a computing system. Background Technology
[0002] Universal Chiplet Interconnect Express (UCIe) is an open and unified interconnect protocol for chips (dies in a chip). It enables chips from different manufacturers and manufactured using different processes to achieve high-bandwidth, low-latency interconnect communication within the same package, thereby improving system performance and reducing power consumption and cost.
[0003] The UCIe protocol adopts a layered architecture, which can be divided into the Protocol Layer, the Adapter Layer, and the Physical Layer. The Protocol Layer is responsible for protocol parsing and session management; the Adapter Layer is responsible for protocol conversion, data caching, and link management; and the Physical Layer implements functions such as signal transmission, link training, clock distribution, and power management.
[0004] In the current UCIe protocol, for link failures that cannot be resolved by physical layer retraining, a full-link reset is the only option. In full-link reset mode, the protocol layer, adaptation layer, and physical layer are reset in tandem, and the data in the retry buffer is cleared to restart the link. The entire reset process relies on a full-chip boot process, requiring the reinitialization of all high-speed interfaces, including Peripheral Component Interconnect Express (PCIe) interfaces and Double Data Rate SDRAM (DDR SDRAM) interfaces. While full-link reset mode can completely repair link failures, the recovery time is long, and the forced clearing of the retry buffer can lead to the loss of unresponsive transactions, reducing bandwidth utilization. This presents a problem of an excessively large reset range for some failure scenarios caused by link quality degradation. Summary of the Invention
[0005] One objective of this disclosure is to provide a new technical solution for link failure repair, in order to control recovery time and improve system availability.
[0006] According to a first aspect of the present disclosure, a link fault repair method is provided. The method is applied to a controller of a first general-purpose interconnect interface (GPII), the first GPII including the controller and a physical layer driven by the controller. The method includes: In response to the occurrence of a set first reset event, a first reset process corresponding to the physical layer reset mode is executed; wherein, the first reset process includes: pausing the transmission of new data, driving the physical layer to switch from the reset state to the active state through full link training, and retaining the configuration parameters negotiated by the controller and the data in the retry cache; After the physical layer reset is completed through the first reset process, the data in the retry buffer is resumed based on the configuration parameters and the link parameters obtained by the physical layer through the complete link training.
[0007] Optionally, the method further includes: In response to a second reset event that fails to reset the physical layer, the second reset process corresponding to the full-link reset mode is executed to complete the full-link reset. The second reset process includes: performing a reset operation and clearing the data in the retry cache; and driving the physical layer to perform the state transition.
[0008] Optionally, the first reset event includes the number of physical layer retraining failures reaching a set number.
[0009] Optionally, the step of performing a first reset process corresponding to a physical layer reset mode in response to the occurrence of a predetermined first reset event includes: In response to the occurrence of a predefined first reset event, determine whether the physical layer reset mode is enabled; When the physical layer reset mode is enabled, the first reset process is executed; If the physical layer reset mode is disabled, a second reset process corresponding to the full-link reset mode is executed.
[0010] Optionally, in response to a predetermined first reset event, the method further includes: By negotiating configuration parameters with the second general-purpose core interconnect interface, it is determined whether the second general-purpose core interconnect interface supports the physical layer reset mode; If the second general-purpose chip interconnect interface supports the physical layer reset mode, then enable the physical layer reset mode; If the second general-purpose chip interconnect interface does not support the physical layer reset mode, then the physical layer reset mode is disabled.
[0011] Optionally, after completing the physical layer reset through the first reset process, restoring the transmission of the data in the retry buffer based on the configuration parameters and the link parameters obtained by the physical layer through the complete link training includes: After confirming that both the first general-purpose core interconnect interface and the interconnected second general-purpose core interconnect interface have completed the physical layer reset, the data in the retry buffer is resumed based on the configuration parameters and the link parameters obtained by the physical layer through the complete link training. The physical layer reset of the second general-purpose chip interconnect interface is triggered by the physical layer of the first general-purpose chip interconnect interface sending a sideband message to the physical layer of the second general-purpose chip interconnect interface via a sideband link.
[0012] Optionally, pausing the transmission of new data and driving the physical layer to switch from a reset state to an active state after full link training includes: Send a first reset request to the physical layer requesting a physical layer reset; Based on the pause request signal sent by the physical layer based on the first reset request, the transmission of new data at the link boundary is paused, and a pause confirmation signal is returned to the physical layer, triggering the physical layer to enter the reset state; The retention of the negotiated configuration parameters of the controller and the data in the retry cache includes: Based on the first status signal reported by the physical layer indicating that the physical layer reset has been initiated, the configuration parameters negotiated by the controller and the data in the retry cache are retained; wherein, the first status signal is reported by the physical layer when it enters the reset state.
[0013] Optionally, the controller sends the first reset request through a reserved code of the status request signal of the bare die inter-particle interface, and the physical layer reports the first status signal through the reserved code of the status indication signal of the bare die inter-particle interface.
[0014] Optionally, driving the physical layer to perform a state transition from a reset state to an active state after a complete link training process further includes: Upon receiving the first state signal, a first activation request is sent to the physical layer to request activation; wherein, the first activation request is used to trigger the physical layer to switch from the reset state to the activated state through full link training; Based on the second state signal reported by the physical layer indicating that the physical layer is in an active state, the physical layer reset is confirmed to be complete.
[0015] According to a second aspect of this disclosure, a controller based on a generic chip interconnect protocol is also provided, the controller being configured to perform the method described according to a first aspect of this disclosure.
[0016] According to a third aspect of this disclosure, a universal chip interconnect interface is also provided, including a controller as described in the second aspect of this disclosure and a physical layer capable of responding to physical layer reset.
[0017] According to a fourth aspect of this disclosure, a chip is also provided, the chip being provided with the universal chip interconnect interface described in a third aspect of this disclosure.
[0018] According to a fifth aspect of this disclosure, a computing system is also provided, which includes at least one chip as described in a fourth aspect of this disclosure.
[0019] This disclosure provides a novel reset mode for general-purpose chip interconnect interfaces: the physical layer reset mode. In this mode, only the physical layer performs the reset operation, transitioning from a reset state to an active state. The controller, including the protocol layer and adaptation layer, does not need to be reset, retaining its negotiated configuration parameters and data in the retry buffer. Thus, after the physical layer reset, the controller can directly utilize these configuration parameters and the link parameters obtained from the physical layer reset to restore the data in the transmission retry buffer, preventing the loss of incomplete transactions. Furthermore, since the physical layer reset operation only covers the physical layer, it eliminates the need to reinitialize all high-speed interfaces of the chip or reload the driver, significantly reducing fault recovery time and effectively improving system availability.
[0020] Other features and advantages of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description
[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure.
[0022] Figure 1 This is a schematic diagram of the structure of a computing system provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of a physical layer link state machine provided in an embodiment of this disclosure; Figure 3 This is a flowchart illustrating a link fault repair method provided in an embodiment of this disclosure; Figure 4 This is a schematic diagram of an RDI state machine provided in an embodiment of this disclosure; Figure 5This is a flowchart illustrating another link fault repair method provided in this embodiment of the disclosure; Figure 6 This is a flowchart illustrating another link fault repair method provided in this disclosure embodiment; Figure 7 This is a schematic diagram of the process of driving the physical layer to complete the physical layer reset according to an embodiment of this disclosure; Figure 8 This is a schematic diagram of a general-purpose chip interconnect interface provided in an embodiment of this disclosure. Detailed Implementation
[0023] Various exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.
[0024] The following description of at least one exemplary embodiment is merely illustrative and is not intended to limit this disclosure or its application or use. Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus may be considered part of the specification.
[0025] It should be noted that similar labels and letters in the following figures indicate similar items, so once an item is defined in one figure, it need not be discussed further in subsequent figures.
[0026] This disclosure relates to a link fault recovery scheme based on UCIe. Figure 1 This is a schematic diagram of the structure of a computing system that can apply the technical solutions provided in the embodiments of this disclosure.
[0027] like Figure 1 As shown, the computing system 1000 may include at least two cores, for example, including Figure 1 The first chip 1100 and the second chip 1200 shown may include more chips. Chips can be interconnected via a universal chip interconnect interface conforming to the UCIe protocol.
[0028] The core of a computing system can be one or more of a computing core, a storage core, or an input / output interface core. For example, the computing core may include multiple streaming processor clusters (SPCs), and the SPC may include multiple computing cores (e.g., GPU Cores). The storage core may include high-bandwidth memory (HBM) or other storage devices. The computing system can implement functions related to artificial intelligence (AI), scientific computing, or image processing based on multiple cores. In this embodiment, the computing system 1000 may be a system-on-a-chip (SoC), a chip, an AI chip, or a computing device, etc.
[0029] It should be noted that, Figure 1 The structure of the computing system shown is illustrative, and the computing system in this embodiment is not limited to the above structure. Exemplarily, the computing system may also include other devices such as control devices and display devices.
[0030] In the layered architecture of the UCIe protocol, the protocol layer and the adaptation layer constitute the UCIe controller that drives the physical layer. The protocol layer and the adaptation layer communicate via a Frame-Aware Die-to-Die Interface (FDI), while the adaptation layer and the physical layer communicate via a Raw Die-to-Die Interface (RDI). The protocol layer interconnects with the network-on-chip (NoC) within the chip via dedicated bridging logic. The protocol layer acts as a translator, converting and encapsulating information from the NoC into UCIe standard transaction packets, and converting and encapsulating UCIe transaction packets into data packet formats that the NoC can recognize and route. The adaptation layer acts as a scheduler, performing flow control, sequencing, and multiplexing of transactions from the protocol layer, breaking them down into smaller, more regular data units (Flits) for transmission over the physical link. The physical layer can act as a courier, performing the lowest-level electrical or optical signal transmission, efficiently and reliably transmitting data units to other cores through actual physical connections (such as microbumps), thereby realizing interconnection and communication between cores.
[0031] The physical layer may include one or more modules, which can be physically independent and fully functional UCIe interface units. These modules may contain a complete set of mainband channels, sideband channels, clock, and power supplies, capable of independently operating a complete UCIe protocol stack (from the physical layer to the adaptation layer) to establish and maintain a complete die-to-die (D2D) link. In this way, the physical layer can implement functions such as signal transmission, link training, clock distribution, and power management.
[0032] The UCIe protocol can use a layered link state machine (LSM) for link training. For example, it can be divided into three layers: the FDI state machine between the protocol layer and the adaptation layer, the RDI state machine between the adaptation layer and the physical layer, and the link training state machine (LTSM) of the physical layer.
[0033] The Link Training State Machine (LTSM) is responsible for managing the link training process within the physical layer. Figure 2 This is a schematic diagram of a physical layer link training state machine (LTSM) according to an embodiment of this disclosure. Figure 2As shown, the physical layer link training process based on LTSM can be sequentially divided into: RESET state → Sideband Initialization (SBINIT) state → Mainband Initialization (MBINIT) state → Mainband Training (MBTRAIN) state → Link Initialization (LINKINIT) state → ACTIVE state. Furthermore, if a link quality degradation or other reasons requiring retraining are detected in the ACTIVE state, the system can enter the physical layer retraining state (PHYRETRAIN). If an anomaly occurs in any state, the system can also enter the training error state (TRAINERROR) and re-enter the LTSM reset state. In the ACTIVE state, the system also supports a low-power management mechanism. When the system needs to reduce power consumption, it can enter Link State 1 (L1) or Link State 2 (L2). L1 is a mild low-power state, entered autonomously by the physical layer. The sideband and main band clocks remain running, and the data path logic is kept powered, with an exit latency of less than 1 microsecond. L2 is a deep low-power state, entered through coordination between the protocol and physical layers. The sideband clock remains running while the main band clock and most data path logic are powered down, with an exit latency of less than 4 microseconds. The entry and exit of low-power states are controlled by the system's power management strategy, with state negotiation conducted through the sideband channel. Physical layer link training can be triggered from either L1 or L2. For example, L1 can trigger link training starting from the main band training state, while L2 can trigger link training starting from the LTSM reset state.
[0034] The RDI state machine maps the complex link training states within the physical layer to macroscopic states that can be recognized by the adaptation layer. These include states such as: Reset, Active, Retrain, LinkError, Disabled, Link Reset, Active.PMNAK (power management rejection in the active state), and L1 and L2 states. Conversely, the FDI state machine reports the internal states of the adaptation layer to the protocol layer, enabling the layer-by-layer propagation of link states. The states and transition relationships contained in the FDI state machine are essentially the same as those in the RDI state machine, and will not be elaborated upon here. In this disclosure, the LTSM reset state is referred to as the LTSM reset state, and the RDI state machine reset state is referred to as the RDI reset state.
[0035] In related technologies, UCIe link fault repair mainly has two modes. The first mode is physical layer retraining. When a degradation in link signal quality is detected, the physical layer initiates retraining, and the LTSM transitions from the PHYRETRAIN state to the MBTRAIN state, thus skipping the sideband initialization (SBINIT) and main band initialization (MBINIT) steps, and only retraining the link signal adaptation parameters. This mode is suitable for mild link degradation scenarios. The second mode is full link reset. If the link cannot be restored after multiple retraining attempts, a full reset of the protocol layer, adaptation layer, and physical layer will be triggered, while the data in the Retry Buffer will be cleared and the link will be restarted.
[0036] For Retrain mode, since the physical layer skips the SBINIT and MBINIT steps, in scenarios with severe link signal attenuation or significant noise interference, link recovery through signal training alone is insufficient, resulting in a low success rate. While full-link reset mode can completely repair link faults, it typically suffers from an excessively broad reset range. Even if only the physical layer fails, a full three-layer reset is triggered, causing data in the Retry Buffer to be cleared, incomplete transactions to be lost, and requiring the upper layer to retransmit data after the reset, thus reducing bandwidth utilization.
[0037] To address the problems of related technologies, this disclosure introduces a physical layer reset mode with a coverage range between physical layer retraining and full-link reset. In physical layer reset mode, only the physical layer is reset, while the protocol layer and adaptation layer do not require reset. Thus, in most fault scenarios, activating physical layer reset mode is sufficient to repair the link fault without requiring a full-link reset, thereby reducing the cost of repairing the link fault.
[0038] The following will combine Figure 1 computing systems and Figure 2 The Link Training State Machine (LTSM) is used to illustrate various embodiments of this disclosure.
[0039] <First Embodiment> Figure 3 A flowchart illustrating a link failure repair method according to some embodiments is shown. Figure 3 The method steps shown are implemented by a controller of the first general-purpose chip interconnect interface of the first chip 1100, which includes a protocol layer and an adaptation layer. The first chip 1100 can be any chip in a computing system. Figure 3 As shown, the method of this embodiment may include the following steps S310 and S320.
[0040] Step S310: In response to the occurrence of a set first reset event, execute the first reset process corresponding to the physical layer reset mode.
[0041] In this embodiment, the physical layer reset mode is set to: the physical layer performs a reset operation in this mode, while the protocol layer and the adaptation layer do not need to perform a reset operation in this mode.
[0042] In this embodiment, the first reset process may include: the controller suspending the transmission of new data and driving the physical layer to switch from the LTSM reset state to the LTSM active state through full link training; and retaining the configuration parameters negotiated by the adaptation layer and the data in the retry cache of the adaptation layer.
[0043] With the addition of a physical layer reset mode, a physical layer reset state (PHY Reset) can be added to the existing states of the RDI and FDI state machines. This allows for collaborative operation of each layer under the physical layer reset mode based on state reporting. The protocol layer, adaptation layer, and physical layer of the general-purpose interconnect interface are all configured to support the physical layer reset mode, enabling physical layer reset to be completed according to the first reset procedure of the corresponding physical layer reset mode.
[0044] Taking the RDI state machine as an example, such as Figure 4 As shown, in this embodiment, the RDI state machine retains the original Reset, LinkError, Disabled, LinkReset, Active, L1, Retrain, and L2 states, and also adds a PHY Reset state. Specifically, after exiting the LinkError, Disabled, or LinkReset states, or after exiting the domain reset (Domain Reset Exit), the RDI state machine enters the Reset state. Entering the Reset state triggers the adaptation layer and protocol layer to perform reset operations; at this time, the scope of the reset covers the protocol layer, adaptation layer, and physical layer.
[0045] Unlike the Reset state, the PHY Reset state can be entered directly from any other state without going through the Reset state; instead, it routes directly to the Active state. Therefore, when the physical layer reports the PHY Reset state, it does not trigger the controller containing the protocol layer and adaptation layer to perform a reset operation. Instead, it retains the configuration parameters negotiated by the adaptation layer and the data in the retry cache.
[0046] To ensure compatibility with existing designs, the RDI state machine can fully retain the original state transition logic, only adding a new state transition path from the PHYReset state to the Active state.
[0047] In some examples, the first reset event may include the physical layer retraining failing a set number of times. For example, when the link is not restored after three retraining attempts, such as when the physical link bit error rate still exceeds a first preset threshold after three retraining attempts, the first reset event is determined to have occurred.
[0048] In other examples, the physical layer reset mode can be triggered directly without retraining. In this case, the first reset event may include: the physical link bit error rate exceeding a second preset threshold, where the second preset threshold may be greater than the first preset threshold for triggering retraining.
[0049] In some other examples, multiple first reset events can be configured, such as the number of physical layer retraining failures reaching a set number, the physical link bit error rate exceeding a second preset threshold, etc. Any event can trigger a physical layer reset.
[0050] In some examples, the controller can send a first reset request to the physical layer via a reserved code for the state request signal (lp_state_req) in the UCIe specification, triggering a physical layer reset. Correspondingly, the physical layer can report a first state signal via the same reserved code for the state indication signal (pl_state_sts) in the UCIe specification, indicating that it has entered a physical layer reset, i.e., the RDI state machine is in the PHY Reset state. Here, lp_state_req is the state request signal sent from the adaptation layer to the physical layer to request a change in link state; pl_state_sts is the state indication signal sent from the physical layer to the adaptation layer to report the current link state.
[0051] In the UCIe specification, status request signals and status indication signals are used as RDI control signals, employing 4-bit binary encoding. Part of this binary encoding is reserved and unused. In this example, any reserved encoding can be selected to represent a physical layer reset; for example, the PHY Reset state can be defined as 4'b1111. In this example, by reusing the existing lp_state_req and pl_state_sts signal lines and utilizing the reserved encoding to transmit the first reset request and the first status signal, information exchange between the controller and the physical layer can be achieved without modifying the hardware structure, thus simplifying the implementation.
[0052] In this embodiment, under physical layer reset mode, the physical layer will enter the LTSM reset state to perform a physical layer reset operation, including performing sideband initialization and main band initialization on the physical layer. For example... Figure 2As shown, the LTSM state machine starts from the Reset state and sequentially goes through the SBINIT, MBINIT, MBTRAIN, and LINKINIT link training steps before finally jumping to the Active state. Unlike retraining, physical layer reset, by executing the complete SBINIT and MBINIT steps, can effectively improve the success rate of repairing severely degraded links.
[0053] Step S320: After the physical layer reset is completed through the first reset process, the data in the transmission retry buffer is restored based on the configuration parameters negotiated by the controller and the link parameters obtained by the physical layer through complete link training.
[0054] In this embodiment, the physical layer reset mode is a partial reset mode in which only the physical layer is reset. In the physical layer reset mode, since the configuration parameters negotiated by the controller are not affected by the physical layer reset, the controller will retain the negotiated configuration parameters and the data in the retry buffer. The configuration parameters are logical service information determined by the inter-layer negotiation, reflecting the logical service capabilities of the interface. They are determined by negotiation between the local controller and the controller of the second general-purpose chip interconnect interface, and include one or more of the following: protocol type, data frame encapsulation format (e.g., Flit format), retransmission mechanism enable, physical layer reset enable, low-power state support, etc. Therefore, after the physical layer reset is completed through the first reset process, the controller can directly restore the data stored in the transmission retry buffer based on its own negotiated configuration parameters and the link parameters obtained after the physical layer reset, without having to re-negotiate the above configuration parameters with the interconnected second general-purpose core interconnect interface. The link parameters are the underlying transmission characteristic parameters of the link negotiated and configured by the physical layer, reflecting the physical transmission characteristics of the interface. They are determined by the local physical layer during complete link training in negotiation with the physical layer of the interconnected second general-purpose core interconnect interface and reported to their respective controllers. Link parameters may include one or more of the following: link speed, link width, clock configuration, channel equalization parameters, etc. In this embodiment, link fault repair can be achieved through physical layer reset, thereby enabling data transmission to be restored using the configuration parameters negotiated by the controller beforehand and the link parameters negotiated by the physical layer during link initialization.
[0055] After the physical layer reset is complete, the controller can resend the data in the retry buffer in transaction order to ensure that data consistency is not compromised. Both ends of the UCIe link use a retry buffer mechanism to ensure the consistency and reliability of data transmission.
[0056] In some examples, the first general-purpose interconnect interface and the interconnected second general-purpose interconnect interface can be synchronously reset at the physical layer to ensure that the link states at both ends are consistent, avoiding state confusion or data loss due to asynchronous resets. After both parties confirm through a handshake that they are in a state where data transmission can proceed, the data stored in the transmission retry buffer is restored, thereby ensuring the reliability of link recovery and data integrity, and preventing data jams or transmission blockages.
[0057] In this example, step S320 may further include: after confirming that both the first general-purpose core interconnect interface and the interconnected second general-purpose core interconnect interface have completed physical layer reset, restoring the data in the transmission retry buffer based on the configuration parameters and the link parameters obtained by the physical layer through complete link training.
[0058] In this example, the physical layer reset of the second general-purpose interconnect interface (GPII) can be triggered by the physical layer of the first GPII sending a sideband message to the physical layer of the second GPII via a sideband link, thereby simplifying cross-interface reset coordination. For example, after receiving a first reset request, the physical layer of the first GPII can send a message triggering the physical layer reset to the physical layer of the second GPII via a sideband link, so that both ends synchronously enter the physical layer reset state.
[0059] In this example, after the physical layer of the first general-purpose interconnect interface completes link training and enters the active state, it can handshake with the physical layer of the second general-purpose interconnect interface to confirm that the other party has also entered the active state, and then drive the RDI state machine to jump to the Active state. In this way, when the controller detects that the state indication signal (pl_state_sts) changes to Active, it can confirm that both parties have completed the physical layer reset.
[0060] In this example, the physical layer of the first general-purpose chip interconnect interface can also directly drive the RDI state machine to jump to the Active state after entering the active state; then, the controller's adapter layer and the adapter layer of the peer (the second general-purpose chip interconnect interface) handshake to confirm that both parties are in the Active state, that is, to confirm that both parties have completed the physical layer reset.
[0061] This embodiment adds a physical layer reset mode to the UCIe protocol. This mode only resets the physical layer, allowing the controller to continue operating normally without data loss, providing greater compatibility and flexibility for UCIe physical links in complex fault scenarios. Because data in the retry buffer is retained during the physical layer reset process, there is no need for upper-layer retransmission of incomplete transactions after the reset is complete, thus significantly improving bandwidth utilization and system response speed. Compared to traditional full-link reset (which typically results in bandwidth interruptions on the order of hundreds of milliseconds), the physical layer reset mode in this embodiment can shorten link interruption time to the microsecond level (e.g., no more than 50μs), effectively reducing the impact on chip operation and improving system availability.
[0062] <Second Embodiment> Figure 5 A link fault repair method according to some other embodiments is illustrated. Unlike the first embodiment, in this embodiment, the first general-purpose interconnect interface supports both physical layer reset mode and full-link reset mode, and can connect to either a second general-purpose interconnect interface that supports physical layer reset mode or a second general-purpose interconnect interface that does not support physical layer reset mode. Figure 5 As shown, the method in this embodiment includes the following steps S500 to S530.
[0063] In step S500, in response to the occurrence of the first reset event, determine whether the physical layer reset mode is enabled. If so, proceed to step S510; otherwise, proceed to step S530.
[0064] Step S510: If the physical layer reset mode is enabled, perform the first reset process corresponding to the physical layer reset mode, and then perform step S520.
[0065] Step S520: After the physical layer reset is completed through the first reset process, the data in the transmission retry buffer is restored based on the configuration parameters negotiated by the controller and the link parameters obtained by the physical layer through complete link training.
[0066] Step S530: If the physical layer reset mode is disabled, perform the second reset process corresponding to the full-link reset mode.
[0067] In some examples, the enable state of the physical layer reset mode can be determined through configuration parameter negotiation with the second general-purpose core interconnect interface of the interconnect.
[0068] In this example, the method further includes: before step S500 in response to the occurrence of a set first reset event, determining whether the second general-purpose interconnect interface supports a physical layer reset mode by negotiating parameters with the interconnected second general-purpose interconnect interface; if the second general-purpose interconnect interface supports the physical layer reset mode, then enabling the physical layer reset mode; if the second general-purpose interconnect interface does not support the physical layer reset mode, then disabling the physical layer reset mode. Thus, if both general-purpose interconnect interfaces at both ends support the scheme of this embodiment, physical layer reset is performed normally. If only one general-purpose interconnect interface supports it, it automatically degrades to a full-link reset, achieving compatibility with existing general-purpose interconnect interfaces.
[0069] The above parameter negotiation can be conducted through the adaptation layers of the two interfaces. The adaptation layers negotiate configuration parameters using the capability declaration (AdvCap) and final confirmation (FinCap) mechanisms defined in the UCIe standard: The adaptation layer of the first general-purpose interconnect interface declares its support for physical layer reset mode in the capability field of the {AdvCap.Adapter} message; upon receiving this message, the adaptation layer of the second general-purpose interconnect interface sets the corresponding bit in its response if it also supports this mode; otherwise, it does not set the bit; the adaptation layer of the first general-purpose interconnect interface finally confirms the configuration based on the intersection of the capabilities of both parties through the {FinCap.Adapter} message. If both parties support it, the physical layer reset mode is enabled; otherwise, it is disabled and automatically downgrades to full-link reset mode, thus achieving backward compatibility with existing general-purpose interconnect interfaces.
[0070] <Third Embodiment> Figure 6 A link failure repair method according to some other embodiments is illustrated. Building upon the first embodiment, this embodiment, after a physical layer reset failure, can enter a full-link reset mode to completely resolve the link failure. For example... Figure 6 As shown, the method of this embodiment includes the following steps S610 and S630: Step S610: In response to the occurrence of a set first reset event, execute the first reset process corresponding to the physical layer reset mode.
[0071] Step S630: In response to the second reset event of physical layer reset failure, execute the second reset process corresponding to the full-link reset mode to complete the full-link reset.
[0072] The second reset process may include: the controller performing a reset operation and clearing the data in the retry buffer; and driving the physical layer to perform a state transition from the LTSM reset state to the LTSM active state through full link training.
[0073] In this embodiment, the full-link reset mode can be started immediately after a physical layer reset fails once, or the full-link reset mode can be started after the physical layer reset has been executed a set number of times.
[0074] In this embodiment, physical layer reset failure includes: after completing the physical layer reset, the first general-purpose interconnect interface resumes transmission of data in the retry buffer, or the physical link bit error rate still exceeds the first preset threshold when transmitting new service data. Physical layer reset failure may also include failure to successfully complete the physical layer reset.
[0075] In this embodiment, based on the second reset event, a full-link reset operation is performed on the physical layer, adaptation layer, and protocol layer, and the data in the retry cache is cleared.
[0076] According to the UCIe specification, the controller can request a full-link reset by setting the status request signal to code 4'b0000, and determine that the physical layer has entered a full-link reset by monitoring the physical layer to set the status indication signal to code 4'b0000. The controller will then perform a reset operation, including clearing the controller's negotiated configuration parameters and data in the retry cache. The three layers work together to complete the full-link reset.
[0077] In this embodiment, the controller's adaptation layer can determine the required operation based on the encoded value of pl_state_sts of the RDI interface. If the encoded value is 4'b0000, which represents the Reset state specified by the UCIe protocol, the data in the retry buffer will be cleared. If the encoded value of pl_state_sts is 4'b1111, indicating a physical layer reset, the data in the retry buffer will not be cleared, but the retry-related logic can be restored to its initial state.
[0078] <Fourth Embodiment> This embodiment provides a reset process for the corresponding physical layer reset mode.
[0079] In this embodiment, the first reset process implemented by the controller may include: the controller sending a first reset request to the physical layer requesting the physical layer to reset (e.g., setting the lp_state_req signal of the RDI interface to the PHY_Reset state); and, according to the pause request signal (pl_stallreq) sent by the physical layer based on the first reset request, pausing the transmission of new data at the link boundary, and returning a pause acknowledgment signal lp_stateack to the physical layer, triggering the physical layer to enter the LTSM reset state.
[0080] In this embodiment, the first reset process may further include: controlling the first state signal of the physical layer reset that has been initiated based on the physical layer report (e.g., setting the pl_state_sts signal of the RDI interface to the PHY_Reset state), and retaining the configuration parameters negotiated by the controller and the data in the retry buffer.
[0081] Correspondingly, the physical layer reset process for the physical layer reset mode may include: in response to the first reset request, sending a pause request signal (pl_stallreq) to the controller; initiating a physical layer reset based on the pause acknowledgment signal (lp_stateack) returned by the controller based on the pause request signal, performing a state transition from the LTSM reset state to the active state via full link training, and reporting a first state signal to the controller, triggering the controller to retain its negotiated configuration parameters and data in the retry cache based on the first state signal.
[0082] Furthermore, the physical layer initiating a physical layer reset and performing a state transition from the LTSM reset state to the active state via full link training may also include: when the physical layer ends the LTSM reset state, determining whether it has received a first activation request sent by the controller to request activation; if the first activation request is received, switching from the LTSM reset state to the LTSM active state via full link training.
[0083] In this embodiment, after receiving the first reset request, the physical layer first initiates the pause handshake process (pl_stallreq / lp_stallack) of the RDI interface, and then initiates the physical layer reset. This ensures that the adaptation layer stops sending new data during the reset process, thereby effectively avoiding data loss. Simultaneously, after detecting the first status signal reported by the physical layer, the controller executes the physical layer reset operation corresponding to the adaptation layer and the protocol layer, enabling the controller and physical layer to coordinate their actions, further improving the reliability and consistency of the reset process.
[0084] Figure 7 This diagram illustrates an optional interaction flow for physical layer reset using the UCIe interface according to this embodiment. Figure 7 In this context, the first general-purpose chip interconnect interface corresponds to the first chip die1, and the second general-purpose chip interconnect interface corresponds to the second chip die2. For example... Figure 7 As shown, the process of performing a physical layer reset by the first general-purpose chip interconnect interface may include the following steps: (1) When the protocol layer of Die1 detects the first reset event, it triggers the physical layer reset (PHY Reset) mode, sets the lp_state_req signal of the FDI interface to the PHY_Reset state, and notifies the adaptation layer of Die1.
[0085] (2) After the Die1 adapter layer detects that the lp_state_req signal of the FDI interface is set to the PHY_Reset state, it also sets the lp_state_req signal of the RDI interface to the PHY_Reset state and passes the first reset request to the physical layer.
[0086] (3) After the physical layer of Die1 detects that the lp_state_req signal of the RDI interface is set to the PHY_Reset state, it starts the pause handshake process of the RDI interface (pl_stallreq / lp_stallack) to ensure that the adaptation layer pauses sending new data at the link boundary during the physical layer reset process, thus avoiding data loss.
[0087] (4) The physical layer of Die1 sends the physical layer reset information to the physical layer of Die2 through the sideband link, triggering the other end to also start the physical layer reset.
[0088] (5) After the physical layer of Die2 receives the physical layer reset information through the sideband link, it also performs pl_stallreq / lp_stallack to pause the handshake on the local RDI interface.
[0089] (6) After completing the pause handshake on their respective ends, the physical layers of Die1 and Die2 each jump the LTSM state machine to the RESET state and set the pl_state_sts signal of the RDI interface to the PHY_Reset state to confirm that the physical layer reset is in progress.
[0090] When the Die1 and Die2 adapter layers detect that the pl_state_sts signal of the RDI interface is set to the PHY_Reset state, they do not perform a reset operation and retain the configuration parameters and data in the retry buffer.
[0091] (7) After the Die1 adaptation layer detects that the pl_state_sts of the RDI interface is set to PHY_Reset, it sets the lp_state_req signal of the RDI interface to the Active state, indicating that the adaptation layer is ready to restore the link.
[0092] (8) After the physical layer of Die1 detects that lp_state_req of the RDI interface is set to Active, it performs link training from SBINIT to LINKINIT.
[0093] (9) The physical layers of Die1 and Die2 perform link training handshake through the sideband link, so that the physical layer of Die2 also performs link training, and negotiates and determines the link parameters when the link training enters the link initialization state.
[0094] (10) After the physical layer of Die1 completes the link training, it shakes hands with the physical layer of Die2 to confirm that both sides have completed the link training.
[0095] (11) After the physical layers of Die1 and Die2 complete the link training, they will switch the pl_state_sts signal of the RDI interface from PHY_Reset back to the Active state.
[0096] (12) The protocol layer and adaptation layer of Die1 and Die2 respectively detected pl_state_sts = Active through the RDI interface and FDI interface, confirming that the physical layer reset process was completed and the link resumed normal communication.
[0097] The above interaction process achieves a reliable closed loop for physical layer reset through dual-end collaboration.
[0098] <Fifth Embodiment> This disclosure provides a controller based on a generic core interconnect protocol, configured to execute a link fault repair method according to any embodiment of this disclosure.
[0099] The controller comprises a protocol layer and an adaptation layer based on the Universal Core Interconnect Protocol (UCIe). The protocol layer is responsible for UCIe protocol parsing, session management, and flow control, while the adaptation layer is responsible for protocol conversion, data caching, and retry mechanisms. The protocol layer and the adaptation layer can interact via the FDI interface.
[0100] In some examples, the controller may include a reset type determination module located in the adaptation layer. This reset type determination module is used to monitor the status indication signal of the RDI and determine the reset type based on the status indication signal. When the reset type is determined to be a physical layer reset, the controller retains the negotiated configuration parameters and data in the retry cache without performing a reset operation. When the reset type is determined to be a full-link reset, a reset operation is performed, clearing the negotiated configuration parameters and data in the retry cache, etc.
[0101] This disclosure also provides a universal chip interconnect interface, such as Figure 8 As shown, the universal chip interconnect interface 800 includes a controller 810 according to the fifth embodiment, and a physical layer 820 capable of responding to physical layer reset. The controller 810 includes a protocol layer and an adaptation layer.
[0102] In this embodiment, the physical layer's ability to respond to a physical layer reset includes: the physical layer being able to identify a first reset request corresponding to a physical layer reset mode, and setting the status indicator signal of the RDI interface to a first status signal indicating a physical layer reset.
[0103] <Sixth Embodiment> This disclosure also provides a chip that may include a universal chip interconnect interface 800 according to embodiments of this disclosure. The chip is, for example, a... Figure 1 The first core 1100 or the second core 1200 of the computing system 1000.
[0104] This disclosure also provides a computing system that may include multiple chips. Exemplarily, the computing system may be... Figure 1 The computing system 1000 shown can be a system that includes computing devices such as GPUs, GPGPUs, NPUs, or TPUs.
[0105] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0106] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and apparatuses according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, unit, or part of a circuit. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, or they may sometimes be executed in reverse order, depending on the functions involved. It should be noted that embodiments of the present disclosure may include some or all of the functions marked in the multiple blocks in the drawings, and may also include other functions not shown in the blocks in the drawings. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented in hardware that performs the specified function or action, or in a combination of dedicated hardware and computer instructions. Unless otherwise specified, implementation in hardware, implementation in software, and implementation in a combination of software and hardware may be equivalent.
[0107] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, and are not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein. The scope of this disclosure is defined by the appended claims.
Claims
1. A link fault repair method, characterized in that, A controller applied to a first universal interconnect interface, the first universal interconnect interface including the controller and a physical layer driven by the controller, the method comprising: In response to the occurrence of a set first reset event, a first reset process corresponding to the physical layer reset mode is executed; wherein, the first reset process includes: pausing the transmission of new data, driving the physical layer to switch from the reset state to the active state through full link training, and retaining the configuration parameters negotiated by the controller and the data in the retry cache; After the physical layer reset is completed through the first reset process, the data in the retry buffer is resumed based on the configuration parameters and the link parameters obtained by the physical layer through the complete link training.
2. The method according to claim 1, characterized in that, The method further includes: In response to a second reset event that fails to reset the physical layer, the second reset process corresponding to the full-link reset mode is executed to complete the full-link reset. The second reset process includes: performing a reset operation and clearing the data in the retry cache; and driving the physical layer to perform the state transition.
3. The method according to claim 1, characterized in that, The first reset event includes the number of physical layer retraining failures reaching a set number.
4. The method according to claim 1, characterized in that, The first reset process corresponding to the physical layer reset mode is executed in response to the occurrence of a predetermined first reset event, including: In response to the occurrence of a predefined first reset event, determine whether the physical layer reset mode is enabled; When the physical layer reset mode is enabled, the first reset process is executed; When the physical layer reset mode is disabled, a second reset process corresponding to the full-link reset mode is executed; wherein, the full-link reset mode is a reset mode in which both the controller and the physical layer are reset.
5. The method according to claim 4, characterized in that, The method further includes responding before a predetermined first reset event occurs: By negotiating configuration parameters with the second general-purpose core interconnect interface, it is determined whether the second general-purpose core interconnect interface supports the physical layer reset mode; If the second general-purpose chip interconnect interface supports the physical layer reset mode, then enable the physical layer reset mode; If the second general-purpose chip interconnect interface does not support the physical layer reset mode, then the physical layer reset mode is disabled.
6. The method according to claim 1, characterized in that, After the physical layer reset is completed through the first reset process, the step of restoring the transmission of the data in the retry buffer based on the configuration parameters and the link parameters obtained by the physical layer through the complete link training includes: After confirming that both the first general-purpose core interconnect interface and the interconnected second general-purpose core interconnect interface have completed the physical layer reset, the data in the retry buffer is resumed based on the configuration parameters and the link parameters obtained by the physical layer through the complete link training. The physical layer reset of the second general-purpose chip interconnect interface is triggered by the physical layer of the first general-purpose chip interconnect interface sending a sideband message to the physical layer of the second general-purpose chip interconnect interface via a sideband link.
7. The method according to any one of claims 1 to 6, characterized in that, The step of pausing the transmission of new data and driving the physical layer to switch from a reset state to an active state after full link training includes: Send a first reset request to the physical layer requesting a physical layer reset; Based on the pause request signal sent by the physical layer based on the first reset request, the transmission of new data at the link boundary is paused, and a pause confirmation signal is returned to the physical layer, triggering the physical layer to enter the reset state; The retention of the negotiated configuration parameters of the controller and the data in the retry cache includes: Based on the first status signal reported by the physical layer indicating that the physical layer reset has been initiated, the configuration parameters negotiated by the controller and the data in the retry cache are retained; wherein, the first status signal is reported by the physical layer when entering the reset state.
8. The method according to claim 7, characterized in that, The controller sends the first reset request through the reserved code of the status request signal of the bare die inter-particle interface, and the physical layer reports the first status signal through the reserved code of the status indication signal of the bare die inter-particle interface.
9. The method according to claim 7, characterized in that, The process of driving the physical layer to switch from a reset state to an active state through complete link training also includes: Upon receiving the first state signal, a first activation request is sent to the physical layer to request activation; wherein, the first activation request is used to trigger the physical layer to switch from the reset state to the activated state through full link training; Based on the second state signal reported by the physical layer indicating that the physical layer is in an active state, the physical layer reset is confirmed to be complete.
10. A controller based on a universal chip interconnect protocol, characterized in that, The controller is configured to perform the method of any one of claims 1 to 9.
11. A universal chip interconnect interface, characterized in that, It includes the controller as described in claim 10 and a physical layer capable of responding to physical layer reset.
12. A core element, characterized in that, The core is configured with the universal core interconnect interface as described in claim 11.
13. A computing system, characterized in that, It includes multiple cores as described in claim 12.