Test vector automatic generation method

By automatically generating ATE test vectors on the VCS simulation platform, the problems of low efficiency, poor accuracy, and insufficient versatility in chip test vector generation are solved. This achieves efficient and accurate test vector generation, adapts to different test platforms and products, simplifies the programming process, and reduces costs.

CN122152606APending Publication Date: 2026-06-05SHANGHAI HUAHONG INTEGRATED CIRCUIT
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
SHANGHAI HUAHONG INTEGRATED CIRCUIT
Filing Date
2026-01-23
Publication Date
2026-06-05

AI Technical Summary

Technical Problem

Existing technologies suffer from low efficiency, poor accuracy, and insufficient versatility in generating chip test vectors, making it difficult to adapt to the testing needs of different ATE test platforms, product series, and various packaging forms. This results in cumbersome test program writing, low integration, and high costs.

Method used

Based on test cases, ATE test vectors are automatically generated on the VCS simulation platform. By writing test cases, performing simulation timing checks, linking scripts, and optimizing conversions, the automatic generation of test vectors is achieved, ensuring timing accuracy and comprehensive coverage, and adapting to different test platforms and products.

Benefits of technology

It improves the efficiency and accuracy of test vector generation, simplifies the writing process, enhances versatility, reduces the probability of errors caused by manual intervention, shortens the testing cycle, and reduces costs.

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Abstract

The application discloses a kind of test vector automation generation methods, which generates test vector based on test case, comprising: S1, writing test case, writing test case in simulation platform, the full coverage simulation verification of function and performance to chip circuit, confirm chip timing correct, provide basis for the script of link vector generation;S2, simulation timing check, write automation vector generation script, test clock cycle, test timing, the input state of all pins, input excitation, output state and expected output value are defined in the script;S3, link script, link test case in automation vector generation script, run simulation in simulation platform, automatically generate the test vector of specified format when simulation ends, the test vector reflects the input and output state of pin with clock cycle change in simulation process;S4, conversion or optimization is carried out to test vector, forms different test platform special vector format, and test vector is debugged and verified in test system.
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