Finfet circuit anti-single event upset layout optimization method based on charge sharing analysis

Abstract

The application discloses a FinFET circuit anti-single event upset layout optimization method based on charge sharing analysis and belongs to the field of integrated circuit radiation effect and anti-radiation reinforcement technology. The method comprises the following steps: calibrating a FinFET device model and determining a single tube sensitive volume through TCAD simulation; analyzing a target circuit to determine a sensitive node and generate an initial layout; constructing a Geant4 circuit model based on the initial layout, locating the sensitive node to determine the circuit sensitive volume distribution; through Monte Carlo simulation, the charge sharing probability two-dimensional distribution graph between the sensitive volumes of adjacent transistors is counted and generated; the layout is iteratively changed to repeat the simulation, and the layout layout which is more conducive to reducing the single event upset risk under the controllable area cost is selected as the optimization scheme. The application realizes the quantitative evaluation of the charge sharing between the sensitive volumes of the FinFET circuit transistor, and provides efficient guidance for the layout-level anti-single event upset reinforcement.

Description

Technical Field

[0001] This invention belongs to the field of radiation effects and radiation hardening technology of integrated circuits, and specifically relates to a layout optimization method for FinFET circuits to resist single-event upsets based on charge sharing analysis. Specifically, it relates to a layout optimization method to improve the single-event upset performance of FinFET circuits by quantitatively evaluating the charge sharing effect. Background Technology

[0002] Compared to traditional planar metal-oxide-semiconductor field-effect transistors (MOSFETs), FinFET devices offer higher drive current and lower leakage current, combining high performance with low power consumption. They are widely used in high-performance computing, mobile communications, and IoT terminals. In recent years, with the increasing demand for intelligent deep space exploration and nuclear energy equipment, FinFET technology has gradually expanded into high-radiation environments such as aerospace and nuclear industries. In these applications, radiation particles can easily cause performance degradation or even permanent functional failure of semiconductor devices; therefore, the radiation reliability of FinFET devices and circuits has become a key challenge for the widespread application of this technology.

[0003] Statistics released by the U.S. Nuclear and Space Radiation Effects Conference indicate that single-event effects (SEE) are a major cause of failures in spacecraft electronic systems. Among these, single-event upsets (SEEs), a typical manifestation of SEEs, can cause abnormal switching of circuit logic states. In FinFET circuits, high integration significantly reduces the spacing between sensitive nodes. The charge generated by a single radiated particle is more easily collected by multiple neighboring sensitive nodes through mechanisms such as lateral diffusion, well barrier modulation, and parasitic bipolar amplification, resulting in a significant charge-sharing effect. This effect may exacerbate or mitigate the SEE risk at sensitive nodes, impacting the radiation reliability of the circuit.

[0004] Traditional hardening methods to resist single-event upsets (such as redundant design and hardened cells) often come at the cost of area, speed, and power consumption. At the layout level, hardening typically relies on empirical rules (such as increasing the spacing between sensitive nodes), lacking quantitative evaluation methods for specific circuit structures and radiation environments. In particular, the three-dimensional architecture of FinFET technology makes the charge collection mechanism more complex, significantly limiting the effectiveness of empirical rules.

[0005] Therefore, there is an urgent need to develop a method that can accurately quantify and evaluate the charge sharing effect of FinFET circuits and directly guide layout optimization. Summary of the Invention

[0006] The purpose of this invention is to provide a FinFET circuit layout optimization method based on charge sharing analysis to resist single-event upsets. This method can simulate the interaction between radiating particles and circuit materials, quantitatively assess the charge sharing risk, and provide layout optimization suggestions.

[0007] To address the aforementioned technical problems, this invention provides a FinFET circuit layout optimization method based on charge-sharing analysis. The method uses Geant4 simulation to quantify and evaluate the charge-sharing effect between transistor sensitive volumes in the circuit layout, thereby optimizing the circuit's resistance to single-event upsets. The method includes: Step S1: Calibrate the FinFET device model using TCAD simulation and determine the single-tube sensitive volume; Step S2: Analyze the target circuit to identify sensitive nodes and generate an initial layout; Step S3: Construct a Geant4 circuit model based on the initial layout, locate sensitive nodes and determine the sensitive volume distribution of the circuit; Step S4: Statistically analyze and generate a two-dimensional distribution map of charge sharing probability among sensitive volumes of adjacent transistors using Monte Carlo simulation; Step S5: Iteratively change the layout and repeat the simulation. Select the layout that is more conducive to reducing the risk of single-event flip under the controllable area cost.

[0008] Preferably, step S1 specifically includes: Step S11: Based on TCAD software, construct a three-dimensional device model according to the FinFET process parameters, simulate the electrical characteristics of the device, and complete the model calibration by comparing with the experimental test results; Step S12: Set the FinFET device to the bias state most sensitive to single-event upset, simulate the single-event transient current pulse generated in different regions of the single-event incident device, and determine the sensitive volume of the FinFET device based on the pulse amplitude distribution.

[0009] Preferably, during the TCAD simulation, the FinFET device is set to the off state, and a reverse-biased PN junction is formed between the drain and the substrate. This is the bias state most sensitive to single-event upsets. During TCAD simulation, a single particle is incident on different regions of the device along a direction perpendicular to the device surface. The corresponding single-particle transient current pulse is extracted, and the sensitive volume of the single-tube device is defined based on the pulse amplitude distribution.

[0010] Preferably, step S2 specifically includes: Step S21: Analyze the target circuit schematic and determine the key circuit nodes that are sensitive to single-event upsets; Step S22: Based on the target circuit schematic, generate an initial transistor layout using the Cadence Virtuoso platform.

[0011] Preferably, step S3 specifically includes: Step S31: Based on the Geant4 toolkit, construct a three-dimensional circuit model according to the FinFET process parameters, the FinFET process flow, and the generated initial layout. Step S32: In the constructed three-dimensional circuit model, locate the key circuit nodes that are sensitive to single-particle flip and the transistors that affect the key nodes, and map the determined single-transistor sensitive volume to the transistor to form the overall sensitive volume distribution of the circuit.

[0012] Preferably, when constructing the three-dimensional circuit model, the layered structure of the FinFET process is referenced, including the substrate, shallow trench isolation, fin structure, gate dielectric, gate, source / drain regions, metal interconnect layer, and passivation layer, to ensure that the model geometry is consistent with the process parameters.

[0013] Preferably, step S4 specifically includes: In the Geant4 simulation, the particle source is set to perform grid scanning emission within a region covering the sensitive volume. The number of events in which the charge generated by a single incident particle is shared by multiple neighboring transistor sensitive volumes is counted, the charge sharing probability is calculated, and a two-dimensional distribution map of the charge sharing probability is generated.

[0014] Preferably, the particles emitted by the particle source are one or more of protons, neutrons, and heavy ions, and the energy is set according to the target radiation environment.

[0015] Preferably, the generation of the two-dimensional distribution map of charge sharing probability specifically includes: dividing the particle source scanning area into a grid, counting the number of charge sharing events in each grid cell and the number of particle incident events in that cell, calculating the ratio of the former to the latter as the charge sharing probability in that cell, summarizing the charge sharing probabilities in all grid cells, and drawing a two-dimensional distribution contour map.

[0016] Preferably, step S5 specifically includes: Step S51: Change the transistor layout to generate a new layout. Repeat steps S3 to S4 to generate a two-dimensional distribution map of the probability of charge sharing between sensitive volumes of adjacent transistors under the new layout. Step S52: Compare the two-dimensional distribution diagrams of charge sharing probability under different layouts, and in combination with the layout area constraint, select the layout that is more conducive to reducing the risk of single-event upset at critical nodes and improving the overall resistance to single-event upset of the circuit under acceptable area cost, as the final optimization scheme.

[0017] Compared with the prior art, the present invention has the following beneficial effects: (1) Based on Geant4 simulation, this invention realizes the probability distribution statistics of charge sharing between sensitive volumes of circuit-level transistors, providing a quantitative basis for evaluating the anti-single-event flip performance of the layout and overcoming the limitations of traditional empirical rules. (2) By comparing and analyzing the simulation results of various layouts, this invention can summarize the transistor arrangement rules for FinFET process, form a reusable radiation-resistant layout design rule library, and improve circuit design efficiency. (3) This invention can be extended to different types of circuits, supports the generation of hardened design rules, and promotes the application of FinFET circuits in strong radiation scenarios. Attached Figure Description

[0018] Figure 1 This is a flowchart of the method of the present invention; Figure 2 A comparison of the transfer characteristic curves of a 16nm bulk silicon FinFET process NMOS device obtained from TCAD simulation and experimental testing after model calibration; Figure 3 The single-particle transient current pulse curve corresponding to the change of particle incident position along the x-axis direction in TCAD simulation; Figure 4 The single-particle transient current pulse curve corresponding to the change of particle incident position along the y-axis direction in TCAD simulation; Figure 5 A three-dimensional schematic diagram of the sensitive volume of a 16 nm bulk silicon FinFET process NMOS device, determined by TCAD simulation. Figure 6 This is a schematic diagram of the buffer circuit used in the embodiment; Figure 7 This is a schematic diagram of the initial layout of the buffer circuit; Figure 8 This is a schematic diagram of a 3D circuit model built in Geant4 based on the initial layout. Figure 9 This is a two-dimensional distribution of the charge sharing probability between the sensitive volumes of transistors N1 and N2, obtained through Geant4 simulation. Figure 10 This is a schematic diagram of the modified layout of the buffer circuit; Figure 11 A schematic diagram of a 3D circuit model built in Geant4 based on the new layout; Figure 12 This is a two-dimensional distribution of charge sharing probability between the sensitive volumes of transistors N1 and N2, obtained from Geant4 simulations for the new layout. Detailed Implementation

[0019] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0020] like Figure 1 As shown, this embodiment of the invention specifically provides a FinFET circuit layout optimization method based on charge-sharing analysis to resist single-event upsets, including the following steps: Step 1: Based on TCAD software, construct a three-dimensional device model according to the process parameters of FinFET (Fin Field-Effect Transistor), simulate the electrical characteristics of the device, and complete the model calibration by comparing with experimental test results.

[0021] Specifically, using Silvaco TCAD software, a three-dimensional model of the dual-fin NMOS device was constructed based on the 16 nm bulk silicon FinFET process parameters, and its transfer characteristic curve, i.e., leakage current ( I d )-Gate voltage ( V g The simulation curve was compared with the experimental results, and the model parameters were adjusted until the simulation curve and experimental data highly matched, thus completing the model calibration. A comparison of the calibrated TCAD simulation and experimental curves is shown below. Figure 2 As shown in Table 1, the key process parameters after model calibration are as follows.

[0022] Table 1 parameter symbol value Grid length <![CDATA[ L g ]]> 16 nm Fin height <![CDATA[ H FIN ]]> 32 nm Fin width <![CDATA[ T FIN ]]> 10 nm Source / drain doping concentration <![CDATA[ N SD ]]> <![CDATA[2×10 20 cm -3 ]]> Bulk doping concentration <![CDATA[ N B ]]> <![CDATA[1×10 17 cm -3 ]]> Step 2: Set the FinFET device to the bias state most sensitive to single-event upsets, simulate the single-event transient current pulses generated in different regions of the single-event incident device, and determine the sensitive volume of the FinFET device based on the pulse amplitude distribution.

[0023] Specifically, setting the gate voltage of the NMOS device V g = 0 V, source voltage V s = 0 V, substrate voltage V b = 0V, drain voltage V d= 0.8 V, at which point the device is in the off state, a reverse-biased PN junction is formed between the drain and the substrate, and the charge collection efficiency is the highest. This is the bias state most sensitive to single-event upsets. The linear energy transfer (LET) value is set to 10 MeV·cm. 2 Single particles of / mg are incident on different regions of the device along the z-axis (perpendicular to the device surface), and the corresponding single-particle transient current pulses are extracted. The simulation results are then normalized, such as... Figure 3 and Figure 4 As shown. Figure 3 The transient current pulse peak value is shown to be the largest at the drain and the smallest at the source when the particle incident position changes along the x-axis. Figure 4 The transient current pulse peak value is the largest at the center of the fin when the particle incident position changes along the y-axis, and is symmetrically distributed in a double-fin structure; the peak value decreases with distance from the fin.

[0024] The sensitive volume is defined as the region where a particle incident on the device can generate a significant transient current. Along the x-direction, with the boundary defined as approximately 50% of the peak value of the single-particle transient current pulse dropping to the maximum value at the drain, the sensitive volume width is 112 nm. Along the y-direction, with the boundary defined as approximately 50% of the peak value of the single-particle transient current pulse dropping to the maximum value at the fin center, the sensitive volume length is approximately 90 nm. Along the z-direction, the sensitive volume covers the entire fin height and extends approximately 500 nm into the substrate to include the sub-fin parasitic bipolar amplification region. The final three-dimensional schematic diagram of the NMOS device sensitive volume is shown below. Figure 5 As shown.

[0025] Step 3: Analyze the target circuit schematic and identify the key circuit nodes that are sensitive to single-event upsets.

[0026] Specifically, taking a buffer circuit composed of two inverters as an example, its schematic diagram is as follows: Figure 6 As shown. Nodes Q1 and Q2 are sensitive nodes that store critical logic values. The drains of transistors P1 and N1 are connected to sensitive node Q1, and the drains of transistors P2 and N2 are connected to sensitive node Q2.

[0027] Step 4: Based on the circuit schematic in Step 3, generate the initial transistor layout using the Cadence Virtuoso platform.

[0028] Specifically, the initial layout diagram of the buffer circuit generated based on the Cadence Virtuoso platform is as follows: Figure 7 As shown.

[0029] Step 5: Based on the Geant4 toolkit, construct a three-dimensional circuit model according to the FinFET process parameters, referring to the FinFET process flow and the initial layout generated in Step 4.

[0030] Specifically, referencing the layered structure of FinFET technology, including substrate, shallow trench isolation, fin structure, gate dielectric, gate, source / drain regions, metal interconnect layer, and passivation layer, to ensure that the model geometry is consistent with the process parameters, a 3D circuit model built using the Geant4 toolkit is shown below. Figure 8 As shown.

[0031] Step 6: In the circuit model constructed in step 5, locate the key circuit nodes that are sensitive to single-event upsets and the transistors that affect the key nodes, and map the radiation-sensitive volume of the single-transistor device determined in step 2 to these transistors to form the overall sensitive volume distribution of the circuit.

[0032] Specifically, the positions of sensitive nodes Q1 and Q2 are located in the circuit model, and the corresponding four transistors P1, P2, N1, and N2 are identified. The sensitive volume of the FinFET single-transistor device determined in step 2 is mapped to the four transistors to form the circuit sensitive volume distribution.

[0033] Step 7: In the Geant4 simulation, set the particle source to perform grid scanning emission within the region covering the sensitive volume, count the number of events in which the charge generated by a single particle incident is shared by multiple neighboring transistor sensitive volumes, calculate the charge sharing probability, and generate a two-dimensional distribution map of the charge sharing probability.

[0034] Specifically, Figure 7 In the buffer circuit shown, when the input signal D is low, the output Q1 of the first-stage inverter is high, and the output Q2 of the second-stage inverter (i.e., the circuit output) is low. At this time, transistor N1 is off, its drain is connected to Q1 at a high level, the substrate is grounded, and a reverse-biased PN junction is formed between the drain and the substrate, making it highly sensitive to single-event upsets (SOME). If a radiated particle hits the vicinity of the sensitive volume of N1, the generated electrons will be collected by the drain of N1, thus pulling down the potential of Q1. Since Q1 serves as the input signal for the second-stage inverter, it will cause the potential of Q2 to rise. When the amount of electrons collected by the drain of N1 exceeds a critical threshold, the potential of Q1 will flip from high to low, causing the potential of Q2 to flip from low to high, ultimately triggering a SOME in the circuit output.

[0035] Since transistors N1 and N2 are arranged adjacent to each other on the layout, if charge sharing occurs between the sensitive volumes of N1 and N2, some electrons generated by the radiated particles are collected by the drain of N1, which lowers the potential of Q1, and the potential of Q2 rises accordingly; other electrons are collected by the drain of N2, which lowers the potential of Q2. The final net effect is that charge sharing can, to some extent, offset the flipping trend of Q2 from low to high, and has the effect of suppressing single-event flip.

[0036] To quantify the charge-sharing effect, the charge-sharing probability between sensitive volumes N1 and N2 was simulated using the Geant4 software package. The radiating particles were set to protons with an energy of 100 MeV. The proton source emitted a uniform grid scan within a rectangular region covering both sensitive volumes N1 and N2, emitting a total of 5 × 10-1... 7 One proton. The simulation output data includes: proton number, proton incident position coordinates, and the identifier signal "Shared," indicating charge sharing between sensitive volumes N1 and N2. The simulation data is processed using MATLAB: the scanned area is divided into a fine grid; the number of charge sharing events within each grid cell is counted relative to the number of particle incident events within that cell; the ratio of the former to the latter is calculated as the charge sharing probability within that cell; the probabilities of charge sharing across all grid cells are summarized, and finally, a result is generated as shown below. Figure 9 The diagram shows the probability distribution of two-dimensional charge sharing.

[0037] Step 8: Change the transistor layout to generate a new layout. Repeat steps 5 to 7 to generate a two-dimensional distribution map of the probability of charge sharing between sensitive volumes of adjacent transistors under the new layout.

[0038] Specifically, the schematic diagram of the new map layout is as follows: Figure 10 As shown. Repeat steps 5 through 7 to construct a new circuit model ( Figure 11 Simulations were performed to obtain a two-dimensional distribution map of the charge sharing probability between the sensitive volumes of transistors N1 and N2 under the new layout, as shown below. Figure 12 As shown.

[0039] Step 9: Compare the two-dimensional distribution diagrams of charge sharing probability under different layouts. Combined with the layout area constraint, select the layout that is more conducive to reducing the risk of single-event upset at critical nodes and improving the overall resistance to single-event upset of the circuit under acceptable area cost, and use it as the final optimization scheme.

[0040] Specifically, the criteria for selecting layout optimization schemes are as follows: under the premise of meeting circuit performance and area constraints, priority is given to layouts that are more conducive to reducing the risk of single-event upsets at critical nodes due to charge sharing effects; if multiple layouts have similar effects, the layout areas are further compared and the one with the smallest area is selected.

[0041] Specifically, through comparison Figure 9 and Figure 12It can be seen that in the initial layout, the probability of charge sharing between the sensitive volumes of transistors N1 and N2 is at most about 4%; while in the new layout, due to the closer arrangement of the sensitive volumes of N1 and N2, the probability of charge sharing between them increases to at most about 7%. Given that the charge sharing effect between the sensitive volumes of N1 and N2 can effectively suppress single-event upsets at the circuit output node Q2, the new layout has better anti-single-event upset performance under the premise of meeting circuit performance and area constraints, and therefore it is selected as the final optimization scheme.

[0042] In summary, this invention aims to propose a method based on Geant4 Monte Carlo simulation to simulate the transport process of radiated particles in a circuit. It obtains the charge sharing probability distribution among the sensitive volumes of transistors under different layouts, providing a quantitative basis for selecting the optimal radiation-hardened layout and achieving efficient and accurate circuit hardening.

[0043] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for optimizing the layout of FinFET circuits against single-event upsets based on charge-sharing analysis, characterized in that, The charge-sharing effect between transistor sensitive volumes in the circuit layout was quantitatively evaluated using Geant4 simulations to optimize the circuit's resistance to single-event upsets; including: Step S1: Calibrate the FinFET device model using TCAD simulation and determine the single-tube sensitive volume; Step S2: Analyze the target circuit to identify sensitive nodes and generate an initial layout; Step S3: Construct a Geant4 circuit model based on the initial layout, locate sensitive nodes and determine the sensitive volume distribution of the circuit; Step S4: Statistically analyze and generate a two-dimensional distribution map of charge sharing probability among sensitive volumes of adjacent transistors using Monte Carlo simulation; Step S5: Iteratively change the layout and repeat the simulation. Select the layout that is more conducive to reducing the risk of single-event flip under the controllable area cost.

2. The FinFET circuit layout optimization method based on charge-sharing analysis as described in claim 1, characterized in that, Step S1 specifically includes: Step S11: Based on TCAD software, construct a three-dimensional device model according to the FinFET process parameters, simulate the electrical characteristics of the device, and complete the model calibration by comparing with the experimental test results; Step S12: Set the FinFET device to the bias state most sensitive to single-event upset, simulate the single-event transient current pulse generated in different regions of the single-event incident device, and determine the sensitive volume of the FinFET device based on the pulse amplitude distribution.

3. The FinFET circuit layout optimization method based on charge-sharing analysis as described in claim 2, characterized in that, During the TCAD simulation, the FinFET device is set to be in the off state, and a reverse-biased PN junction is formed between the drain and the substrate. This is the bias state most sensitive to single-event upsets. During TCAD simulation, a single particle is incident on different regions of the device along a direction perpendicular to the device surface. The corresponding single-particle transient current pulse is extracted, and the sensitive volume of the single-tube device is defined based on the pulse amplitude distribution.

4. The FinFET circuit layout optimization method based on charge-sharing analysis as described in claim 1, characterized in that, Step S2 specifically includes: Step S21: Analyze the target circuit schematic and determine the key circuit nodes that are sensitive to single-event upsets; Step S22: Based on the target circuit schematic, generate an initial transistor layout using the Cadence Virtuoso platform.

5. The FinFET circuit layout optimization method based on charge-sharing analysis as described in claim 1, characterized in that, Step S3 specifically includes: Step S31: Based on the Geant4 toolkit, construct a three-dimensional circuit model according to the FinFET process parameters, the FinFET process flow, and the generated initial layout. Step S32: In the constructed three-dimensional circuit model, locate the key circuit nodes that are sensitive to single-particle flip and the transistors that affect the key nodes, and map the determined single-transistor sensitive volume to the transistor to form the overall sensitive volume distribution of the circuit.

6. The FinFET circuit layout optimization method based on charge-sharing analysis as described in claim 5, characterized in that, When constructing the three-dimensional circuit model, the layered structure of the FinFET process is referenced, including the substrate, shallow trench isolation, fin structure, gate dielectric, gate, source / drain regions, metal interconnect layer, and passivation layer, to ensure that the model geometry is consistent with the process parameters.

7. The FinFET circuit layout optimization method based on charge-sharing analysis as described in claim 1, characterized in that, Step S4 specifically includes: In the Geant4 simulation, the particle source is set to perform grid scanning emission within a region covering the sensitive volume. The number of events in which the charge generated by a single incident particle is shared by multiple neighboring transistor sensitive volumes is counted, the charge sharing probability is calculated, and a two-dimensional distribution map of the charge sharing probability is generated.

8. The FinFET circuit layout optimization method based on charge-sharing analysis as described in claim 7, characterized in that, The particles emitted by the particle source are one or more of protons, neutrons, and heavy ions, and the energy is set according to the target radiation environment.

9. The FinFET circuit layout optimization method based on charge-sharing analysis as described in claim 7, characterized in that, The specific steps of generating the two-dimensional distribution map of charge sharing probability include: dividing the particle source scanning area into a grid, counting the number of charge sharing events in each grid cell and the number of particle incident events in that cell, calculating the ratio of the former to the latter as the charge sharing probability in that cell, summarizing the charge sharing probabilities in all grid cells, and drawing a two-dimensional distribution contour map.

10. The FinFET circuit layout optimization method based on charge-sharing analysis as described in claim 1, characterized in that, Step S5 specifically includes: Step S51: Change the transistor layout to generate a new layout. Repeat steps S3 to S4 to generate a two-dimensional distribution map of the probability of charge sharing between sensitive volumes of adjacent transistors under the new layout. Step S52: Compare the two-dimensional distribution diagrams of charge sharing probability under different layouts, and in combination with the layout area constraint, select the layout that is more conducive to reducing the risk of single-event upset at critical nodes and improving the overall resistance to single-event upset of the circuit under acceptable area cost, as the final optimization scheme.

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