Memory device including memory blocks performing sub-block operations

By employing a chip stacking structure and cell array structure with sub-block operation in the memory device, the problem of increased chip size in 3D NAND flash memory has been solved, thereby improving the performance and reliability of the memory device.

CN122157737APending Publication Date: 2026-06-05SAMSUNG ELECTRONICS CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
SAMSUNG ELECTRONICS CO LTD
Filing Date
2025-10-30
Publication Date
2026-06-05

AI Technical Summary

Technical Problem

As memory cell size decreases, the integration density of 3D NAND flash memory increases, leading to larger chip size, and the need for spare memory blocks affects reliability and availability.

Method used

By implementing sub-block operations on a single memory block in a memory device, including chip stack structures and cell array structures, multiple sub-blocks are used for erase, program, verify, and read operations, thereby reducing chip size and improving performance.

Benefits of technology

This enables a reduction in the chip size of memory devices while improving their performance and reliability, supporting the reliability, availability, and serviceability of memory controllers.

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Abstract

Memory devices are provided that include memory blocks that perform sub-block operations. The memory devices include a chip stack that includes a peripheral circuit structure and a cell array structure. The cell array structure includes a first cell chip and a second cell chip on the first cell chip. The first cell chip includes a plurality of first sub-blocks and the second cell chip includes a plurality of second sub-blocks. Each of the memory blocks is made up of a first sub-block and a corresponding second sub-block thereof. First word lines are connected to second word lines, respectively. In an erase operation of a selected first sub-block of a selected memory block among the memory blocks, first string select lines starting from a first bit line away from the first string select lines are sequentially floated with a delay at a level of a ground voltage.
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Citation Information

Patent Citations

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