Audio acquisition device and acquisition method

Abstract

The audio acquisition device comprises a first audio acquisition module, a second audio acquisition module, a logic scheduling module and a processing module. The first audio acquisition module works in an I2S master mode, outputs an N-bit first digital audio signal, a reference bit clock signal and a first left-right channel control signal; the second audio acquisition module works in an I2S slave mode and outputs an N-bit second digital audio signal under the triggering of a second left-right channel control signal. The logic scheduling module generates a second left-right channel control signal with a K-bit clock period offset based on the reference bit clock signal, and forms a combined data stream by making two signals time-sharing occupy the same physical data channel through hardware selection logic according to the combined logic state of the first left-right channel control signal and the second left-right channel control signal. The processing module receives the combined data stream and parses multiple original audio data. The scheme realizes multi-channel acquisition without increasing the number of physical channels, reduces the interface resource occupation and hardware cost.

Description

Technical Field

[0001] This invention relates to the field of audio processing technology, and in particular to an audio acquisition device and acquisition method. Background Technology

[0002] With the continuous development of audio processing technology, the demand for multi-channel audio acquisition is increasing in applications such as conference systems, in-vehicle audio, voice interaction devices, and professional recording. In these systems, the I2S (Inter-IC Sound) bus is often used as the digital audio transmission interface between the audio analog-to-digital converter and the processor.

[0003] In existing technologies, the I2S interface, as a commonly used serial digital audio transmission standard, typically includes a bit clock signal, left and right channel control signals, and a serial data line. In a typical stereo acquisition architecture, a single I2S channel generally only supports the acquisition of audio data from the left and right channels; that is, the digital audio data of the left and right channels is transmitted sequentially within one sampling period via the left and right channel control signals. This method can meet the basic audio acquisition needs of conventional consumer electronics products, but its scalability is limited in applications requiring the simultaneous acquisition of four or more audio signals.

[0004] To achieve multi-channel audio acquisition, existing technologies typically employ methods such as increasing the number of I2S physical interfaces, introducing multiple sets of serial data lines, or selecting dedicated audio processing chips that support multi-channel time-division multiplexing. However, these solutions often require more hardware interface resources or rely on dedicated chips with complex internal timing logic and higher costs, resulting in a complex system hardware structure, increased costs, and higher demands on the interface resources of the main control processor.

[0005] Therefore, how to reduce the hardware complexity and cost of audio acquisition equipment is a technical problem that urgently needs to be solved in the field of high-frequency audio processing technology.

[0006] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0007] In view of the problems in the prior art, the purpose of this invention is to provide an audio acquisition device and acquisition method, which overcomes the difficulties of the prior art and can solve the technical problems that the hardware devices used in the audio acquisition schemes of related technologies are both complex and costly.

[0008] The first aspect of this disclosure provides an audio acquisition device, which includes a first audio acquisition module, a second audio acquisition module, a logic scheduling module, and a processing module; The first audio acquisition module is configured to work in I2S master mode, and is used to acquire analog audio signals and output a first digital audio signal with a fixed bit width of N bits, and output a reference bit clock signal and a first left and right channel control signal. The second audio acquisition module is configured to work in I2S slave mode, and is used to receive the reference clock signal and the second left and right channel control signals, and output a second digital audio signal with a fixed bit width of N bits when triggered by the second left and right channel control signals. The logic scheduling module is connected to the sampling trigger terminals of the first audio acquisition module and the second audio acquisition module, as well as the processing module, respectively; The logic scheduling module receives the first left and right channel control signals and generates second left and right channel control signals with a K-bit clock cycle offset relative to the first left and right channel control signals based on the reference clock signal, where K... <N; The logic scheduling module is configured to output the generated second left and right channel control signals to the second audio acquisition module, so as to drive the second audio acquisition module to start outputting the second digital audio signal after a delay of K bits under the action of the reference clock signal, and according to the combined logic state of the first left and right channel control signals and the second left and right channel control signals, switch the output of the first digital audio signal or the second digital audio signal through hardware selection logic, so that the first digital audio signal and the second digital audio signal are time-division multiplexed and occupy the same physical data channel to form a merged data stream; The processing module is connected to the physical data channel and is configured to receive the merged data stream and parse multiple raw audio data from the merged data stream.

[0009] Optionally, N is 24 bits, where the high 16 bits of the first digital audio signal and the second digital audio signal are valid audio data, and the low 8 bits are padding bits; The processing module is specifically configured to parse four 16-bit valid audio data streams from a 32-bit merged data stream through shift and extraction operations, and then construct the merged data stream.

[0010] Optionally, the logic scheduling module has a counting unit inside, which is used to count the pulses of the reference clock signal; Combinational logic states include: When the count value of the counting unit reaches the threshold corresponding to the K-bit, the level of the second left and right channel control signal changes, and the hardware selection logic is triggered to switch from outputting the first digital audio signal to outputting the second digital audio signal.

[0011] Optionally, the merged data stream is presented on the physical data channel as follows: Within a single channel sampling period, the N-bit sequence of the first digital audio signal and the N-bit sequence of the second digital audio signal are sequentially included in the bit timing order, wherein the high K bits of each N-bit sequence are valid audio data; The processing module is specifically configured to extract multiple original audio data streams by performing shift and extraction operations on the merged data streams.

[0012] Optionally, N is 24 bits and K is 16 bits; The processing module is configured as follows: The high 16 bits of the corresponding first channel time slot in the merged data stream are identified as the first audio data; The lower 16 bits of the time slot corresponding to the first channel in the merged data stream are identified as the second audio data. The high 16 bits of the corresponding second channel time slot in the merged data stream are identified as the third audio data; The lower 16 bits of the corresponding second channel time slot in the merged data stream are identified as the fourth audio data. By restoring the data bit width, the identified first, second, third, and fourth audio data are converted into their corresponding original audio data.

[0013] Optionally, both the first audio acquisition module and the second audio acquisition module include a dual-channel analog-to-digital converter. The first digital audio signal includes first left channel audio data and first right channel audio data, and the second digital audio signal includes second left channel audio data and second right channel audio data.

[0014] Optionally, the logic scheduling module is implemented using a programmable logic device, and the hardware selection logic is a real-time selection circuit based on combinational logic circuits.

[0015] A second aspect of this disclosure provides an audio acquisition method, comprising: The first audio acquisition module operates in I2S master mode, acquiring analog audio signals and outputting a first digital audio signal with a fixed bit width of N bits, as well as a reference bit clock signal and a first left and right channel control signal. The logic scheduling module receives the first left and right channel control signals and generates second left and right channel control signals with a K-bit clock period offset relative to the first left and right channel control signals based on the reference clock signal, where K... <N; The logic scheduling module outputs the generated second left and right channel control signals to the second audio acquisition module to drive the second audio acquisition module to start outputting the second digital audio signal after a delay of K bits under the action of the reference clock signal; Based on the combined logical state of the first left and right channel control signals and the second left and right channel control signals, the logic scheduling module switches the output of the first digital audio signal or the second digital audio signal through hardware selection logic, so that the first digital audio signal and the second digital audio signal are time-division multiplexed and occupy the same physical data channel to form a merged data stream. The processing module parses multiple raw audio data streams from the merged data stream.

[0016] Optionally, a second left and right channel control signal with a K-bit clock period offset is generated based on the reference bit clock signal, including: The counting unit inside the logic scheduling module is used to count the pulses of the reference clock signal; When the count value of the counting unit reaches the threshold corresponding to the K-bit, the level of the second left and right channel control signal changes, and the hardware selection logic is triggered to switch from outputting the first digital audio signal to outputting the second digital audio signal.

[0017] Optionally, the merged data stream is presented on the physical data channel as follows: Within a single channel sampling period, the N-bit sequence of the first digital audio signal and the N-bit sequence of the second digital audio signal are sequentially included in the bit timing order, wherein the high K bits of each N-bit sequence are valid audio data; The processing module extracts multiple original audio data streams by performing shifting and extraction operations on the merged data streams.

[0018] Optionally, N is 24 bits and K is 16 bits; The high 16 bits of the corresponding first channel time slot in the merged data stream are identified as the first audio data; The lower 16 bits of the time slot corresponding to the first channel in the merged data stream are identified as the second audio data. The high 16 bits of the corresponding second channel time slot in the merged data stream are identified as the third audio data; The lower 16 bits of the corresponding second channel time slot in the merged data stream are identified as the fourth audio data. By restoring the data bit width, the identified first, second, third, and fourth audio data are converted into the corresponding original audio data.

[0019] The audio acquisition device and acquisition method proposed in this disclosure have the following advantages: The logic scheduling module receives the first left and right channel control signals and generates second left and right channel control signals with a K-bit clock cycle offset relative to the first left and right channel control signals based on the reference bit time signal. These second left and right channel control signals are output to the sampling trigger terminal of the second audio acquisition module, driving the second audio acquisition module to delay outputting the second digital audio signal by K bits, thereby achieving a time-division multiplexing arrangement of the first and second digital audio signals without overlap in time sequence. This technical feature provides a reliable timing basis for data multiplexing on a single physical data channel.

[0020] Furthermore, based on the combined logic states of the first and second left / right channel control signals, the logic scheduling module selects either the first or second digital audio signal to be output via hardware selection logic. This allows the two digital audio signals to occupy the same physical data channel in a time-sharing manner, forming a merged data stream. This structure enables the entire system to achieve synchronous acquisition of multiple audio signals using only one standard sampling interface of the processing module, significantly reducing the consumption of processor interface resources and lowering hardware connection complexity and cost.

[0021] The processing module connects to a single physical data channel, receiving the merged data stream, reference clock signal, and first left and right channel control signals, from which multiple raw audio data streams can be extracted. This solution achieves efficient acquisition and processing of multiple audio signals without increasing the number of physical channels, making it suitable for applications with limited interface resources and high requirements for multi-channel synchronization.

[0022] In summary, the embodiments disclosed herein, through the combination of the above-described structure and signal scheduling method, achieve the acquisition and transmission of multiple audio signals without changing the physical form of the I2S interface. At the same time, they can achieve corresponding technical effects in terms of reducing interface resource consumption, reducing system hardware complexity, and improving system integration.

[0023] It should be understood that the above general description and detailed description are exemplary and explanatory only, and do not limit this disclosure. Attached Figure Description

[0024] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0025] Figure 1 A hardware logic architecture diagram of an audio acquisition device provided in this disclosure embodiment; Figure 2 This invention discloses a block diagram showing the internal unit composition of a first audio acquisition module provided in an embodiment of the present invention. Figure 3 This invention discloses a block diagram showing the internal unit composition of a logic scheduling module provided in an embodiment of the present invention. Figure 4 A timing logic diagram of an audio acquisition device in a two-channel audio acquisition mode provided in this embodiment of the present disclosure; Figure 5 A timing logic diagram of an audio acquisition device in a four-channel audio acquisition mode provided in this embodiment of the disclosure; Figure 6 A flowchart illustrating an audio acquisition method provided by an embodiment of this disclosure is shown. Detailed Implementation

[0026] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0027] Figure 1 An architecture diagram of the audio acquisition device provided in this disclosure embodiment is shown below. Figure 1 As shown, the audio acquisition device provided in this embodiment may include a first audio acquisition module 10, a second audio acquisition module 20, a logic scheduling module 30, and a processing module 40. The modules can interact with each other via signal lines, circuit interfaces, or other forms of connection.

[0028] The first audio acquisition module 10 can be used to acquire at least one analog audio signal and convert the analog audio signal into a first digital audio signal. In some embodiments, the first audio acquisition module 10 can operate in I2S master mode, and while outputting the first digital audio signal, it can also output a reference clock signal BCLK for audio data transmission and a first left and right channel control signal LRCLK1.

[0029] The first digital audio signal can have a fixed data bit width, such as N bits. N can be set according to specific application requirements, and is not limited to a specific value.

[0030] The second audio acquisition module 20 can be used to acquire at least one analog audio signal and output a second digital audio signal after receiving a second left / right channel control signal provided externally. In some embodiments, the second audio acquisition module 20 can operate in I2S slave mode, which can receive a reference bit clock signal BCLK and a second left / right channel control signal LRCLK2 provided by the logic scheduling module 30, and output the second digital audio signal under the control of the second left / right channel control signal LRCLK2.

[0031] The data bit width of the second digital audio signal can be the same as that of the first digital audio signal, for example, both being a fixed bit width N.

[0032] The logic scheduling module 30 can be connected to the first audio acquisition module 10, the second audio acquisition module 20 and the processing module 40 respectively, and is used to schedule and control the timing signals and data output during the audio acquisition process.

[0033] In some embodiments, the logic scheduling module 30 can receive the first left and right channel control signal LRCLK1, and generate a second left and right channel control signal LRCLK2 with a certain clock cycle offset relative to the first left and right channel control signal LRCLK1 based on the reference bit clock signal BCLK. The clock cycle offset can be represented by K bit clock cycles, where K can be less than N, and the specific value of K can be set according to the audio data organization method.

[0034] In addition, the logic scheduling module 30 can also control the output of the first digital audio signal or the second digital audio signal by selecting logic according to different combinations of the first left and right channel control signal LRCLK1 and the second left and right channel control signal LRCLK2, so that digital audio signals from different sources are alternately output to the same physical data channel in time, thereby forming a merged data stream.

[0035] In some embodiments, the logic scheduling module 30 may be implemented using a programmable logic device, such as a programmable logic device (PLD), a complex programmable logic device (CPLD), or an erasable programmable logic device (EPLD), but is not limited to these.

[0036] The processing module 40 can be connected to the physical data channel to receive the merged data stream output by the logic scheduling module 30. In some embodiments, the processing module 40 can perform processing operations such as buffering, shifting, extracting, or reassembling on the received merged data stream to parse out multiple original audio data streams.

[0037] The processing module 40 can be a digital signal processor, a microcontroller, an audio processing chip, or other processing unit with audio data processing capabilities, and its specific implementation is not limited.

[0038] In this embodiment, the logic scheduling module 30 generates a second left / right channel control signal LRCLK2 that is time-shifted from the first left / right channel control signal LRCLK1, thereby controlling the second audio acquisition module 20 to output the second digital audio signal at the corresponding timing position. This design allows audio data from different audio acquisition modules to be organized and differentiated in a time sequence, achieving a non-overlapping time-division arrangement. Thus, without changing the I2S interface hardware structure of the main control chip, it achieves effective carrying and transmission of multiple audio data streams, significantly improving the utilization rate of existing I2S bus resources.

[0039] Furthermore, the logic scheduling module 30, through selection control logic, enables digital audio signals from multiple audio acquisition modules to occupy the same physical data channel in a time-division multiplexing manner during different time periods, forming a merged data stream. This structure allows for the acquisition and output of multiple digital audio signals using only a single I2S channel. Compared to expanding the number of acquisition channels by adding serial data lines or setting additional I2S interfaces, this implementation reduces the number of interfaces required and lowers the complexity of hardware circuit design. Simultaneously, since it eliminates the need for dedicated audio chips supporting multi-channel time-division multiplexing and multiple I2S interfaces, it reduces the system's reliance on high-performance audio codec chips, thereby helping to control overall hardware costs.

[0040] Finally, the processing module 40 receives the merged data stream through a single physical data channel and extracts the multiple original audio data streams from it. Since the multiple digital audio signals are acquired and transmitted based on the same I2S channel, each digital audio signal has a consistent clock reference and a defined relative timing relationship, which helps maintain the consistency of the multiple digital audio signals on the time axis. This characteristic helps improve the stability and reliability of subsequent audio processing algorithms when jointly analyzing multiple audio data streams in applications such as conferencing systems, array audio processing, or multi-channel recording.

[0041] In summary, the embodiments disclosed herein, through the combination of the above-described structure and signal scheduling method, achieve the acquisition and transmission of multiple digital audio signals without changing the physical form of the I2S interface. At the same time, they can achieve corresponding technical effects in terms of reducing interface resource consumption, reducing system hardware complexity, and improving system integration.

[0042] In some embodiments of this disclosure, the first audio acquisition module 10 is used to acquire at least one analog audio signal and output a first digital audio signal under the action of the corresponding first left and right channel control signal LRCLK1.

[0043] Specifically, such as Figure 2 As shown, the first audio acquisition module 10 may include an audio input unit 11, an analog-to-digital converter 12, and a digital output unit 13. The audio input unit 11 is used to receive analog audio signals input from an external audio source, the analog-to-digital converter 12 is used to convert the analog audio signals into first digital audio signals, and the digital output unit 13 is used to output the converted digital audio signals to the physical data channels under the control of the first left and right channel control signal LRCLK1.

[0044] In some embodiments, the first audio acquisition module 10 operates under the drive of the first left and right channel control signal LRCLK1. When the first left and right channel control signal LRCLK1 is in a predetermined logic state, the first audio acquisition module 10 outputs the first digital audio signal corresponding to the channel. Thus, the first digital audio signal output by the first audio acquisition module 10 occupies the time position corresponding to the first left and right channel control signal LRCLK1 in the time sequence.

[0045] In some embodiments, the first audio acquisition module 10 can serve as a reference audio acquisition module, and its output first digital audio signal is located in a predetermined time period or time slot in the merged data stream, which is used to distinguish it from digital audio signals from other audio acquisition modules.

[0046] In some embodiments of this disclosure, the second audio acquisition module 20 (such as...) Figure 1 (As shown) is used to acquire at least one analog audio signal that is different from the first audio acquisition module 10, and outputs a second digital audio signal under the action of the second left and right channel control signal LRCLK2 which has a timing difference from the first audio acquisition module 10.

[0047] Specifically, the second audio acquisition module 20 may be structurally the same as or similar to the first audio acquisition module 10, or may be configured with different parameters according to application requirements. The second audio acquisition module 20 may also include an audio input unit, an analog-to-digital conversion unit, and a digital output unit (not shown in the figure), used to complete the conversion and output of analog audio signals to second digital audio signals.

[0048] In some embodiments, the second audio acquisition module 20 operates under the control of the second left and right channel control signal LRCLK2, wherein the second left and right channel control signal LRCLK2 is offset by a preset clock period K relative to the first left and right channel control signal LRCLK1. This clock period offset K causes the timing of the second digital audio signal output by the second audio acquisition module 20 to differ from the timing of the first digital audio signal output by the first audio acquisition module 10.

[0049] Therefore, the second digital audio signal output by the second audio acquisition module 20 can form a time-division arrangement with the first digital audio signal in the same physical data channel, thereby avoiding the overlap of different digital audio signals in time.

[0050] In this disclosure, such as Figure 1As shown, the first audio acquisition module 10 and the second audio acquisition module 20 work together under the control of the logic scheduling module 30. The logic scheduling module 30 provides the first left and right channel control signal LRCLK1 to the first audio acquisition module 10 and provides the second left and right channel control signal LRCLK2 with a clock period offset K to the second audio acquisition module 20, so that the digital audio signals output by the two are staggered in time sequence.

[0051] Through the above-mentioned collaborative method, the first digital audio signal and the second digital audio signal from the first audio acquisition module 10 and the second audio acquisition module 20 can be output in a predetermined order in the same physical data channel to form a merged data stream, which is then received and parsed by the subsequent processing module 40.

[0052] It should be noted that the number, structure, and type of audio signal acquired by the first audio acquisition module 10 and the second audio acquisition module 20 are not limited. In other embodiments, more audio acquisition modules can be set and expanded using a similar timing control method.

[0053] In some embodiments of this disclosure, N represents the fixed bit width of the first digital audio signal and the second digital audio signal. The fixed bit width is the number of data bits occupied by the first digital audio signal and the second digital audio signal output by the first audio acquisition module 10 and the second audio acquisition module 20 respectively within a single channel sampling period.

[0054] In some embodiments, N can be a pre-defined integer value used to limit the transmission length of the first and second digital audio signals on the physical data channel. By uniformly setting N, digital audio signals from different audio acquisition modules have a consistent data format in the time dimension, facilitating subsequent merging and parsing.

[0055] It should be noted that the value of N is not limited. In different embodiments, N can be configured according to the audio sampling accuracy, system bandwidth or the resolution capability of the processing module, as long as the first digital audio signal and the second digital audio signal have the same fixed bit width.

[0056] In some embodiments of this disclosure, K is used to represent the clock cycle offset introduced by the logic scheduling module 30 based on the reference bit clock signal BCLK.

[0057] Specifically, K represents the number of bit clock cycles that the second left and right channel control signal LRCLK2 is delayed in time relative to the first left and right channel control signal LRCLK1, where K is less than N.

[0058] In some embodiments, by setting K, the second audio acquisition module 20 starts outputting the second digital audio signal after the first audio acquisition module 10 outputs the first digital audio signal, delayed by K bits, within a single channel sampling period. Thus, the first and second digital audio signals are staggered in time sequence.

[0059] It should be noted that the specific value of K can be set according to the requirements of the audio data arrangement, and is not limited to a fixed value. As long as K and N satisfy the preset relationship, the time-division arrangement of digital audio signals on the same physical data channel can be achieved.

[0060] In some embodiments of this disclosure, the logic scheduling module 30 is used to process the first left and right channel control signals LRCLK1 from the first audio acquisition module 10 and output corresponding scheduling control signals to the second audio acquisition module 20 and the physical data channel.

[0061] In some embodiments, such as Figure 3 As shown, the logic scheduling module 30 may include at least a portion of the following functional units: Control signal receiving unit 31 is used to receive the first left and right channel control signal LRCLK1; Timing generation unit 32 is used to generate a second left and right channel control signal LRCLK2 with a clock period offset K based on the reference clock signal BCLK; Select control unit 33 is used to control the output paths of the first digital audio signal and the second digital audio signal based on the combined logic state of the first left and right channel control signal LRCLK1 and the second left and right channel control signal LRCLK2.

[0062] The above functional units can be implemented in hardware logic or in programmable logic, and their specific structural form is not limited.

[0063] In some implementations, the logic scheduling module 30 discretizes the time based on the reference bit clock signal BCLK, thereby introducing a preset clock period offset K. Specifically, when the logic scheduling module 30 detects a low state change in the first left and right channel control signal LRCLK1, it delays the signal according to the number of bit clocks corresponding to K, and outputs the second left and right channel control signal when the delay reaches a low state.

[0064] In this way, the second left and right channel control signal LRCLK2 is offset from the first left and right channel control signal LRCLK1 by a certain clock cycle, thereby providing the second audio acquisition module with a different output timing reference than the first audio acquisition module.

[0065] In some embodiments, the logic scheduling module 30 schedules the output content on the physical data channel based on the combined logic state of the first left and right channel control signal LRCLK1 and the second left and right channel control signal LRCLK2.

[0066] Specifically, when the combinational logic state meets the first preset condition, the logic scheduling module 30 controls the physical data channel to output the first digital audio signal; when the combinational logic state meets the second preset condition, the logic scheduling module 30 controls the physical data channel to output the second digital audio signal.

[0067] This allows the first and second digital audio signals to be output sequentially in time on the same physical data channel, forming a merged data stream.

[0068] In some embodiments, the logic scheduling module 30 may be implemented using discrete logic circuits, programmable logic devices, or other hardware structures capable of performing timing control and signal selection functions.

[0069] It should be noted that the specific implementation method, internal circuit structure and signal generation strategy of the logic scheduling module 30 do not constitute a limitation of this disclosure, as long as it can generate a second left and right channel control signal LRCLK2 with timing offset based on the reference clock signal BCLK, and complete the time-division scheduling of the first digital audio signal and the second digital audio signal.

[0070] In some embodiments of this disclosure, the logic scheduling module 30 is further provided with a counting unit 34, which is used to count pulses of the reference bit clock signal BCLK to obtain discrete count values ​​corresponding to the bit clock.

[0071] Specifically, the counting unit 34, driven by the reference bit clock signal BCLK, accumulates and counts each bit clock pulse, forming a continuously changing count value within a single channel sampling period. The count value is used to characterize the current bit timing position of the digital audio signal in the physical data channel.

[0072] In some embodiments, the logic scheduling module 30 determines the combinational logic state based on the relationship between the count value of the counting unit 34 and a preset threshold. The preset threshold corresponds to bit K and is used to indicate the timing offset position of the second left / right channel control signal LRCLK2 relative to the first left / right channel control signal LRCLK1.

[0073] When the count value of the counting unit 34 reaches the threshold corresponding to the K-bit, the logic scheduling module 30 controls the second left and right channel control signal LRCLK2 to undergo a level transition. This level transition is used to indicate the second audio acquisition module 20 (e.g., Figure 1(As shown) Enter the corresponding second digital audio signal output timing.

[0074] At the same time, when the level of the second left and right channel control signal LRCLK2 changes, the logic scheduling module 30 also synchronously triggers the state switching of the hardware selection logic, so that the physical data channel switches from outputting the first digital audio signal to outputting the second digital audio signal.

[0075] In this way, the level change of the second left and right channel control signal LRCLK2 is consistent with the switching action of the hardware selection logic in time, thereby ensuring that the first digital audio signal and the second digital audio signal are output in time-division according to the predetermined bit timing relationship on the physical data channel.

[0076] It should be noted that the specific implementation, counting method, and threshold setting method of the counting unit 34 are not limited, as long as it can count the pulses of the reference clock signal BCLK and trigger the level transition of the second left and right channel control signal LRCLK2 and the synchronous switching of the hardware selection logic when the count value reaches the threshold corresponding to the K position.

[0077] In some embodiments of this disclosure, both the first digital audio signal and the second digital audio signal are configured with a fixed bit width of N bits, where N is 24 bits.

[0078] In some embodiments, the high 16 bits of the first and second digital audio signals are used to carry valid audio data, i.e., the actual sound sample values, while the low 8 bits are set as padding bits to ensure that the bit width of the first and second digital audio signals on the physical data channel is consistent with other signals or for internal system alignment. The padding bits can be fixed to 0 or set according to other preset rules, but this will not affect the correctness of the high 16 bits of valid audio data.

[0079] In some embodiments, such as Figure 1 As shown, the processing module 40 performs shift and extraction operations on the merged data stream output from the logic scheduling module 30 to parse multi-channel audio data. Specifically: Processing module 40 first receives the continuous bit sequence in the merged data stream according to the physical data channel transmission order; The processing module 40 performs time-division parsing of the 24-bit first digital audio signal and the second digital audio signal on the physical data channel according to the sampling period of each channel; During the parsing process, the high 16 bits of each digital audio signal are identified as valid audio data, while the low 8 bits are ignored or treated as padding bits. By using shift operations, the effective bits corresponding to the 24-bit sequences of different channels are combined into four 16-bit digital audio data, corresponding to the first, second, third and fourth digital audio data respectively. The extracted four 16-bit audio data streams can be further used for subsequent mixing, noise reduction, or storage operations, but this embodiment only describes the extraction method.

[0080] It should be noted that the displacement and extraction operations can be implemented through hardware logic or through software or firmware within the processing module. The specific implementation method does not constitute a limitation of this disclosure, as long as it can correctly separate and extract four channels of 16-bit valid audio data from the merged data stream.

[0081] In this embodiment, the lower 8 bits of the first and second digital audio signals are used as padding bits. Their main function is to meet the alignment requirements of the physical data channel for bit width, or to facilitate internal logic processing. In application scenarios where audio accuracy requirements are not high, such as ordinary conference systems, in-vehicle voice transmission, or daily audio acquisition, the presence of padding bits will not have a significant impact on audio quality, while simplifying the parsing and alignment operations of the data stream by the processing module 40.

[0082] In this way, while maintaining the integrity of the high 16 bits of valid audio data, multiple audio signals can be transmitted through a single I2S channel, achieving a low-cost and simple-to-design multi-channel audio acquisition solution.

[0083] In some embodiments of this disclosure, the merged data stream is presented on the physical data channel as follows: Within a single channel sampling period, the N-bit sequence of the first digital audio signal and the N-bit sequence of the second digital audio signal are sequentially included in the bit timing order. The high K bits of each N-bit sequence carry valid audio data, and the low bits (NK) can be used as padding bits for bit width alignment or internal logic processing.

[0084] In some embodiments, N is set to 24 bits and K is set to 16 bits, meaning that the high 16 bits of each digital audio signal contain valid audio data, and the low 8 bits are padding bits. The padding bits can be fixed to 0, or they can be used to meet the alignment or register mapping requirements of the processing module 40, while not affecting the sound quality in scenarios with low audio requirements, such as ordinary meetings, in-vehicle voice, or low bit rate recording applications.

[0085] In some embodiments, the processing module 40 parses and merges the data streams through shift and extraction operations to separate multiple raw audio data streams. The specific operations are as follows: First channel processing: The high 16 bits of the corresponding first channel time slot in the merged data stream are identified as the first audio data, and the low 16 bits of the same time slot are identified as the second audio data; Second channel processing: The high 16 bits of the corresponding second channel time slot in the merged data stream are identified as the third audio data, and the low 16 bits of the same time slot are identified as the fourth audio data. Data bit width restoration: The processing module 40 can restore the bit width or convert the format of the four identified audio data to generate the corresponding original audio data for subsequent mixing, noise reduction or storage operations; The bit width restoration method can be hardware register mapping, shift operation or software processing according to system requirements, but there is no limit to the specific implementation method. It is only necessary to ensure that each audio data channel is completely and effectively parsed.

[0086] Through the above structural design and operation method, the above-mentioned multi-channel digital audio signals maintain an orderly bit timing relationship when transmitted on a single I2S channel, realizing the synchronous acquisition and time-division parsing of four audio signals, while ensuring the integrity of high-bit valid data and the flexibility of low-bit padding, which is conducive to realizing multi-channel audio acquisition in a low-cost hardware solution.

[0087] In one embodiment of this disclosure, both the first digital audio signal and the second digital audio signal carry at least two audio data streams.

[0088] Specifically, both the first audio acquisition module 10 and the second audio acquisition module 20 use a multi-channel analog-to-digital converter (ADC) chip (e.g., a dual-channel ADC).

[0089] When the first audio acquisition module 10 is working, its output first digital audio signal includes first left channel (Left Channel) audio data and first right channel (Right Channel) audio data. Similarly, the second digital audio signal output by the second audio acquisition module 20 includes second left channel audio data corresponding to the left channel and second right channel audio data corresponding to the right channel. Under the standard I2S protocol, each digital audio signal originally occupies a complete channel bit slot within a single sampling period (Frame).

[0090] In order to integrate the above four audio data streams within a single physical data channel, the logic scheduling module 30 executes the following scheduling logic: While the first left and right channel control signal LRCLK1 is at the first level (e.g., high level, representing the left channel time slot), the logic scheduling module 30 first activates the path of the first audio acquisition module 10. At this time, the high K bits of the "first left channel audio data" corresponding to the left channel in the first digital audio signal are sent to the physical data channel; Subsequently, based on the transition of the second left and right channel control signal LRCLK2 with a K-bit clock cycle offset, the logic scheduling module 30 quickly switches the path to the second audio acquisition module 20, so that the high K bit of the "second left channel audio data" corresponding to the left channel in the second digital audio signal is sent into the physical data channel immediately after its low bit.

[0091] When LRCLK1 flips to the second level (e.g., low level, representing the right channel time slot), the above process is repeated: the physical data channel loads the "first right channel audio data" corresponding to the right channel from the first digital audio signal in the first half, and the "second right channel audio data" corresponding to the right channel from the second digital audio signal in the second half. In this way, the four audio data channels that originally required two sets of I2S interfaces to transmit are compressed and merged into the left and right channel time slots of a single physical data channel. After receiving the merged data stream, the processing module 40 can completely restore these four independent audio data channels according to the preset bit slot allocation rules through simple shift and extraction commands. This implementation method doubles the number of acquisition channels without increasing hardware pins, greatly improving the system integration.

[0092] In one embodiment of this disclosure, such as Figure 4 As shown, taking the two-channel audio acquisition mode as an example. The first audio acquisition module 10 (e.g.) Figure 1 As shown, the device operates in I2S master mode as the master device, and the reference clock signal BCLK and the first left and right channel control signal LRCLK1 generated by it directly drive the system timing.

[0093] Within each channel sampling cycle (e.g., a 32-bit clock cycle), the first audio acquisition module 10 outputs a first digital audio signal SDIN1 with a fixed bit width of N=24 bits. Since the logic scheduling module 30 does not introduce the second left / right channel control signal LRCLK2 with a clock cycle offset of K at this time, the physical data channel SDIN fully carries the data stream output by the first audio acquisition module 10.

[0094] During the left channel cycle (e.g., LRCLK1 is high), SDIN1 outputs 24 bits of valid audio data, padding the lower bits with 8 bits of zero to complete the 32-bit slot. The processing module 40 receives the merged data stream and identifies it as the first audio data channel. Similarly, during the right channel cycle (LRCLK1 is low), the data output by SDIN1 is identified as the second audio data channel. This two-channel audio acquisition mode is suitable for scenarios requiring high sampling accuracy (full 24 bits) and only needing to acquire two audio channels.

[0095] In the second embodiment of this disclosure, such as Figure 5As shown, taking the four-channel audio acquisition mode as an example, synchronous acquisition of four digital audio signals using a single I2S channel is achieved. For example, the logic scheduling module 30 uses a low-cost EPLD or PLD chip and implements dynamic switching of physical data channels through a Very High Speed ​​Integrated Circuit Hardware Description Language (VHDL) program. Its design goal is to achieve real-time gating and switching of physical data channels based on combinational logic circuits.

[0096] like Figure 5 As shown, the logic scheduling module 30 generates a second left and right channel control signal LRCLK2 with a clock cycle offset of K=16. Specifically, the logic scheduling module 30 can internally preset an audio acquisition enable signal audio_start_con. When this signal is in an invalid state (e.g., audio_start_con='1'), the physical data channel SDIN is forcibly pulled low, stopping data transmission. When audio acquisition starts (audio_start_con='0'), the logic scheduling module 30 establishes the following gating mapping based on the real-time level combination of the first left and right channel control signal LRCLK1 and the second left and right channel control signal LRCLK2 with a K-bit offset: First time division interval (LRCLK1='1', LRCLK2='0'): At this time, it is in the first half of the left channel cycle. The logic scheduling module 30 selects the first digital audio signal SDIN1 and outputs it to the physical bus, corresponding to the high 16 bits of the first left channel audio data.

[0097] Second time division interval (LRCLK1='1', LRCLK2='1'): At this time, due to the level transition after LRCLK2 completes the K-bit offset, the logic scheduling module 30 instantly switches the bus occupancy right to the second digital audio signal SDIN2, corresponding to the high 16 bits of the second left channel audio data.

[0098] The third time-division interval (LRCLK1='0', LRCLK2='1'): At this time, it is in the first half of the right channel cycle, and the gating logic returns to SDIN1, corresponding to the high 16 bits of the first right channel audio data.

[0099] The fourth time-division interval (LRCLK1='0', LRCLK2='0'): the lower half of the right channel cycle, the bus is occupied by SDIN2, and the high 16 bits of the second right channel audio data are output at this time.

[0100] The hardware selection logic is implemented using parallel conditional assignment statements, ensuring signal switching is completed within nanoseconds and guaranteeing the alignment of multiple digital audio signals on the time axis. Its code logic is as follows: SDIN <= SDIN1 when (LRCLK1 = '1' and LRCLK2 = '0' and audio_start_con= '0') else SDIN2 when (LRCLK1 = '1' and LRCLK2 = '1' and audio_start_con = '0')else SDIN1 when (LRCLK1 = '0' and LRCLK2 = '1' and audio_start_con = '0')else SDIN2 when (LRCLK1 = '0' and LRCLK2 = '0' and audio_start_con = '0')else '0'; -- Outputs a zero level when the default state or when acquisition stops.

[0101] The processing module 40 may be configured with a buffer unit, such as a FIFO register, for temporary storage and sequential reading of the merged data stream.

[0102] In one specific embodiment, the processing module 40 performs shift and extraction operations on the merged data stream based on preset bit width parameters and channel timing relationships to reconstruct the four original audio data streams, specifically including: First, for the 32-bit merged data stream in the corresponding first channel time slot, the processing module 40 takes the high 16 bits (BIT16~BIT31) as valid audio data, which corresponds to the first left channel audio data and is identified as the first audio data. The data bit width is restored by padding the low bits with zeros. Second, for the 32-bit merged data stream in the first channel time slot, after shifting it left by 16 bits, the processing module 40 takes the high 16 bits (BIT16~BIT31) as valid audio data, extracts it as the second audio data, which corresponds to the second left channel audio data, and restores the data bit width by padding the low bits with zeros. Third, for the 32-bit merged data stream in the corresponding second channel time slot, the processing module 40 takes the high 16 bits (BIT16~BIT31) as valid audio data, which corresponds to the first right channel audio data and is identified as the third audio data. The data bit width is restored by padding the low bits with zeros. Fourth, for the 32-bit merged data stream in the second channel time slot, after shifting it left by 16 bits, the processing module 40 extracts the high 16 bits (BIT16~BIT31) as valid audio data and uses them as the fourth audio data, which corresponds to the second right channel audio data. The data bit width is restored by padding the low bits with zeros.

[0103] In some embodiments, although the physical output of the first audio acquisition module 10 and the second audio acquisition module 20 is still 24 bits, in order to fit two audio data channels into a limited 32-bit bus slot, the timing design actively discards the lower 8 bits of audio data with poor sound quality and susceptibility to interference from each digital audio signal, retaining only the higher 16 bits. This method doubles the number of acquisition channels by utilizing time-domain redundancy without changing the physical form of the main control chip interface.

[0104] Figure 6 A flowchart illustrating an embodiment of the audio acquisition method provided in this disclosure is shown. This audio acquisition method can be implemented based on the aforementioned audio acquisition device and is used to achieve synchronous acquisition and transmission of multiple audio signals without increasing the number of I2S physical interfaces. Figure 6 As shown, this audio acquisition method includes, but is not limited to, the following steps: Step 610: The first audio acquisition module operates in I2S master mode, acquires analog audio signals and outputs a first digital audio signal with a fixed bit width of N bits, and outputs a reference bit clock signal and a first left and right channel control signal. Step 620: The logic scheduling module receives the first left and right channel control signals and generates second left and right channel control signals with a K-bit clock period offset relative to the first left and right channel control signals based on the reference clock signal, where K... <N; Step 630: The logic scheduling module outputs the generated second left and right channel control signals to the second audio acquisition module to drive the second audio acquisition module to start outputting the second digital audio signal after a delay of K bits under the action of the reference clock signal; Step 640: The logic scheduling module, based on the combined logic state of the first left and right channel control signals and the second left and right channel control signals, switches the output of the first digital audio signal or the second digital audio signal through hardware selection logic, so that the first digital audio signal and the second digital audio signal are time-division multiplexed and occupy the same physical data channel to form a merged data stream. Step 650: The processing module parses the multiple raw audio data streams from the merged data stream.

[0105] The audio acquisition method provided in this disclosure achieves multi-channel audio acquisition and transmission by performing bit-level time-division multiplexing of multiple audio data within the same physical data channel. This avoids configuring a separate physical data channel for each audio channel, thereby reducing the number of system pins and hardware costs. This audio acquisition method is based on a standard I2S bit clock and corresponding left and right channel control signals, achieving data multiplexing through bit-level timing offset. It does not require increasing the bit clock frequency and is compatible with existing audio codecs and processor interfaces.

[0106] The K-bit clock cycle offset between the first and second left / right channel control signals is precisely controlled by the logic scheduling module, ensuring a stable and predictable bit structure in the merged data stream. The processing module can then parse the data through simple shifting and extraction operations. Furthermore, by using the high K bits of the N-bit audio data as the valid audio data and the remaining bits as padding, parallel acquisition of multiple audio streams is achieved with acceptable audio quality degradation. This is particularly suitable for applications such as speech recognition, environmental monitoring, and control-related audio input.

[0107] In summary, the embodiments of this disclosure, through the above-described audio acquisition method, achieve the acquisition and transmission of multiple digital audio signals without changing the physical form of the I2S interface. At the same time, it can achieve corresponding technical effects in terms of reducing interface resource consumption, reducing system hardware complexity, and improving system integration.

[0108] In some implementations, the fixed bit width N of the first digital audio signal is 24 bits, meaning 24 bits of data are transmitted per channel sampling period. Driven by the first left and right channel control signal LRCLK1, the first audio acquisition module outputs data according to the MSB priority order of the I2S protocol. When LRCLK1 is at a first level (e.g., high), it outputs the 24-bit data corresponding to the left channel; when LRCLK1 toggles to a second level (e.g., low), it outputs the 24-bit data corresponding to the right channel.

[0109] In one specific embodiment, the process of generating a second left and right channel control signal with a K-bit clock cycle offset based on a reference clock signal is implemented in the following manner.

[0110] The logic scheduling module has a counting unit inside, which is connected to the reference clock signal and is used to count the number of pulses of the reference clock signal bit by bit.

[0111] At the beginning of each channel sampling period, the counting unit is reset to the initial count value and increments bit by bit under the drive of the reference bit clock signal.

[0112] When the count value of the counting unit reaches the threshold corresponding to the clock cycle offset K, the logic scheduling module controls the second left and right channel control signals to undergo a level transition, thereby delaying the second left and right channel control signals relative to the first left and right channel control signals by K clock cycles.

[0113] At the same time, when the level of the second left and right channel control signal changes, the logic scheduling module synchronously triggers the state switching of the hardware selection logic, causing the hardware selection logic to switch from outputting the first digital audio signal to outputting the second digital audio signal.

[0114] In this way, the generation of the second left and right channel control signals and the switching of hardware selection logic are completed at the same timing node, thereby ensuring that the bit-level boundaries of the first digital audio signal and the second digital audio signal in the merged data stream are clear and the timing is consistent, avoiding bit overlap or bit loss.

[0115] In one specific embodiment, the merged data stream is presented in the following form on the physical data channel.

[0116] Within a single channel sampling period, the merged data stream, following the bit timing order of the reference bit clock signal, sequentially contains an N-bit sequence of the first digital audio signal and an N-bit sequence of the second digital audio signal.

[0117] Each N-bit sequence is transmitted according to a predetermined bit arrangement, with the high K bits used to carry valid audio data and the remaining bits used as padding or invalid bits.

[0118] Because the first digital audio signal and the second digital audio signal have a K-bit bit clock offset in time, and are output in a time-division manner within the same physical data channel through hardware selection logic, the merged data stream has a fixed and predictable data arrangement order in the bit-level structure.

[0119] Upon receiving the merged data stream, the processing module performs shifting, masking, and extraction operations on the merged data stream based on the pre-configured N and K values ​​and channel timing relationships. Only the high K bits of each N-bit sequence are extracted and processed to obtain multiple original audio data streams.

[0120] In this way, the processing module can reliably recover multiple audio data from a single physical data channel without performing complex synchronization or resampling operations.

[0121] In one specific embodiment, N is set to 24 bits and K is set to 16 bits.

[0122] In this configuration, the high 16 bits of each digital audio signal are used to carry the valid audio data, and the low 8 bits are used as padding bits to meet the requirements of bit timing alignment and time-division multiplexing.

[0123] When processing the merged data stream, the processing module parses the data in different slots according to the channel timing, specifically including: The high 16 bits of the corresponding first channel time slot in the merged data stream are identified as the first audio data; The lower 16 bits of the time slot corresponding to the first channel in the merged data stream are identified as the second audio data. The high 16 bits of the corresponding second channel time slot in the merged data stream are identified as the third audio data; The lower 16 bits of the time slot corresponding to the second channel in the merged data stream are identified as the fourth audio data.

[0124] After completing the above identification, the processing module performs data bit width restoration processing on the first, second, third, and fourth audio data respectively. For example, by using sign extension or zero extension, the 16-bit valid audio data is restored to the target bit width required by the processing system, thereby obtaining the corresponding original audio data.

[0125] This implementation method achieves simultaneous acquisition and recovery of four audio data channels without increasing the number of physical data channels. It features clear parsing rules, low implementation complexity, and is suitable for application scenarios with multiple audio inputs but moderate audio accuracy requirements.

[0126] Through the above steps, this implementation method achieves synchronous acquisition and analysis of multiple audio signals on a single physical data channel, which has the advantages of simple structure, low cost and low interface resource consumption.

[0127] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. An audio acquisition device, characterized in that, It includes a first audio acquisition module, a second audio acquisition module, a logic scheduling module, and a processing module; The first audio acquisition module is configured to work in I2S master mode, and is used to acquire analog audio signals and output a first digital audio signal with a fixed bit width of N bits, and output a reference bit clock signal and a first left and right channel control signal. The second audio acquisition module is configured to work in I2S slave mode, and is used to receive the reference clock signal and the second left and right channel control signal, and output a second digital audio signal with a fixed bit width of N bits when triggered by the second left and right channel control signal; The logic scheduling module is connected to the sampling trigger terminals of the first audio acquisition module, the second audio acquisition module, and the processing module, respectively. The logic scheduling module is used to receive the first left and right channel control signals and generate second left and right channel control signals with a K-bit clock period offset relative to the first left and right channel control signals based on the reference clock signal, where K... <N; The logic scheduling module is configured to output the generated second left and right channel control signals to the second audio acquisition module, thereby driving the second audio acquisition module to start outputting the second digital audio signal after a delay of K bits under the action of the reference clock signal, and to switch the output of the first digital audio signal or the second digital audio signal through hardware selection logic according to the combined logic state of the first left and right channel control signals and the second left and right channel control signals, so that the first digital audio signal and the second digital audio signal are time-division multiplexed and occupy the same physical data channel to form a merged data stream; The processing module is connected to the physical data channel and is configured to receive the merged data stream and parse multiple original audio data streams from the merged data stream.

2. The audio acquisition device according to claim 1, characterized in that, N is 24 bits, and the high 16 bits of the first digital audio signal and the second digital audio signal are valid audio data, while the low 8 bits are padding bits. The processing module is specifically configured to parse four 16-bit valid audio data streams from the 32-bit merged data stream through shift and extraction operations, and then construct the merged data stream.

3. The audio acquisition device according to claim 1, characterized in that, The logic scheduling module has a counting unit inside, which is used to count the pulses of the reference clock signal; The combinational logic states include: When the count value of the counting unit reaches the threshold corresponding to the K-bit, the second left and right channel control signals undergo a level transition, and simultaneously trigger the hardware selection logic to switch from outputting the first digital audio signal to outputting the second digital audio signal.

4. The audio acquisition device according to claim 1, characterized in that, The merged data stream appears on the physical data channel as follows: Within a single channel sampling period, the N-bit sequence of the first digital audio signal and the N-bit sequence of the second digital audio signal are sequentially included in the bit timing order, wherein the high K bits of each N-bit sequence are valid audio data; The processing module is specifically configured to extract multiple original audio data from the merged data stream by performing displacement and extraction operations.

5. The audio acquisition device according to claim 4, characterized in that, N is 24 bits, and K is 16 bits; The processing module is configured as follows: The high 16 bits of the time slot corresponding to the first channel in the merged data stream are identified as the first audio data. The lower 16 bits of the time slot corresponding to the first channel in the merged data stream are identified as the second audio data. The high 16 bits of the corresponding second channel time slot in the merged data stream are identified as the third audio data; The lower 16 bits of the time slot corresponding to the second channel in the merged data stream are identified as the fourth audio data. By restoring the data bit width, the identified first, second, third, and fourth audio data are converted into the corresponding original audio data.

6. The audio acquisition device according to claim 1, characterized in that, Both the first audio acquisition module and the second audio acquisition module include a dual-channel analog-to-digital converter. The first digital audio signal includes first left channel audio data and first right channel audio data, and the second digital audio signal includes second left channel audio data and second right channel audio data.

7. The audio acquisition device according to claim 1, characterized in that, The logic scheduling module is implemented using programmable logic devices, and the hardware selection logic is a real-time selection circuit based on combinational logic circuits.

8. An audio acquisition method, characterized in that, include: The first audio acquisition module operates in I2S master mode, acquiring analog audio signals and outputting a first digital audio signal with a fixed bit width of N bits, as well as a reference bit clock signal and a first left and right channel control signal. The logic scheduling module receives the first left and right channel control signals and generates second left and right channel control signals with a K-bit clock period offset relative to the first left and right channel control signals based on the reference clock signal, where K... <N; The logic scheduling module outputs the generated second left and right channel control signals to the second audio acquisition module to drive the second audio acquisition module to start outputting the second digital audio signal after a delay of K bits under the action of the reference clock signal; The logic scheduling module, based on the combined logic state of the first left and right channel control signals and the second left and right channel control signals, switches the output of the first digital audio signal or the second digital audio signal through hardware selection logic, so that the first digital audio signal and the second digital audio signal are time-division multiplexed and occupy the same physical data channel to form a merged data stream. The processing module parses multiple raw audio data streams from the merged data stream.

9. The audio acquisition method according to claim 8, characterized in that, The generation of second left and right channel control signals with a K-bit clock cycle offset based on the reference clock signal includes: The counting unit inside the logic scheduling module is used to count the pulses of the reference clock signal; When the count value of the counting unit reaches the threshold corresponding to the K-bit, the second left and right channel control signals undergo a level transition, and simultaneously trigger the hardware selection logic to switch from outputting the first digital audio signal to outputting the second digital audio signal.

10. The audio acquisition method according to claim 8, characterized in that, The merged data stream appears on the physical data channel as follows: Within a single channel sampling period, the N-bit sequence of the first digital audio signal and the N-bit sequence of the second digital audio signal are sequentially included in the bit timing order, wherein the high K bits of each N-bit sequence are valid audio data; The processing module performs shift and extraction operations on the merged data stream to parse out multiple channels of the original audio data.

11. The audio acquisition method according to claim 10, characterized in that, N is 24 bits, and K is 16 bits; The high 16 bits of the time slot corresponding to the first channel in the merged data stream are identified as the first audio data. The lower 16 bits of the time slot corresponding to the first channel in the merged data stream are identified as the second audio data. The high 16 bits of the corresponding second channel time slot in the merged data stream are identified as the third audio data; The lower 16 bits of the time slot corresponding to the second channel in the merged data stream are identified as the fourth audio data. By restoring the data bit width, the identified first, second, third, and fourth audio data are converted into the corresponding original audio data.

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